void StopAudio()
{
StopAudioDMA();
SPI3->CR2&=~SPI_CR2_TXDMAEN; // Disable I2S TX DMA request.
DisableInterrupt(DMA1_Stream7_IRQn);
CallbackFunction=NULL;
}
/*
* Setup the timer 0 to generate the tick interrupts at the required frequency.
*/
static void prvSetupTimerInterrupt( void )
{
unsigned long ulCompareMatch;
/* Calculate the match value required for our wanted tick rate. */
ulCompareMatch = 1000000 / configTICK_RATE_HZ;
/* Protect against divide by zero. Using an if() statement still results
in a warning - hence the #if. */
#if portPRESCALE_VALUE != 0
{
ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
}
#endif
DisableInterrupts();
InitInterruptController();
DisableInterrupt(64);
RegisterInterrupt(64, vTickISR, NULL);
pRegs->CTL = 0x003E0000;
pRegs->LOD = 1000 - 1;
pRegs->RLD = 1000 - 1;
pRegs->DIV = portTIMER_PRESCALE;
pRegs->CLI = 0;
pRegs->CTL = 0x003E00A2;
EnableInterrupt(64);
}
void CPdd6410Uart::PostInit()
{
DWORD dwCount=0;
m_HardwareLock.Lock();
m_pReg6410Uart->Write_UCON(0); // Set to Default;
DisableInterrupt(S6410UART_INT_RXD | S6410UART_INT_TXD | S6410UART_INT_ERR | S6410UART_INT_MODEM);
// Mask all interrupt.
while ((GetInterruptStatus() & (S6410UART_INT_RXD | S6410UART_INT_TXD | S6410UART_INT_ERR | S6410UART_INT_MODEM))!=0 && dwCount <MAX_RETRY)
{
InitReceive(TRUE);
InitLine(TRUE);
ClearInterrupt(S6410UART_INT_RXD | S6410UART_INT_TXD | S6410UART_INT_ERR | S6410UART_INT_MODEM);
dwCount++;
}
ASSERT((GetInterruptStatus() & (S6410UART_INT_RXD | S6410UART_INT_TXD | S6410UART_INT_ERR | S6410UART_INT_MODEM))==0);
m_HardwareLock.Unlock();
CSerialPDD::PostInit();
CeSetPriority(m_dwPriority256);
#ifdef DEBUG
if ( ZONE_INIT )
{
m_pReg6410Uart->DumpRegister();
}
#endif
ThreadStart(); // Start IST.
}
status_t
VirtioQueue::Interrupt()
{
CALLED();
DisableInterrupt();
while (fRingUsedIndex != fRing.used->idx)
Finish();
EnableInterrupt();
return B_OK;
}
BOOL CPdd6410Uart::InitialEnableInterrupt(BOOL bEnable )
{
m_HardwareLock.Lock();
if (bEnable)
{
EnableInterrupt(S6410UART_INT_RXD | S6410UART_INT_ERR | S6410UART_INT_MODEM);
}
else
{
DisableInterrupt(S6410UART_INT_RXD | S6410UART_INT_ERR | S6410UART_INT_MODEM);
}
m_HardwareLock.Unlock();
return TRUE;
}
VirtioQueue::VirtioQueue(VirtioDevice* device, uint16 queueNumber,
uint16 ringSize)
:
fDevice(device),
fQueueNumber(queueNumber),
fRingSize(ringSize),
fRingFree(ringSize),
fRingHeadIndex(0),
fRingUsedIndex(0),
fStatus(B_OK),
fIndirectMaxSize(0)
{
fDescriptors = new(std::nothrow) TransferDescriptor*[fRingSize];
if (fDescriptors == NULL) {
fStatus = B_NO_MEMORY;
return;
}
uint8* virtAddr;
phys_addr_t physAddr;
fAreaSize = vring_size(fRingSize, device->Alignment());
fArea = alloc_mem((void **)&virtAddr, &physAddr, fAreaSize, 0,
"virtqueue");
if (fArea < B_OK) {
fStatus = fArea;
return;
}
memset(virtAddr, 0, fAreaSize);
vring_init(&fRing, fRingSize, virtAddr, device->Alignment());
for (uint16 i = 0; i < fRingSize - 1; i++)
fRing.desc[i].next = i + 1;
fRing.desc[fRingSize - 1].next = UINT16_MAX;
if ((fDevice->Features() & VIRTIO_FEATURE_RING_INDIRECT_DESC) != 0)
fIndirectMaxSize = 128;
for (uint16 i = 0; i < fRingSize; i++) {
fDescriptors[i] = new TransferDescriptor(this, fIndirectMaxSize);
if (fDescriptors[i] == NULL || fDescriptors[i]->InitCheck() != B_OK) {
fStatus = B_NO_MEMORY;
return;
}
}
DisableInterrupt();
device->SetupQueue(fQueueNumber, physAddr);
}
bool ProvideAudioBufferWithoutBlocking(void *samples,int numsamples)
{
if(NextBufferSamples) return false;
DisableInterrupt(DMA1_Stream7_IRQn);
NextBufferSamples=samples;
NextBufferLength=numsamples;
if(!DMARunning) StartAudioDMAAndRequestBuffers();
EnableInterrupt(DMA1_Stream7_IRQn);
return true;
}
void timer_init( void )
{
DisableInterrupt(64);
g_VectorTable[64].pfnHandler=tickISR;
timerRegs->CTL = 0x003E0000;
timerRegs->LOD = 1000000/OS_TICKS_PER_SEC - 1;
timerRegs->RLD = 1000000/OS_TICKS_PER_SEC - 1;
timerRegs->DIV = 0xF9;
timerRegs->CLI = 0;
timerRegs->CTL = 0x003E00A2;
EnableInterrupt(64);
}
int main(void)
{
uint8 test[64],i;
DisableInterrupt();
sys_init();
EnableInterrupt();
for(;;)
{
//Process_Event();
}
// for(i=0;i<64;i++)
// {
// test[i]=i;
// }
// /********************send test***********************/
//
// while(1)
// {
// A7139_StrobeCmd(CMD_PLL);
// delay_us(1);
// A7139_WriteFIFO(test,64);
// delay_us(1);
// A7139_StrobeCmd(CMD_TX);
// delay_us(1);
// while(GIO2);
// //delay_ms(11); delay_ms(1000);
// LED1_REV();
// delay_ms(50);
// }
/*******************************************************/
/*****************receive test**************************///ÓÃÖжϲâ½ÓÊÕ
// while(1)
// {
// A7139_StrobeCmd(CMD_PLL);
// delay_us(2);
// A7139_StrobeCmd(CMD_RX);
// delay_us(1);
// while(GIO1);
// A7139_ReadFIFO(DataRecv,64);
// LED2_REV();
// }
/*******************************************************/
}
NTSTATUS
BalloonInterruptDisable(
IN WDFINTERRUPT WdfInterrupt,
IN WDFDEVICE WdfDevice
)
{
PDEVICE_CONTEXT devCtx = NULL;
UNREFERENCED_PARAMETER( WdfInterrupt );
TraceEvents(TRACE_LEVEL_VERBOSE, DBG_PNP, "--> %s\n", __FUNCTION__);
devCtx = GetDeviceContext(WdfDevice);
DisableInterrupt(devCtx);
TraceEvents(TRACE_LEVEL_VERBOSE, DBG_PNP, "<-- %s\n", __FUNCTION__);
return STATUS_SUCCESS;
}
void S3C2450DISP::SetVisibleSurface( GPESurf *pTempSurf, BOOL bWaitForVBlank)
{
static int timeoutcnt=0;
DWORD we;
#ifdef HIGH_PRIORITY_INTR
int iPriority;
HANDLE hThread;
hThread = GetCurrentThread();
iPriority = CeGetThreadPriority(hThread);
CeSetThreadPriority(hThread, DISPDRV_IST_PRIORITY);
#endif
S3C2450Surf *pSurf = (S3C2450Surf *) pTempSurf;
EnterCriticalSection(&m_CS);
// assume Synchronous to VSYNC
EnableInterrupt();
we = WaitForSingleObject(m_hVSYNCInterruptEvent,1000/*INFINITE*/);
DisableInterrupt();
InterruptDone(m_dwVSYNCSysIntr);
if(we != WAIT_OBJECT_0)
{
timeoutcnt++;
RETAILMSG(1,(TEXT("Surface Flipping Time Out %d !!!\n"), timeoutcnt));
for(int i=0;i<78;i++)
RETAILMSG(1,(TEXT("0x%08X = 0x%08X\n"),(DWORD*)((DWORD*)m_pLCDReg + i),*(DWORD*)((DWORD*)m_pLCDReg + i)));
RETAILMSG(1,(TEXT("saved_x=%d"),saved_x));
RETAILMSG(1,(TEXT("saved_y=%d"),saved_y));
RETAILMSG(1,(TEXT("saved_width=%d"),saved_width));
RETAILMSG(1,(TEXT("saved_height=%d"),saved_height));
while(1);
}
if(pSurf->m_bIsOverlay == FALSE)
{
//RETAILMSG(1,(TEXT("pSurf->OffsetInVideoMemory()=0x%08X\n"),pSurf->OffsetInVideoMemory()));
m_pVisibleSurface = pSurf;
m_pLCDReg->VIDW00ADD0B0 = (UINT32)(pSurf->OffsetInVideoMemory() + IMAGE_FRAMEBUFFER_DMA_BASE);
// buffer end address
m_pLCDReg->VIDW00ADD1B0 = (UINT32)(pSurf->OffsetInVideoMemory() + IMAGE_FRAMEBUFFER_DMA_BASE) + (LCD_XSIZE_TFT*LCD_YSIZE_TFT*2);
// buffer size
m_pLCDReg->VIDW00ADD2B0 = (0<<VIDWxADD2_OFFSET_SIZE_S)|(LCD_XSIZE_TFT*2);
}
else
{
m_pLCDReg->VIDW01ADD0 = (UINT32)(pSurf->OffsetInVideoMemory() + IMAGE_FRAMEBUFFER_DMA_BASE);
// buffer end address
m_pLCDReg->VIDW01ADD1 = (UINT32)(pSurf->OffsetInVideoMemory() + IMAGE_FRAMEBUFFER_DMA_BASE) +
(pSurf->Width()*pSurf->Height()*2);
// buffer size
m_pLCDReg->VIDW01ADD2 = (0<<VIDWxADD2_OFFSET_SIZE_S)|(pSurf->Width()*2);
}
RETAILMSG(DBGLCD, (TEXT("S3C2450DISP::SetVisibleSurface\r\n")));
LeaveCriticalSection(&m_CS);
#ifdef HIGH_PRIORITY_INTR
CeSetThreadPriority(hThread, iPriority);
#endif
}
void FlashOperation(UINT32 op, void* addr, UINT32 data32)
{
//UINT32 status;
// NVMADDR only accept Physical Address
NVMADDR = ConvertToPhysicalAddress(addr);
#if 0 && defined(DEBUG)
SerialPrint("FlashOperation / ");
if (op == FLASH_WORD_WRITE)
{
SerialPrint("Write Address 0x");
SerialPrintNumber(NVMADDR,16);
SerialPrint("\r\n");
mLED_1_Toggle();
}
if (op == FLASH_PAGE_ERASE)
{
SerialPrint("Erase Address 0x");
SerialPrintNumber(NVMADDR,16);
SerialPrint("\r\n");
mLED_2_Toggle();
}
#endif
// Load data into NVMDATA register
NVMDATA = data32;
// Suspend or Disable all Interrupts
//status = DisableInterrupt();
// Enable Flash Write/Erase Operations
// 1-Select Flash operation to perform
// Enable writes to WR bit and LVD circuit
NVMCON = _NVMCON_WREN_MASK | op;
// 2-Wait for LVD to become stable (at least 6us).
Delayus(7);
// 3-Write unlock sequence before the WR bit is set
NVMKEY = 0xAA996655;
NVMKEY = 0x556699AA;
// 4-Start the operation (WR=1)
NVMCONSET = _NVMCON_WR_MASK;
// 5-Wait for operation to complete (WR=0)
while (NVMCON & _NVMCON_WR_MASK);
// 6-Disable Flash Write/Erase operations
NVMCONCLR = _NVMCON_WREN_MASK;
// Restore Interrupts if necessary
#if 0
if (status & 1)
{
EnableInterrupt();
}
else
DisableInterrupt();
#endif
#if 0
// Return NVMERR and LVDERR Error Status Bits
if (NVMCON & (_NVMCON_WRERR_MASK | _NVMCON_LVDERR_MASK))
{
while (1)
{
mLED_2_Toggle();
DelayUs(500);
}
}
#endif
}
int USBTesting()
{
UINT ch; // channel number
UINT TX_Status;
CHAR *dma_src_addr;
char Continue_test = 1;
//cyli++ 01/17/07
if (IS_16_ENDPT()) {
printf("16 end-points\n");
} else if (IS_10_ENDPT()) {
printf("10 end-points\n");
} else if (IS_4_ENDPT()) {
printf("4 end-points\n");
} else {
printf("Error end-point number!\n");
printf("DEV_INFO = 0x%08x", readw(UDC_DEVINFO) & ENDPT_NUM_MASK);
}
// CY+ to fix program reload Socle phy hang up problem
#ifdef UDC_SOCLE_PHY
ASSERT_SOFT_POR();
#if 0
isr_time_value = 0;
isr_waiting_time = 1;
setup_1ms_timer(1);
#else
MSDELAY(1);
#endif
while (isr_time_value != isr_waiting_time);
DEASSERT_SOFT_POR();
#endif
#ifdef UDC_SOCLE_PHY
#if 0
isr_time_value = 0;
isr_waiting_time = 8;
setup_1ms_timer(8);
#else
MSDELAY(8);
#endif
while (isr_time_value != isr_waiting_time);
// SET_PHY_16_BIT();
#endif
ResetFlag = 0;
bIsConnected = VBUS_OK();
// if (bIsConnected)
// printf(" -> USB VBus connect\n");
// else
// printf(" -> USB VBus disconnect");
// enable interrupt
INT0_ENABLE(LDK_INTC_UDC);
// setup interrupt handler
connectInterrupt( LDK_INTC_UDC, UDCIintHandler, NULL);
INT0_SET_MASK(LDK_INTC_UDC);
while (1) {
// ;printf("\n USB cable disconnected!\n");
SOFT_DISCONNECT();
// wait for plugin stable on vbus
// printf("\nWait for USB Host connect...");
// while ( !bIsConnected );
//CY++ for checking USB Host connect waiting
int wait=0;
while ( !bIsConnected ){
MSDELAY(60);
printf("%4d", wait);
wait++;
if(wait > 100)
return USB_NO_CONNECT_ERROR;
printf("\b\b\b\b");
}
#ifdef UDC_SOCLE_PHY
ASSERT_SOFT_POR();
#if 0
isr_time_value = 0;
isr_waiting_time = 1;
setup_1ms_timer(1);
#else
MSDELAY(1);
#endif
while (isr_time_value != isr_waiting_time);
DEASSERT_SOFT_POR();
#endif
#ifdef UDC_SOCLE_PHY
#if 0
isr_time_value = 0;
isr_waiting_time = 8;
setup_1ms_timer(8);
#else
MSDELAY(8);
#endif
while (isr_time_value != isr_waiting_time);
// SET_PHY_16_BIT();
#endif
initUDCController(); // initialize UDC Controller
initUDCTestingEnv(); // initialize UDC testing environment
SOFT_CONNECT();
;//printf("\n USB cable connected!\n");
uNeedDoProcCtrlBlockNum = 0;
while ( bIsConnected ) {
// check ENP 0 transmit request
if ( uNeedDoProcCtrlBlockNum > 0 ) {
int dma_size;
// dma done now, polling for empty data set
if (!( readw(UDC_TX0BUF) & TxFULL)) {
// critical section
DisableInterrupt();
uNeedDoProcCtrlBlockNum--;
dma_src_addr = CtrlInBuffer + uCurrentCtrlBlockNum++ * uCurrentCtrlPacketSize;
if ( uControlDataSize > uCurrentCtrlPacketSize ) {
dma_size = uCurrentCtrlPacketSize;
}
else {
dma_size = uControlDataSize;
}
// calculate remaining bytes need transfer
uControlDataSize -= dma_size;
writew( dma_size, UDC_TX0STAT );
writew( virt_to_phy((u32_t)dma_src_addr) , UDC_DMA0LM_IADDR );
writew( ENP_DMA_START , UDC_DMA0CTLI );
EnableInterrupt();
// set ACK--after we have overwritten the previously incorrect data
writew( readw( UDC_TX0CON ) & ~TxNAK, UDC_TX0CON );
}
}
if (Continue_test){
printf("Done\n");
printf("USB initialize...Done\n");
printf("HandShaking...Done\n");
printf("Waiting for Bulk Read/Write test...\n");
printf("Remove Socle USB Bulk device Hardware from Windows and USB cable to Exit !!!\n");
Continue_test = 0;
}
// check channel group transmit request
for (ch = 0; ch < NUM_OF_USB_CHANNEL; ch++) {
// check each Bulk_IN End Point transmit request
if ( ChannelSet[ch].uLoopbackCount > 0 ) {
if (ChannelSet[ch].bBulkDMAOnGoing == false) {
// check buffer is available for transmit data
TX_Status = readw(UDC_TXBUF(ChannelSet[ch].uBulk_IN)); // get buffer status
if ((TX_Status & TxFULL) == 0) {
#if 0
if ((TX_Status & TxDS0) == 0)
DEBUG_OUT('0');
if ((TX_Status & TxDS1) == 0)
DEBUG_OUT('1');
#endif
//DEBUG_OUT('i');
// enter critical section, protect share variable
DisableInterrupt();
//DEBUG_OUT('+');
ChannelSet[ch].uLoopbackCount--;
// get transmit buffer address & move buffer to next position
dma_src_addr = ChannelSet[ch].pBulkInBuffer + ChannelSet[ch].uCurrentBulkInBlockNum * uBulkBlockSize;
// setup DMA
writew( ChannelSet[ch].sBulkBlockSizeBuffer[ChannelSet[ch].uCurrentBulkInBlockNum],
UDC_TXSTAT(ChannelSet[ch].uBulk_IN) ); // write transmit count
writew( virt_to_phy((u32_t)dma_src_addr), // set transmit buffer pointer
UDC_DMALM_IADDR(ChannelSet[ch].uBulk_IN) );
writew( ENP_DMA_START , UDC_DMACTRLI(ChannelSet[ch].uBulk_IN) ); // start transmit DMA
// move to next buffer
ChannelSet[ch].uCurrentBulkInBlockNum = ++ChannelSet[ch].uCurrentBulkInBlockNum % uMaxBlockNumber;
#if 0
WAIT_DMA_DONE(UDC_TXSTAT(ChannelSet[ch].uBulk_IN));
#endif
#if 0
for (delay = 0; delay < 1000; delay++) {
TX2_DMAOnGoing = true;
}
#endif
ChannelSet[ch].bBulkDMAOnGoing = true;
//DEBUG_OUT('-');
EnableInterrupt();
// leave critical section
}
}
}
// check each Intr_IN End Point transmit request
if ( ChannelSet[ch].uIntrINCount > 0 ) {
// if (!( readw(UDC_TXBUF(ChannelSet[ch].uIntr_IN)) & TxFULL)) {
if (ChannelSet[ch].bIntrDMAOnGoing == false) {
// critical section
DisableInterrupt();
ChannelSet[ch].uCurrentIntrInBlockNum--;
dma_src_addr = ChannelSet[ch].pIntrInBuffer + ChannelSet[ch].uCurrentIntrInBlockNum * INTR_BLOCK_SIZE;
EnableInterrupt();
writew( INTR_BLOCK_SIZE, UDC_TXSTAT(ChannelSet[ch].uIntr_IN) );
writew( virt_to_phy((u32_t)dma_src_addr), UDC_DMALM_IADDR(ChannelSet[ch].uIntr_IN) );
writew( ENP_DMA_START, UDC_DMACTRLI(ChannelSet[ch].uIntr_IN) );
ChannelSet[ch].bIntrDMAOnGoing = true;
#if 0
WAIT_DMA_DONE(UDC_DMACTRLI(ChannelSet[ch].uIntr_IN) );
#endif
ChannelSet[ch].uCurrentBulkInBlockNum = ++ChannelSet[ch].uCurrentBulkInBlockNum % MAX_INTR_NUM;
}
}
}
}
// CY+ for disconnect detect and exit testing program
printf ("USB Host disconnected !!!\n");
printf ("Press Y to continue and any other Key to exit? ");
char i;
i=getchar();
if((i!='Y')&&(i!='y'))
{
printf ("\n");
return UPF_TEST_SUCCESS;
}
else
Continue_test = 1;
}
// leave usb test now, should never been here
return USB_UNKONW_ERROR;
}
HardwareLayer::TeensyDigitalPin::~TeensyDigitalPin()
{
DisableInterrupt();
}
HardwareLayer::SDLDigitalPin::~SDLDigitalPin()
{
DisableInterrupt();
}
//
//Create a thread,and put the thread's control block into array g_pKThreadQueue,
//and update the corresponding queue.
//If failed,it returns 0,otherwise,returns the created kernal thread's ID.
//
DWORD CreateKThread(DWORD dwStackSize, //Thread's stack size.
DWORD dwFlags, //Flags.
DWORD dwPriority, //Priority.
LPKTHREAD_ROUTINE pStartAddress, //Start running address.
LPVOID pData, //Parameter.
LPVOID /*pReserved*/) //Reserved.
{
DWORD dwKThreadID = 0x00000000;
struct __KTHREAD_CONTROL_BLOCK* pControlBlock = NULL;
LPVOID pStackPointer = NULL;
BOOL bFind = FALSE;
RoundTo4k(dwStackSize); //Round the stack size to 4k times.
pControlBlock = (struct __KTHREAD_CONTROL_BLOCK*) KMemAlloc(dwStackSize,KMEM_SIZE_TYPE_4K);
if(NULL == pControlBlock) //If can not allocate the memory.
{
return dwKThreadID;
}
MemZero((LPVOID)pControlBlock,dwStackSize); //Zero the memory allocated just now.
pControlBlock->pKThreadRoutine = pStartAddress; //Members initialization.
pControlBlock->dwKThreadPriority = dwPriority;
pControlBlock->pData = pData;
pControlBlock->wCurrentMsgNum = 0x0000;
pControlBlock->wHeader = 0x0000;
pControlBlock->wTrial = 0x0000;
//DisableInterrupt(); //Disable interrupt.
// ****************
for(dwKThreadID = 0;dwKThreadID < MAX_KTHREAD_NUM;dwKThreadID ++)
{
if(0 == g_bKThreadQueueStatus[dwKThreadID]) //Find a free control block slot.
{
bFind = TRUE;
break;
}
}
if(FALSE == bFind) //If can not find a free control block slot.
{
KMemFree((LPVOID)pControlBlock,KMEM_SIZE_TYPE_4K,dwStackSize); //Free the memory.
return 0L;
}
DisableInterrupt(); //Disable interrupt.
//******************
g_pKThreadQueue[dwKThreadID] = pControlBlock;
g_bKThreadQueueStatus[dwKThreadID] = 1; //Set the occupied flag.
dwKThreadID ++; //Increase the KThreadID.
pControlBlock->dwKThreadID = dwKThreadID;
pControlBlock->dwStackSize = dwStackSize;
switch(dwFlags) //Update the proper kernal thread queues.
//Insert the created kernal thread into
//the status queue.
{
case KTHREAD_STATUS_BLOCKED: //Insert into blocked queue.
pControlBlock->dwKThreadStatus = KTHREAD_STATUS_BLOCKED;
pControlBlock->pNext = g_pBlockedQueue;
g_pBlockedQueue = pControlBlock;
break;
case KTHREAD_STATUS_SUSPEND: //Insert it into suspended queue.
pControlBlock->dwKThreadStatus = KTHREAD_STATUS_SUSPEND;
pControlBlock->pNext = g_pSuspendQueue;
g_pSuspendQueue = pControlBlock;
break;
default: //All other status,insert into ready queue.
case KTHREAD_STATUS_READY:
case KTHREAD_STATUS_RUNNING:
pControlBlock->dwKThreadStatus = KTHREAD_STATUS_READY;
pControlBlock->pNext = g_pReadyQueue;
g_pReadyQueue = pControlBlock;
break;
}
#ifdef __I386__ //Update the x86 CPU's context.
pControlBlock->dwESP = (DWORD)pControlBlock + dwStackSize;
pControlBlock->dwEIP = (DWORD)pStartAddress;
pControlBlock->dwEFlags = 512; //*****************************
#else
#endif
EnableInterrupt(); //Enable interrupt.
//*****************
return dwKThreadID;
}
int USBTesting()
{
UINT ch; // channel number
UINT TX_Status;
CHAR *dma_src_addr;
#ifdef UDC_SOCLE_PHY
ASSERT_SOFT_POR();
#if 0
isr_time_value = 0;
isr_waiting_time = 1;
setup_1ms_timer(1);
#else
MSDELAY(1);
#endif
while (isr_time_value != isr_waiting_time);
DEASSERT_SOFT_POR();
#endif
#ifdef UDC_SOCLE_PHY
#if 0
isr_time_value = 0;
isr_waiting_time = 8;
setup_1ms_timer(8);
#else
MSDELAY(8);
#endif
while (isr_time_value != isr_waiting_time);
// SET_PHY_16_BIT();
#endif
ResetFlag = 0;
bIsConnected = VBUS_OK();
// if (bIsConnected)
// printf(" -> USB VBus connect\n");
// else
// printf(" -> USB VBus disconnect");
// enable interrupt
INT0_ENABLE(LDK_INTC_UDC);
// setup interrupt handler
connectInterrupt( LDK_INTC_UDC, UDCIintHandler, NULL);
INT0_SET_MASK(LDK_INTC_UDC);
while (1) {
// ;printf("\n USB cable disconnected!\n");
SOFT_DISCONNECT();
// wait for plugin stable on vbus
printf("\nWait for USB Host connect...");
// while ( !bIsConnected );
//CY++ for checking USB Host connect waiting
int wait=0;
while ( !bIsConnected ){
MSDELAY(60);
printf("%4d", wait);
wait++;
if(wait > 100)
return USB_NO_CONNECT_ERROR;
printf("\b\b\b\b");
}
#ifdef UDC_SOCLE_PHY
ASSERT_SOFT_POR();
#if 0
isr_time_value = 0;
isr_waiting_time = 1;
setup_1ms_timer(1);
#else
MSDELAY(1);
#endif
while (isr_time_value != isr_waiting_time);
DEASSERT_SOFT_POR();
#endif
#ifdef UDC_SOCLE_PHY
#if 0
isr_time_value = 0;
isr_waiting_time = 8;
setup_1ms_timer(8);
#else
MSDELAY(8);
#endif
while (isr_time_value != isr_waiting_time);
// SET_PHY_16_BIT();
#endif
initUDCController(); // initialize UDC Controller
initUDCTestingEnv(); // initialize UDC testing environment
SOFT_CONNECT();
;//printf("\n USB cable connected!\n");
uNeedDoProcCtrlBlockNum = 0;
for (ch = 0; ch < NUM_OF_USB_CHANNEL; ch++) {
ChannelSet[ch].uLoopbackCount = 0;
ChannelSet[ch].uIntrINCount = 0;
// start receive from Bulk_OUT pipe
writew(virt_to_phy( (u32_t)ChannelSet[ch].pBulkOutBuffer), UDC_DMALM_OADDR(ChannelSet[ch].uBulk_OUT));
writew( ENP_DMA_START, UDC_DMACTRLO(ChannelSet[ch].uBulk_OUT));
}
while ( bIsConnected ) {
// check ENP 0 transmit request
if ( uNeedDoProcCtrlBlockNum > 0 ) {
int dma_size;
// dma done now, polling for empty data set
if (!( readw(UDC_TX0BUF) & TxFULL)) {
// critical section
DisableInterrupt();
uNeedDoProcCtrlBlockNum--;
dma_src_addr = CtrlInBuffer + uCurrentCtrlBlockNum++ * uCurrentCtrlPacketSize;
if ( uControlDataSize > uCurrentCtrlPacketSize ) {
dma_size = uCurrentCtrlPacketSize;
}
else {
dma_size = uControlDataSize;
}
// calculate remaining bytes need transfer
uControlDataSize -= dma_size;
writew( dma_size, UDC_TX0STAT );
writew( virt_to_phy((u32_t)dma_src_addr) , UDC_DMA0LM_IADDR );
writew( ENP_DMA_START , UDC_DMA0CTLI );
EnableInterrupt();
// set ACK--after we have overwritten the previously incorrect data
writew( readw( UDC_TX0CON ) & ~TxNAK, UDC_TX0CON );
}
}
// check channel group transmit request
for (ch = 0; ch < NUM_OF_USB_CHANNEL; ch++) {
// check each Bulk_IN End Point transmit request
if ( ChannelSet[ch].uLoopbackCount > 0 ) {
if (ChannelSet[ch].bBulkDMAOnGoing == false) {
// check buffer is available for transmit data
TX_Status = readw(UDC_TXBUF(ChannelSet[ch].uBulk_IN)); // get buffer status
if ((TX_Status & TxFULL) == 0) {
#if 0
if ((TX_Status & TxDS0) == 0)
DEBUG_OUT('0');
if ((TX_Status & TxDS1) == 0)
DEBUG_OUT('1');
#endif
//DEBUG_OUT('i');
// enter critical section, protect share variable
DisableInterrupt();
//DEBUG_OUT('+');
ChannelSet[ch].uLoopbackCount--;
// get transmit buffer address & move buffer to next position
dma_src_addr = ChannelSet[ch].pBulkInBuffer + ChannelSet[ch].uCurrentBulkInBlockNum * uBulkBlockSize;
// setup DMA
writew( ChannelSet[ch].sBulkBlockSizeBuffer[ChannelSet[ch].uCurrentBulkInBlockNum],
UDC_TXSTAT(ChannelSet[ch].uBulk_IN) ); // write transmit count
writew( virt_to_phy((u32_t)dma_src_addr), // set transmit buffer pointer
UDC_DMALM_IADDR(ChannelSet[ch].uBulk_IN) );
writew( ENP_DMA_START , UDC_DMACTRLI(ChannelSet[ch].uBulk_IN) ); // start transmit DMA
// move to next buffer
ChannelSet[ch].uCurrentBulkInBlockNum = ++ChannelSet[ch].uCurrentBulkInBlockNum % uMaxBlockNumber;
#if 0
WAIT_DMA_DONE(UDC_TXSTAT(ChannelSet[ch].uBulk_IN));
#endif
#if 0
for (delay = 0; delay < 1000; delay++) {
TX2_DMAOnGoing = true;
}
#endif
ChannelSet[ch].bBulkDMAOnGoing = true;
//DEBUG_OUT('-');
EnableInterrupt();
// leave critical section
}
}
}
// check each Intr_IN End Point transmit request
if ( ChannelSet[ch].uIntrINCount > 0 ) {
// if (!( readw(UDC_TXBUF(ChannelSet[ch].uIntr_IN)) & TxFULL)) {
if (ChannelSet[ch].bIntrDMAOnGoing == false) {
// critical section
DisableInterrupt();
ChannelSet[ch].uCurrentIntrInBlockNum--;
dma_src_addr = ChannelSet[ch].pIntrInBuffer + ChannelSet[ch].uCurrentIntrInBlockNum * INTR_BLOCK_SIZE;
EnableInterrupt();
writew( INTR_BLOCK_SIZE, UDC_TXSTAT(ChannelSet[ch].uIntr_IN) );
writew( virt_to_phy((u32_t)dma_src_addr), UDC_DMALM_IADDR(ChannelSet[ch].uIntr_IN) );
writew( ENP_DMA_START, UDC_DMACTRLI(ChannelSet[ch].uIntr_IN) );
ChannelSet[ch].bIntrDMAOnGoing = true;
#if 0
WAIT_DMA_DONE(UDC_DMACTRLI(ChannelSet[ch].uIntr_IN) );
#endif
ChannelSet[ch].uCurrentBulkInBlockNum = ++ChannelSet[ch].uCurrentBulkInBlockNum % MAX_INTR_NUM;
}
}
}
}
}
// leave usb test now, should never been here
return 0;
}
void UART_IRQHandler(void)
{
uint32_t iir = LPC_USART->IIR;
uint32_t data;
int cnt;
uint32_t iid = iir & LPCUART_IIR_ID_MASK;
if ((iir & LPCUART_IIR_STATUS) == 0)
{
switch (iid)//r & LPCUART_IIR_ID_MASK)
{
case LPCUART_IIR_ID_MS:
// data = LPC_USART->MCR;
// break;
case LPCUART_IIR_ID_RLS: // Line status
{
uint32_t r = LPC_USART->LSR;
if (g_LpcUartDev->pUartDev->EvtCallback)
{
data = (r & LPCUART_LSR_OE) ? UART_LINESTATE_OVR : 0;
data |= (r & LPCUART_LSR_PE) ? UART_LINESTATE_PARERR : 0;
data |= (r & LPCUART_LSR_FE) ? UART_LINESTATE_FRMERR : 0;
data |= (r & LPCUART_LSR_BI) ? UART_LINESTATE_BRK : 0;
data |= (r << 16L);
r = LPC_USART->MSR;
if (r & LPCUART_MSR_DCTS)
{
g_LpcUartDev->pUartDev->LineState ^= UART_LINESTATE_CTS;
data |= (g_LpcUartDev->pUartDev->LineState & UART_LINESTATE_CTS);
}
//data |= (r & LPCUART_MSR_CTS) ? UART_LINESTATE_CTS : 0;
data |= (r & LPCUART_MSR_DDSR) ? UART_LINESTATE_DSR : 0;
data |= (r & LPCUART_MSR_RI) ? UART_LINESTATE_RI : 0;
data |= (r & LPCUART_MSR_DCD) ? UART_LINESTATE_DCD : 0;
data |= (r << 24L);
g_LpcUartDev->pUartDev->EvtCallback(g_LpcUartDev->pUartDev, UART_EVT_LINESTATE, (uint8_t*)&data, 1);
}
}
//break;
case LPCUART_IIR_ID_CTIMOUT:
//flushrx = true;
//break;
case LPCUART_IIR_ID_RDA:
//case LPCUART_IIR_ID_THRE:
{
cnt = 0;
uint32_t state = DisableInterrupt();
while ((g_LpcUartDev->pUartReg->LSR & LPCUART_LSR_RDR) && cnt < 14) {
//while (LpcUARTWaitForRxFifo(&g_LpcUartDev, 10) && cnt < 8) {
//do {
uint8_t *p = CFifoPut(g_LpcUartDev->pUartDev->hRxFifo);
if (p)
{
//d[cnt++] = g_LpcUartDev->pUartReg->RBR;
*p = g_LpcUartDev->pUartReg->RBR;
cnt++;
}
else
{
//printf("drop2\r\n");
break;
}
}
//while ((g_LpcUartDev->pUartReg->LSR & LPCUART_LSR_RDR) && cnt < 14);
cnt = CFifoUsed(g_LpcUartDev->pUartDev->hRxFifo);
EnableInterrupt(state);
//data = LPC_USART->RBR;
if (g_LpcUartDev->pUartDev->EvtCallback)
{
if (iid == LPCUART_IIR_ID_CTIMOUT)
g_LpcUartDev->pUartDev->EvtCallback(g_LpcUartDev->pUartDev, UART_EVT_RXTIMEOUT, NULL, cnt);
else //if (cnt > 8)
g_LpcUartDev->pUartDev->EvtCallback(g_LpcUartDev->pUartDev, UART_EVT_RXDATA, NULL, cnt);
}
}
break;
case LPCUART_IIR_ID_THRE:
//data = LPC_USART->LSR;
{
cnt = 0;
uint32_t state = DisableInterrupt();
g_LpcUartDev->bTxReady = false;
do {
uint8_t *p = CFifoGet(g_LpcUartDev->pUartDev->hTxFifo);
if (p == NULL)
{
g_LpcUartDev->bTxReady = true;
break;
}
LPC_USART->THR = *p;
cnt++;
} //while (LpcUARTWaitForTxFifo(&g_LpcUartDev, 10) && cnt < 14);
while (g_LpcUartDev->pUartReg->LSR & (LPCUART_LSR_TEMT | LPCUART_LSR_THRE) && cnt < 14);
EnableInterrupt(state);
if (g_LpcUartDev->pUartDev->EvtCallback)
{
int len = CFifoAvail(g_LpcUartDev->pUartDev->hTxFifo);
len = g_LpcUartDev->pUartDev->EvtCallback(g_LpcUartDev->pUartDev, UART_EVT_TXREADY, NULL, len);
if (len > 0)
{
//LpcUARTTxData(&g_LpcUartDev->pUartDev->SerIntrf, d, len);
// LPC_USART->THR = d[0];
}
if (g_LpcUartDev->bTxReady)
{
if (g_LpcUartDev->pUartReg->LSR & (LPCUART_LSR_TEMT | LPCUART_LSR_THRE))
{
uint8_t *p = CFifoGet(g_LpcUartDev->pUartDev->hTxFifo);
if (p == NULL)
{
g_LpcUartDev->bTxReady = true;
break;
}
LPC_USART->THR = *p;
}
}
}
}
break;
default:
;
}
}
}
