int link_channel(unsigned int ch1Id , unsigned int ch2Id) { EDMA3_DRV_Result result = EDMA3_DRV_SOK; result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id); if (result != EDMA3_DRV_SOK) { printf("link_channel failed: %u to %u\n", ch2Id, ch1Id); return -1; } return 0; }
/** * \brief EDMA3 mem-to-mem data copy test case, using two DMA * channels, linked to each other. * * \param acnt [IN] Number of bytes in an array * \param bcnt [IN] Number of arrays in a frame * \param ccnt [IN] Number of frames in a block * \param syncType [IN] Synchronization type (A/AB Sync) * * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code */ EDMA3_DRV_Result edma3_test_with_link( EDMA3_DRV_Handle hEdma, unsigned int acnt, unsigned int bcnt, unsigned int ccnt, EDMA3_DRV_SyncType syncType) { EDMA3_DRV_Result result = EDMA3_DRV_SOK; EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0}; unsigned int ch1Id = 0; unsigned int ch2Id = 0; unsigned int tcc1 = 0; unsigned int tcc2 = 0; int i; unsigned int count; unsigned int Istestpassed1 = 0u; unsigned int Istestpassed2 = 0u; unsigned int numenabled = 0; unsigned int BRCnt = 0; int srcbidx = 0, desbidx = 0; int srccidx = 0, descidx = 0; srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1); dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1); srcBuff2 = (signed char*) GLOBAL_ADDR(_srcBuff2); dstBuff2 = (signed char*) GLOBAL_ADDR(_dstBuff2); /* Initalize source and destination buffers */ for (count = 0u; count < (acnt*bcnt*ccnt); count++) { srcBuff1[count] = (int)count+1; srcBuff2[count] = (int)count+1; /** * No need to initialize the destination buffer as it is being invalidated. dstBuff1[count] = initval; dstBuff2[count] = initval; */ } #ifdef EDMA3_ENABLE_DCACHE /* * Note: These functions are required if the buffer is in DDR. * For other cases, where buffer is NOT in DDR, user * may or may not require the below functions. */ /* Flush the Source Buffers */ if (result == EDMA3_DRV_SOK) { result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt)); } if (result == EDMA3_DRV_SOK) { result = Edma3_CacheFlush((unsigned int)srcBuff2, (acnt*bcnt*ccnt)); } /* Invalidate the Destination Buffers */ if (result == EDMA3_DRV_SOK) { result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt)); } if (result == EDMA3_DRV_SOK) { result = Edma3_CacheInvalidate((unsigned int)dstBuff2, (acnt*bcnt*ccnt)); } #endif /* EDMA3_ENABLE_DCACHE */ irqRaised1 = 0; irqRaised2 = 0; /* Set B count reload as B count. */ BRCnt = bcnt; /* Setting up the SRC/DES Index */ srcbidx = (int)acnt; desbidx = (int)acnt; if (syncType == EDMA3_DRV_SYNC_A) { /* A Sync Transfer Mode */ srccidx = (int)acnt; descidx = (int)acnt; } else { /* AB Sync Transfer Mode */ srccidx = ((int)acnt * (int)bcnt); descidx = ((int)acnt * (int)bcnt); } /* Setup for Channel 1*/ tcc1 = EDMA3_DRV_TCC_ANY; ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY; /* Request any DMA channel and any TCC */ if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL); } if (result == EDMA3_DRV_SOK) { /* Fill the PaRAM Set with transfer specific information */ paramSet.srcAddr = (unsigned int)(srcBuff1); paramSet.destAddr = (unsigned int)(dstBuff1); /** * Be Careful !!! * Valid values for SRCBIDX/DSTBIDX are between –32768 and 32767 * Valid values for SRCCIDX/DSTCIDX are between –32768 and 32767 */ paramSet.srcBIdx = srcbidx; paramSet.destBIdx = desbidx; paramSet.srcCIdx = srccidx; paramSet.destCIdx = descidx; /** * Be Careful !!! * Valid values for ACNT/BCNT/CCNT are between 0 and 65535. * ACNT/BCNT/CCNT must be greater than or equal to 1. * Maximum number of bytes in an array (ACNT) is 65535 bytes * Maximum number of arrays in a frame (BCNT) is 65535 * Maximum number of frames in a block (CCNT) is 65535 */ paramSet.aCnt = acnt; paramSet.bCnt = bcnt; paramSet.cCnt = ccnt; /* For AB-synchronized transfers, BCNTRLD is not used. */ paramSet.bCntReload = BRCnt; paramSet.linkAddr = 0xFFFFu; /* Src & Dest are in INCR modes */ paramSet.opt &= 0xFFFFFFFCu; /* Program the TCC */ paramSet.opt |= ((tcc1 << OPT_TCC_SHIFT) & OPT_TCC_MASK); /* Enable Intermediate & Final transfer completion interrupt */ paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT); paramSet.opt |= (1 << OPT_TCINTEN_SHIFT); if (syncType == EDMA3_DRV_SYNC_A) { paramSet.opt &= 0xFFFFFFFBu; } else { /* AB Sync Transfer Mode */ paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT); } /* Now, write the PaRAM Set. */ result = EDMA3_DRV_setPaRAM (hEdma, ch1Id, ¶mSet); } /* * There is another way to program the PaRAM Set using specific APIs * for different PaRAM set entries. It gives user more control and easier * to use interface. User can use any of the methods. * Below is the alternative way to program the PaRAM Set. */ /* if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT); } if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_setDestParams (hEdma, ch1Id, (unsigned int)(dstBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT); } if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx); } if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx); } if (result == EDMA3_DRV_SOK) { if (syncType == EDMA3_DRV_SYNC_A) { result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt, ccnt, BRCnt, EDMA3_DRV_SYNC_A); } else { result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt, ccnt, BRCnt, EDMA3_DRV_SYNC_AB); } } if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_setOptField (hEdma, ch1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1u); } if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_setOptField (hEdma, ch1Id, EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u); } */ /* Request any LINK channel and any TCC */ if (result == EDMA3_DRV_SOK) { /* Setup for Channel 2 */ ch2Id = EDMA3_DRV_LINK_CHANNEL; tcc2 = EDMA3_DRV_TCC_ANY; result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2, (EDMA3_RM_EventQueue)0, &callback1, NULL); } if (result == EDMA3_DRV_SOK) { /* * Fill the PaRAM Set for the LINK channel * with transfer specific information. */ paramSet.srcAddr = (unsigned int)(srcBuff2); paramSet.destAddr = (unsigned int)(dstBuff2); /** * Be Careful !!! * Valid values for SRCBIDX/DSTBIDX are between –32768 and 32767 * Valid values for SRCCIDX/DSTCIDX are between –32768 and 32767 */ paramSet.srcBIdx = srcbidx; paramSet.destBIdx = desbidx; paramSet.srcCIdx = srccidx; paramSet.destCIdx = descidx; /** * Be Careful !!! * Valid values for ACNT/BCNT/CCNT are between 0 and 65535. * ACNT/BCNT/CCNT must be greater than or equal to 1. * Maximum number of bytes in an array (ACNT) is 65535 bytes * Maximum number of arrays in a frame (BCNT) is 65535 * Maximum number of frames in a block (CCNT) is 65535 */ paramSet.aCnt = acnt; paramSet.bCnt = bcnt; paramSet.cCnt = ccnt; /* For AB-synchronized transfers, BCNTRLD is not used. */ paramSet.bCntReload = BRCnt; paramSet.linkAddr = 0xFFFFu; /* Reset opt field first */ paramSet.opt = 0x0u; /* Src & Dest are in INCR modes */ paramSet.opt &= 0xFFFFFFFCu; /* Enable Intermediate & Final transfer completion interrupt */ paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT); paramSet.opt |= (1 << OPT_TCINTEN_SHIFT); if (syncType == EDMA3_DRV_SYNC_A) { paramSet.opt &= 0xFFFFFFFBu; } else { /* AB Sync Transfer Mode */ paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT); } /* Now, write the PaRAM Set. */ result = EDMA3_DRV_setPaRAM(hEdma, ch2Id, ¶mSet); } /* * There is another way to program the PaRAM Set using specific APIs * for different PaRAM set entries. It gives user more control and easier * to use interface. User can use any of the methods. * Below is the alternative way to program the PaRAM Set. */ /* if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (unsigned int)(srcBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT); } if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_setDestParams (hEdma, ch2Id, (unsigned int)(dstBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT); } if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx); } if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx); } if (result == EDMA3_DRV_SOK) { if (syncType == EDMA3_DRV_SYNC_A) { result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt, ccnt, BRCnt,EDMA3_DRV_SYNC_A); } else { result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt, ccnt, BRCnt,EDMA3_DRV_SYNC_AB); } } if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_setOptField (hEdma, ch2Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1u); } if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_setOptField (hEdma, ch2Id, EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u); } */ /* Link both the channels. */ if (result == EDMA3_DRV_SOK) { result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id); } /* * Since the transfer is going to happen in Manual mode of EDMA3 * operation, we have to 'Enable the Transfer' multiple times. * Number of times depends upon the Mode (A/AB Sync) * and the different counts. */ if (result == EDMA3_DRV_SOK) { /*Need to activate next param*/ if (syncType == EDMA3_DRV_SYNC_A) { numenabled = bcnt * ccnt; } else { /* AB Sync Transfer Mode */ numenabled = ccnt; } for (i = 0; i < numenabled; i++) { irqRaised1 = 0; /* * Now enable the transfer for Master channel as many times * as calculated above. */ result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL); if (result != EDMA3_DRV_SOK) { #ifdef EDMA3_DRV_DEBUG EDMA3_DRV_PRINTF ("error from edma3_test_with_link\n\r\n"); #endif /* EDMA3_DRV_DEBUG */ break; } while (irqRaised1 == 0) { /* Wait for the Completion ISR on Master Channel. */ printf ("waiting for interrupt...\n"); } /* Check the status of the completed transfer */ if (irqRaised1 < 0) { /* Some error occured, break from the FOR loop. */ #ifdef EDMA3_DRV_DEBUG EDMA3_DRV_PRINTF ("\r\nedma3_test_with_link: Event Miss Occured!!!\r\n"); #endif /* EDMA3_DRV_DEBUG */ /* Clear the error bits first */ result = EDMA3_DRV_clearErrorBits (hEdma, ch1Id); break; } } } /** * Now the transfer on Master channel is finished. * Trigger next (LINK) param. */ if (EDMA3_DRV_SOK == result) { for (i = 0; i < numenabled; i++) { irqRaised1 = 0; /* * Enable the transfer for LINK channel as many times * as calculated above. */ result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL); if (result != EDMA3_DRV_SOK) { #ifdef EDMA3_DRV_DEBUG EDMA3_DRV_PRINTF ("error from edma3_test_with_link\n\r\n"); #endif /* EDMA3_DRV_DEBUG */ break; } while (irqRaised1 == 0) { /* Wait for the Completion ISR on the Link Channel. */ printf ("waiting for interrupt...\n"); } /* Check the status of the completed transfer */ if (irqRaised1 < 0) { /* Some error occured, break from the FOR loop. */ #ifdef EDMA3_DRV_DEBUG EDMA3_DRV_PRINTF ("\r\nedma3_test_with_link: Event Miss Occured!!!\r\n"); #endif /* EDMA3_DRV_DEBUG */ /* Clear the error bits first */ result = EDMA3_DRV_clearErrorBits (hEdma, ch2Id); break; } } } /* Match the Source and Destination Buffers. */ if (EDMA3_DRV_SOK == result) { for (i = 0; i < (acnt*bcnt*ccnt); i++) { if (srcBuff1[i] != dstBuff1[i]) { Istestpassed1 = 0u; #ifdef EDMA3_DRV_DEBUG EDMA3_DRV_PRINTF("edma3_test_with_link: Data write-read " \ "matching FAILED at i = %d " \ "(srcBuff1 -> dstBuff1)\r\n", i); #endif /* EDMA3_DRV_DEBUG */ break; } } if (i == (acnt*bcnt*ccnt)) { Istestpassed1 = 1u; } for (i = 0; i < (acnt*bcnt*ccnt); i++) { if (srcBuff2[i] != dstBuff2[i]) { Istestpassed2 = 0; #ifdef EDMA3_DRV_DEBUG EDMA3_DRV_PRINTF("edma3_test_with_link: Data write-read " \ "matching FAILED at i = %d " \ "(srcBuff2 -> dstBuff2)\r\n", i); #endif /* EDMA3_DRV_DEBUG */ break; } } if (i == (acnt*bcnt*ccnt)) { Istestpassed2 = 1u; } /* Free the previously allocated channels. */ result = EDMA3_DRV_freeChannel (hEdma, ch1Id); if (result != EDMA3_DRV_SOK) { #ifdef EDMA3_DRV_DEBUG EDMA3_DRV_PRINTF("edma3_test_with_link: EDMA3_DRV_freeChannel() " \ "for ch1 FAILED, error code: %d\r\n", result); #endif /* EDMA3_DRV_DEBUG */ } else { result = EDMA3_DRV_freeChannel (hEdma, ch2Id); if (result != EDMA3_DRV_SOK) { #ifdef EDMA3_DRV_DEBUG EDMA3_DRV_PRINTF("edma3_test_with_link: " \ "EDMA3_DRV_freeChannel() for ch 2 FAILED, " \ "error code: %d\r\n", result); #endif /* EDMA3_DRV_DEBUG */ } } } if((Istestpassed1 == 1u) && (Istestpassed2 == 1u)) { #ifdef EDMA3_DRV_DEBUG EDMA3_DRV_PRINTF("edma3_test_with_link PASSED\r\n"); #endif /* EDMA3_DRV_DEBUG */ } else { #ifdef EDMA3_DRV_DEBUG EDMA3_DRV_PRINTF("edma3_test_with_link FAILED\r\n"); #endif /* EDMA3_DRV_DEBUG */ result = ((EDMA3_DRV_SOK == result) ? EDMA3_DATA_MISMATCH_ERROR : result); } return result; }