.data = &da8xx_edma0_pdata, .size_data = sizeof(da8xx_edma0_pdata), }; static const struct platform_device_info da850_edma1_device __initconst = { .name = "edma", .id = 1, .dma_mask = DMA_BIT_MASK(32), .res = da850_edma1_resources, .num_res = ARRAY_SIZE(da850_edma1_resources), .data = &da850_edma1_pdata, .size_data = sizeof(da850_edma1_pdata), }; static const struct dma_slave_map da830_edma_map[] = { { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) }, { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) }, { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) }, { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) }, { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, }; int __init da830_register_edma(struct edma_rsv_info *rsv) {
[IRQ_DM365_TCERRINT3] = 7, [IRQ_DM365_EMUINT] = 7, }; /* Four Transfer Controllers on DM365 */ static s8 dm365_queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 7}, {1, 7}, {2, 7}, {3, 0}, {-1, -1}, }; static const struct dma_slave_map dm365_edma_map[] = { { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) }, { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) }, { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) }, { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) }, { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) }, { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) }, { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) }, { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) }, { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) }, { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) }, { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) }, { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) }, { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) }, { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
[IRQ_COMMTX] = 7, [IRQ_COMMRX] = 7, [IRQ_EMUINT] = 7, }; /*----------------------------------------------------------------------*/ static s8 queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 3}, {1, 7}, {-1, -1}, }; static const struct dma_slave_map dm644x_edma_map[] = { { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) }, { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) }, { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) }, { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) }, { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, }; static struct edma_soc_info dm644x_edma_pdata = { .queue_priority_mapping = queue_priority_mapping, .default_queue = EVENTQ_1, .slave_map = dm644x_edma_map, .slavecnt = ARRAY_SIZE(dm644x_edma_map), }; static struct resource edma_resources[] = {
}; /*----------------------------------------------------------------------*/ /* Four Transfer Controllers on DM646x */ static s8 dm646x_queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 4}, {1, 0}, {2, 5}, {3, 1}, {-1, -1}, }; static const struct dma_slave_map da646x_edma_map[] = { { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) }, { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) }, { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) }, { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) }, { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) }, }; static struct edma_soc_info dm646x_edma_pdata = { .queue_priority_mapping = dm646x_queue_priority_mapping, .default_queue = EVENTQ_1, .slave_map = da646x_edma_map, .slavecnt = ARRAY_SIZE(da646x_edma_map), }; static struct resource edma_resources[] = { {