/** * \brief Performs the low-level initialization of the chip. * This includes EFC and master clock configuration. * It also enable a low level on the pin NRST triggers a user reset. */ extern WEAK void LowLevelInit( void ) { uint32_t dwTimeout; /* Set 3 WS for Embedded Flash Access for 84 MHz */ EFC0->EEFC_FMR = EEFC_FMR_FWS( 3 ); EFC1->EEFC_FMR = EEFC_FMR_FWS( 3 ); /* Initialize main oscillator */ if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) /* Main Oscillator Selection */ { /* The Main Crystal Oscillator is enabled */ PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8) /* Main Crystal Oscillator Start-up Time: 1.4ms(datasheet) */ /* Specifies the number of Slow Clock cycles multiplied by 8 for the Main Crystal Oscillator start-up time */ | CKGR_MOR_MOSCRCEN /* Main On-Chip RC Oscillator Enable */ | CKGR_MOR_MOSCXTEN; /* Main Crystal Oscillator Enable */ /* MOSCSEL: The Main On-Chip RC Oscillator is selected */ /* MOSCRCF: The Fast RC Oscillator Frequency is at 4 MHz (default) */ /* CFDEN: The Clock Failure Detector is disabled. */ dwTimeout = 0; while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) && (dwTimeout++ < CLOCK_TIMEOUT) ); } /* Switch to 3-20MHz Xtal oscillator */ /* The Main Crystal Oscillator is enabled */ PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8) /* Main Crystal Oscillator Start-up Time: 1.4ms(datasheet) */ /* Specifies the number of Slow Clock cycles multiplied by 8 for the Main Crystal Oscillator start-up time */ | CKGR_MOR_MOSCRCEN /* Main On-Chip RC Oscillator Enable */ | CKGR_MOR_MOSCXTEN /* Main Crystal Oscillator Enable */ | CKGR_MOR_MOSCSEL; /* The Main Crystal Oscillator is selected */ /* MOSCRCF: The Fast RC Oscillator Frequency is at 4 MHz (default) */ /* CFDEN: The Clock Failure Detector is disabled. */ dwTimeout = 0; /* Wait Main XTAL Oscillator Status */ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS) && (dwTimeout++ < CLOCK_TIMEOUT)); /* configure PLLA to 168 MHz */ PMC->CKGR_PLLAR = CKGR_PLLAR_STUCKTO1 | CKGR_PLLAR_MULA(13) /* PLLA Multiplier 12 MHz x (13+1) = 168 MHz */ | CKGR_PLLAR_PLLACOUNT(2) /* PLLA Counter 200µs(datasheet) */ | CKGR_PLLAR_DIVA(1); /* Divider bypassed */ dwTimeout = 0; /* Wait PLL A Lock Status */ while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (dwTimeout++ < CLOCK_TIMEOUT)); PMC->PMC_MCKR = PMC_MCKR_PRES_CLK_2 /* Selected clock divided by 2 => 168/2 = 84 MHz */ | PMC_MCKR_CSS_MAIN_CLK; /* Main Clock is selected */ dwTimeout = 0; /* Wait Master Clock Status */ while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (dwTimeout++ < CLOCK_TIMEOUT)); PMC->PMC_MCKR = PMC_MCKR_PRES_CLK_2 /* Selected clock divided by 2 => 168/2 = 84 MHz */ | PMC_MCKR_CSS_PLLA_CLK; /* PLLA Clock is selected */ dwTimeout = 0; /* Wait Master Clock Status */ while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (dwTimeout++ < CLOCK_TIMEOUT)); }
/** * \brief Setup the microcontroller system. * * Initialize the System and update the SystemFrequency variable. */ void SystemInit( void ) { /* Set 1 FWS for Embedded Flash Access */ EFC0->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE; #if defined(ID_EFC1) EFC1->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE; #endif }
/** * \brief Initialize the EFC controller. * * \param ul_access_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit. * \param ul_fws The number of wait states in cycle (no shift). * * \return 0 if successful. */ uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws) { #if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws) | EEFC_FMR_CLOE); #else efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws)); #endif return EFC_RC_OK; }
void clock_init(void) { uint32_t timeout; /* Disable watchdog */ WDT_MR = BV(WDT_WDDIS); /* Set wait states for flash access, needed for higher CPU clock rates */ EEFC0_FMR = EEFC_FMR_FWS(3); #ifdef EEFC1_FMR EEFC1_FMR = EEFC_FMR_FWS(3); #endif // Initialize main oscillator if (!(CKGR_MOR & BV(CKGR_MOR_MOSCSEL))) { CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8) | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN); timeout = CLOCK_TIMEOUT; while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout); } // Switch to external oscillator CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8) | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN) | BV(CKGR_MOR_MOSCSEL); timeout = CLOCK_TIMEOUT; while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout); // Initialize and enable PLL clock CKGR_PLLR = evaluate_pll() | BV(CKGR_PLLR_STUCKTO1) | CKGR_PLLR_PLLCOUNT(0x2); timeout = CLOCK_TIMEOUT; while (!(PMC_SR & BV(PMC_SR_LOCK)) && --timeout); PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK; timeout = CLOCK_TIMEOUT; while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout); PMC_MCKR = PMC_MCKR_CSS_PLL_CLK; timeout = CLOCK_TIMEOUT; while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout); /* Enable clock on PIO for inputs */ // TODO: move this in gpio_init() for better power management? pmc_periphEnable(PIOA_ID); pmc_periphEnable(PIOB_ID); pmc_periphEnable(PIOC_ID); #ifdef PIOF_ID pmc_periphEnable(PIOD_ID); pmc_periphEnable(PIOE_ID); pmc_periphEnable(PIOF_ID); #endif }
/** * @brief Initialize the CPU, set IRQ priorities */ void cpu_init(void) { /* disable the watchdog timer */ WDT->WDT_MR |= WDT_MR_WDDIS; /* initialize the Cortex-M core */ cortexm_init(); /* setup the flash wait states */ EFC0->EEFC_FMR = EEFC_FMR_FWS(CLOCK_FWS); EFC1->EEFC_FMR = EEFC_FMR_FWS(CLOCK_FWS); /* unlock write protect register for PMC module */ PMC->PMC_WPMR = PMC_WPMR_WPKEY(WPKEY); /* activate the external crystal */ PMC->CKGR_MOR = (CKGR_MOR_KEY(MORKEY) | CKGR_MOR_MOSCXTST(XTAL_STARTUP) | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCRCEN); /* wait for crystal to be stable */ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); /* select crystal to clock the main clock */ PMC->CKGR_MOR = (CKGR_MOR_KEY(MORKEY) | CKGR_MOR_MOSCXTST(XTAL_STARTUP) | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCSEL); /* wait for main oscillator selection to be complete */ while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)); /* setup PLLA */ PMC->CKGR_PLLAR = (CKGR_PLLAR_ONE | CKGR_PLLAR_PLLACOUNT(PLL_CNT) | CKGR_PLLAR_MULA(CLOCK_PLL_MUL) | CKGR_PLLAR_DIVA(CLOCK_PLL_DIV)); /* wait for PLL to lock */ while (!(PMC->PMC_SR & PMC_SR_LOCKA)); /* before switching to PLLA, we need to switch to main clock */ PMC->PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK; while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); /* use PLLA as main clock source */ PMC->PMC_MCKR = PMC_MCKR_CSS_PLLA_CLK; /* wait for master clock to be ready */ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); /* trigger static peripheral initialization */ periph_init(); }
/* Clock settings (84MHz) */ static void clock_init(void) { /* Set FWS according to SYS_BOARD_MCKR configuration */ SAM_EEFC0->FMR = EEFC_FMR_FWS(4) | EEFC_FMR_FRDY; SAM_EEFC1->FMR = EEFC_FMR_FWS(4) | EEFC_FMR_FRDY; /* Initialize main oscillator */ SAM_PMC->CKGR_MOR = (PMC_CKGR_MOR_KEY(0x37) | PMC_CKGR_MOR_MOSCXTST(0x8) | PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN); while ((SAM_PMC->SR & PMC_SR_MOSCXTS) == 0); /* Switch to the oscillator connected to XIN/XOUT. */ SAM_PMC->CKGR_MOR = (PMC_CKGR_MOR_KEY(0x37) | PMC_CKGR_MOR_MOSCXTST(0x8) | PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN | PMC_CKGR_MOR_MOSCSEL); while ((SAM_PMC->SR & PMC_SR_MOSCSELS) == 0); SAM_PMC->MCKR = ((SAM_PMC->MCKR & ~(uint32_t)PMC_MCKR_CSS_MASK) | PMC_MCKR_CSS_MAIN_CLK); while ((SAM_PMC->SR & PMC_SR_MCKRDY) == 0); /* Initialize PLLA. */ SAM_PMC->CKGR_PLLAR = (PMC_CKGR_PLLAR_ONE | PMC_CKGR_PLLAR_MULA(0xd) | PMC_CKGR_PLLAR_PLLACOUNT(0x3f) | PMC_CKGR_PLLAR_DIVA(1)); while ((SAM_PMC->SR & PMC_SR_LOCKA) == 0); /* Switch to main clock. */ SAM_PMC->MCKR = (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_MAIN_CLK); while ((SAM_PMC->SR & PMC_SR_MCKRDY) == 0); /* Switch to PLLA. */ SAM_PMC->MCKR = (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK); while ((SAM_PMC->SR & PMC_SR_MCKRDY) == 0); }
/** * \brief Setup the microcontroller system. * * Initialize the System and update the SystemFrequency variable. */ void SystemInit( void ) { /* Set 6 FWS for Embedded Flash Access */ EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE ; /* Initialize main oscillator */ if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) { PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTST(0x8U) | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN ; while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) ) ; } /* Switch to 3-20MHz Xtal oscillator */ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTST(0x8U) | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) ) ; PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK ; while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) ; /* Initialize PLLA */ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x13U) | CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U) ; while ( !(PMC->PMC_SR & PMC_SR_LOCKA) ) ; /* Switch to main clock */ PMC->PMC_MCKR = ((PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK) & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK ; while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) ; /* Switch to PLLA */ PMC->PMC_MCKR = PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK ; while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) ; SystemCoreClock=__SYSTEM_CLOCK_120MHZ ; }
/** * \brief Setup the microcontroller system. * * Initialize the System and update the SystemFrequency variable. */ void SystemInit( void ) { /* * TODO: * Add code to initialize the system according to your application. * * For SAM4S, the internal 4MHz fast RC oscillator is the default clock * selected at system reset state. */ /* Set FWS according to default clock configuration */ EFC0->EEFC_FMR = EEFC_FMR_FWS(1); #if defined(ID_EFC1) EFC1->EEFC_FMR = EEFC_FMR_FWS(1); #endif }
/** * \brief Performs the low-level initialization of the chip. * This includes EFC and master clock configuration. * It also enable a low level on the pin NRST triggers a user reset. */ extern WEAK void LowLevelInit( void ) { uint32_t timeout = 0; /* Set 3 FWS for Embedded Flash Access */ EFC->EEFC_FMR = EEFC_FMR_FWS(3); /* Initialize main oscillator */ if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) { PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; timeout = 0; while (!(PMC->PMC_SR & PMC_SR_MOSCXTS) && (timeout++ < CLOCK_TIMEOUT)); } /* Switch to 3-20MHz Xtal oscillator */ PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; timeout = 0; while (!(PMC->PMC_SR & PMC_SR_MOSCSELS) && (timeout++ < CLOCK_TIMEOUT)); PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; ); /* Initialize PLLB */ PMC->CKGR_PLLBR = BOARD_PLLBR; timeout = 0; while (!(PMC->PMC_SR & PMC_SR_LOCKB) && (timeout++ < CLOCK_TIMEOUT)); /* Switch to main clock */ PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; ); PMC->PMC_MCKR = BOARD_MCKR ; for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; ); }
/** Initialise flash, disable watchdog, set up clocks. This and any functions it calls must be for the C runtime startup to work. */ void mcu_init (void) { irq_id_t id; int i; EFC0->EEFC_FMR = EEFC_FMR_FWS (5); /* Disable all interrupts to be sure when debugging. */ for (i = 0; i < 8; i++) NVIC->ICER[i] = ~0; mcu_reset_enable (); /* Reduce the number of wait states for the flash memory. */ mcu_flash_init (); mcu_watchdog_disable (); mcu_clock_init (); #if 0 /* Enable protect mode. */ AIC->AIC_DCR |= AIC_DCR_PROT; /* Use MATRIX_WPMR ? */ #endif irq_global_enable (); }
/** * \brief Setup the microcontroller system. * Initialize the System and update the SystemFrequency variable. */ void SystemInit( void ) { /* Set FWS according to SYS_BOARD_MCKR configuration */ EFC0->EEFC_FMR = EEFC_FMR_FWS(4); EFC1->EEFC_FMR = EEFC_FMR_FWS(4); /* Initialize main oscillator */ if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) { PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) ) { } } /* Switch to 3-20MHz Xtal oscillator */ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) ) { } PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { } /* Initialize PLLA */ PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; while ( !(PMC->PMC_SR & PMC_SR_LOCKA) ) { } /* Switch to main clock */ PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) { } /* Switch to PLLA */ PMC->PMC_MCKR = SYS_BOARD_MCKR; while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) { } SystemCoreClock = CHIP_FREQ_CPU_MAX; }
/** * \brief Setup the microcontroller system. * Initialize the System and update the SystemFrequency variable. */ void SystemInit( void ) { #if (__FPU_USED == 1) // Keil /* enable FPU if available and used */ SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ (3UL << 11*2) ); /* set CP11 Full Access */ #endif /* Set FWS according to SYS_BOARD_MCKR configuration */ EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; /* Initialize main oscillator */ if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) { PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) ) { } } /* Switch to 3-20MHz Xtal oscillator */ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) ) { } PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) { } /* Initialize PLLA */ PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; while ( !(PMC->PMC_SR & PMC_SR_LOCKA) ) { } /* Switch to main clock */ PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) { } /* Switch to PLLA */ PMC->PMC_MCKR = SYS_BOARD_MCKR; while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) { } SystemCoreClock = CHIP_FREQ_CPU_MAX; /* SDRAM initialization */ sdramInit(); }
/** * \brief Set read/write wait state on the EEFC perpherial. * * \param efc Pointer to a Efc instance * \param cycles the number of wait states in cycle. */ extern void EFC_SetWaitState( Efc* efc, uint8_t ucCycles ) { uint32_t dwFmr ; dwFmr = efc->EEFC_FMR ; dwFmr &= ~((uint32_t)EEFC_FMR_FWS_Msk) ; dwFmr |= EEFC_FMR_FWS(ucCycles); EFC_WriteFMR(efc, dwFmr); }
extern void EFC_SetWaitState( Efc* efc, uint8_t ucCycles ) { uint32_t dwValue ; dwValue = efc->EEFC_FMR ; dwValue &= ~((uint32_t)EEFC_FMR_FWS_Msk) ; dwValue |= EEFC_FMR_FWS(ucCycles); efc->EEFC_FMR = dwValue ; }
/** * \brief Setup the microcontroller system. * * Initialize the System and update the System Frequency variable. */ void SystemInit( void ) { /* Set 6 FWS for Embedded Flash Access according to 120MHz configuration */ EFC0->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE; /* * We are coming from a Hard Reset or Backup mode. * The core is clocked by Internal Fast RC @ 8MHz. * We intend to use the device @120MHz from external 32kHz oscillator. * Steps are: * 1- Activation of external 32kHz oscillator * 2- Set PLLA configuration * 3- Select the master clock and processor clock * 4- Select the programmable clocks (optional) */ /* Step 1 - Activation of external 32kHz oscillator * Then, we wait the startup time to be finished by checking PMC_SR_MOSCXTS in PMC_SR. */ SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL; while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL) && (PMC->PMC_SR & PMC_SR_OSCSELS)) ; /* Step 2 - Set PLLA configuration * The external oscillator is 32kHz. As we intend to clock the system @120MHz, * we need to multiply the oscillator frequency by 3662 (120000000/32768). * This can be done by setting CKGR_PLLAR_MULA to value 0xe4d (3662 - 1). * We set the maximum PLL Lock time to maximum in CKGR_PLLAR_PLLACOUNT. * Reference is product datasheet at 18.19.9 PMC Clock Generator PLLA Register. * * In case of, we could check first if PLLA is already active and put CKGR_PLLAR_MULA * prior to set new configuration (not done here). */ PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(1ul) | CKGR_PLLAR_MULA(0xe4dul) | CKGR_PLLAR_PLLACOUNT(0x3ful); for ( ; (PMC->PMC_SR & PMC_SR_LOCKA) != PMC_SR_LOCKA ; ); /* Step 3 - Select the master clock and processor clock * Source clock will be PLLA, instead of MAINCK from startup (8MHz Fast-RC). * We first update the prescaler value to one and then switch source to PLLA. */ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | PMC_MCKR_PRES_CLK_1; for ( ; !(PMC->PMC_SR & PMC_SR_MCKRDY);); PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_PLLA_CLK; for ( ; !(PMC->PMC_SR & PMC_SR_MCKRDY); ); /* * Step 4 - Select the programmable clocks * * Output MCK on PCK1/pins PA17/PA21/PA30 * Used to validate Master Clock settings */ // PMC->PMC_SCER = PMC_SCER_PCK1 ; SystemCoreClock=__SYSTEM_CLOCK_120MHZ; }
/** * \brief Setup the microcontroller system. * * Initialize the System and update the SystemFrequency variable. */ void SystemInit( void ) { /* Disable Watchdog*/ WDT->WDT_MR |= WDT_MR_WDDIS; /* Set FWS according to 24MHz clock configuration */ EFC->EEFC_FMR = EEFC_FMR_FWS(1); /* Set internal oscillator to 24MHz*/ while(!(PMC->PMC_SR & PMC_SR_MOSCRCS)); PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCF_24_MHz); }
void init_flash(void) { /* Set FWS for embedded Flash access according to operating frequency */ if ( MASTER_CLOCK_FREQ < CHIP_FREQ_FWS_0 ) { EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE; } else { if (MASTER_CLOCK_FREQ < CHIP_FREQ_FWS_1) { EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE; } else { if (MASTER_CLOCK_FREQ < CHIP_FREQ_FWS_2) { EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE; } else { if ( MASTER_CLOCK_FREQ < CHIP_FREQ_FWS_3 ) { EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE; } else { if ( MASTER_CLOCK_FREQ < CHIP_FREQ_FWS_4 ) { EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE; } else { EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE; } } } } } }
int main() { #if 1 WDT_Disable(WDT); /* Set 3 FWS for Embedded Flash Access */ EFC->EEFC_FMR = EEFC_FMR_FWS(3); CLOCK_SetConfig(2); /* I don't know why, the baudrate is 38400 = 115200/3 */ UART_Configure(115200, 64000000/3);// so I add this to solve the problem printf("Start GaInOS-TK.\r\n"); #endif StartOS(OSDEFAULTAPPMODE); return 0; }
void clock_init(void) { uint32_t timeout; /* Disable watchdog */ WDT_MR = BV(WDT_WDDIS); /* Set 4 wait states for flash access, needed for higher CPU clock rates */ EEFC_FMR = EEFC_FMR_FWS(3); // Select external slow clock if (!(SUPC_SR & BV(SUPC_SR_OSCSEL))) { SUPC_CR = BV(SUPC_CR_XTALSEL) | SUPC_CR_KEY(0xA5); while (!(SUPC_SR & BV(SUPC_SR_OSCSEL))); } // Initialize main oscillator if (!(CKGR_MOR & BV(CKGR_MOR_MOSCSEL))) { CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN); timeout = CLOCK_TIMEOUT; while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout); } // Switch to external oscillator CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN) | BV(CKGR_MOR_MOSCSEL); timeout = CLOCK_TIMEOUT; while (!(PMC_SR & BV(PMC_SR_MOSCSELS)) && --timeout); PMC_MCKR = (PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_MASK) | PMC_MCKR_CSS_MAIN_CLK; timeout = CLOCK_TIMEOUT; while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout); // Initialize and enable PLL clock CKGR_PLLR = evaluate_pll() | BV(CKGR_PLLR_STUCKTO1) | CKGR_PLLR_PLLCOUNT(0x1); timeout = CLOCK_TIMEOUT; while (!(PMC_SR & BV(PMC_SR_LOCK)) && --timeout); PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK; timeout = CLOCK_TIMEOUT; while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout); PMC_MCKR = PMC_MCKR_CSS_PLL_CLK; timeout = CLOCK_TIMEOUT; while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout); /* Enable clock on PIO for inputs */ PMC_PCER = BV(PIOA_ID) | BV(PIOB_ID) | BV(PIOC_ID); }
/** * \brief Performs the low-level initialization of the chip. * This includes EFC and master clock configuration. * It also enable a low level on the pin NRST triggers a user reset. */ extern WEAK void LowLevelInit( void ) { /* Set 3 FWS for Embedded Flash Access */ EFC->EEFC_FMR = EEFC_FMR_FWS(3); if ((PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) /* Main Oscillator Selection */ { /* Switch MCK to Slow clock */ PMC_SetMckSelection(PMC_MCKR_CSS_SLOW_CLK, PMC_MCKR_PRES_CLK); /* First, select external clock */ PMC_SelectExtOsc(); /* Then, enable Main XTAL oscillator */ PMC_EnableExtOsc(); /* Then, cofigure PLLB and switch clock */ PMC_ConfigureMckWithPllb(0x8, 1, PMC_MCKR_PRES_CLK_2); /* MCK = 12MHz * 8 / 2 = 48MHz */ } }
/** * \brief Setup the microcontroller system. * Initialize the System and update the SystemFrequency variable. */ void SystemInit(void) { /* Set FWS according to SYS_BOARD_MCKR configuration */ EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE; /* Initialize PLLA */ PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; while (!(PMC->PMC_SR & PMC_SR_LOCKA)) { } /* Switch to PLLA */ PMC->PMC_MCKR = SYS_BOARD_MCKR; while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { } SystemCoreClock = CHIP_FREQ_CPU_MAX; }
//----------------------------------------------------------------------------- static void sys_init(void) { // Disable watchdog WDT->WDT_MR = WDT_MR_WDDIS; // Set flash wait states to maximum for 150 MHz operation EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; // Enable 32 kHz Xtal SUPC->SUPC_CR |= SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL; // Enable 12 MHz Xtal PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTST(8) | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTST(8) | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)); // Setup PLL (12 MHz * 25 = 300 MHz) PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(25-1) | CKGR_PLLAR_PLLACOUNT(0x3f) | CKGR_PLLAR_DIVA(1); while (!(PMC->PMC_SR & PMC_SR_LOCKA)); // Switch main clock to PLL (two step process) PMC->PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK | PMC_MCKR_MDIV_PCK_DIV2; while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); PMC->PMC_MCKR = PMC_MCKR_CSS_PLLA_CLK | PMC_MCKR_MDIV_PCK_DIV2; while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); // Enable PIOA, PIOB, PIOC, PIOD and PIOE PMC->PMC_PCER0 = PMC_PCER0_PID10 | PMC_PCER0_PID11 | PMC_PCER0_PID12 | PMC_PCER0_PID16 | PMC_PCER0_PID17; // Disable altenate functions on some pins MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; // Enable interrupts asm volatile ("cpsie i"); }
/** * \brief Setup the microcontroller system. * * Initialize the System and update the SystemFrequency variable. */ void SystemInit( void ) { /* * TODO: * Add code to initialize the system according to your application. * * For SAMG55, the internal 8MHz fast RC oscillator is the default clock * selected at system reset state. */ /* Disable Watchdog*/ WDT->WDT_MR |= WDT_MR_WDDIS; /* Set FWS according to default clock configuration */ EFC->EEFC_FMR = EEFC_FMR_FWS(1); /* Set internal oscillator to 24MHz*/ while(!(PMC->PMC_SR & PMC_SR_MOSCRCS)); PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCF_24_MHz); }
void system_init_flash(uint32_t ul_clk) { /* Set FWS for embedded Flash access according to operating frequency */ if (ul_clk < CHIP_FREQ_FWS_0) { EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE; } else if (ul_clk < CHIP_FREQ_FWS_1) { EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE; } else if (ul_clk < CHIP_FREQ_FWS_2) { EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE; } else if (ul_clk < CHIP_FREQ_FWS_3) { EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE; } else if (ul_clk < CHIP_FREQ_FWS_4) { EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE; } else { EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE; } }
static inline void sam_efcsetup(void) { uint32_t regval = EEFC_FMR_FWS(BOARD_FWS) | EEFC_FMR_CLOE; putreg32(regval, SAM_EEFC_FMR); }
/** * \brief Performs the low-level initialization of the chip. * This includes EFC and master clock configuration. * It also enable a low level on the pin NRST triggers a user reset. */ extern WEAK void LowLevelInit( void ) { uint32_t dwTimeout ; /* Set 2 WS for Embedded Flash Access */ EFC0->EEFC_FMR = EEFC_FMR_FWS( 4 ) ; EFC1->EEFC_FMR = EEFC_FMR_FWS( 4 ) ; /* Initialize main oscillator */ if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) /* Main Oscillator Selection */ { // 48MHz PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8) /* Main Crystal Oscillator Start-up Time: 1.4ms(datasheet) */ | CKGR_MOR_MOSCRCEN /* Main On-Chip RC Oscillator Enable */ | CKGR_MOR_MOSCXTEN; /* Main Crystal Oscillator Enable */ /* The Main On-Chip RC Oscillator is selected */ dwTimeout = 0 ; while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) && (dwTimeout++ < CLOCK_TIMEOUT) ) ; } /* Switch to 3-20MHz Xtal oscillator */ PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8) /* Main Crystal Oscillator Start-up Time: 1.4ms(datasheet) */ | CKGR_MOR_MOSCRCEN /* Main On-Chip RC Oscillator Enable */ | CKGR_MOR_MOSCXTEN /* Main Crystal Oscillator Enable */ | CKGR_MOR_MOSCSEL; /* The Main Crystal Oscillator is selected */ dwTimeout = 0; /* Wait Main Oscillator Selection Status */ while (!(PMC->PMC_SR & PMC_SR_MOSCSELS) && (dwTimeout++ < CLOCK_TIMEOUT)); PMC->PMC_MCKR = (PMC->PMC_MCKR & ~ (0x7UL << 0)/*AT91C_PMC_CSS*/) | PMC_MCKR_CSS_MAIN_CLK; /* Main Clock is selected */ dwTimeout = 0; /* Wait Master Clock Status */ while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (dwTimeout++ < CLOCK_TIMEOUT)); /* Initialize PLLA */ PMC->CKGR_PLLAR = CKGR_PLLAR_STUCKTO1 | CKGR_PLLAR_MULA(13) /* PLLA Multiplier */ | CKGR_PLLAR_PLLACOUNT(2) /* PLLA Counter 200µs(datasheet) */ | CKGR_PLLAR_DIVA(1); /* Divider */ dwTimeout = 0; /* Wait PLL A Lock Status */ while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (dwTimeout++ < CLOCK_TIMEOUT)); /* Initialize UTMI for USB usage, can be disabled if not using USB for the sake of saving power*/ PMC->CKGR_UCKR |= CKGR_UCKR_UPLLCOUNT(3) /* UTMI PLL Start-up Time */ | CKGR_UCKR_UPLLEN; /* UTMI PLL Enable */ dwTimeout = 0; /* Wait UTMI PLL Lock Status */ while (!(PMC->PMC_SR & PMC_SR_LOCKU) && (dwTimeout++ < CLOCK_TIMEOUT)); /* Switch to PLLA*/ PMC->PMC_MCKR = ((PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK) & ~(0x7UL << 0)/*AT91C_PMC_CSS*/) | PMC_MCKR_CSS_MAIN_CLK; /* Main Clock is selected */ dwTimeout = 0; /* Wait Master Clock Status */ while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (dwTimeout++ < CLOCK_TIMEOUT)); PMC->PMC_MCKR = PMC_MCKR_PRES_CLK_2 /* Selected clock divided by 2 */ | PMC_MCKR_CSS_PLLA_CLK; /* PLLA Clock is selected */ dwTimeout = 0; /* Wait Master Clock Status */ while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (dwTimeout++ < CLOCK_TIMEOUT)); }
/** * \brief Set flash wait state. * * \param p_efc Pointer to an EFC instance. * \param ul_fws The number of wait states in cycle (no shift). */ void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws) { uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FWS_Msk); efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FWS(ul_fws)); }
/** * \brief Initialize the EFC controller. * * \param ul_access_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit. * \param ul_fws The number of wait states in cycle (no shift). * * \return 0 if successful. */ uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws) { efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws)); return EFC_RC_OK; }
// ============================================================================= // 功能:系统时钟初始化,主时钟配置为300MHz,外设时钟为150M // 参数:无 // 返回:无 // ============================================================================= void SysClk_Init(void) { uint32_t read_MOR; EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8)); EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(7)); TCM_Disable(); /* Set FWS according to SYS_BOARD_MCKR configuration */ EFC->EEFC_FMR = EEFC_FMR_FWS(5); /* Before switching MAIN OSC on external crystal : enable it and don't * disable at the same time RC OSC in case of if MAIN OSC is still using RC * OSC */ read_MOR = PMC->CKGR_MOR; /* enable external crystal - enable RC OSC */ read_MOR |= (CKGR_MOR_KEY_PASSWD |CKGR_MOR_XT32KFME); PMC->CKGR_MOR = read_MOR; /* Select XTAL 32k instead of internal slow RC 32k for slow clock */ if ( (SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST ) { SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL; while( !(SUPC->SUPC_SR & SUPC_SR_OSCSEL) ); } /* Initialize main oscillator */ if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) { PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) ) { } } /* Switch to 3-20MHz Xtal oscillator */ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) ) { } PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) { } /* Initialize PLLA */ PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; while ( !(PMC->PMC_SR & PMC_SR_LOCKA) ) { } /* Switch to main clock */ PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) { } /* Switch to PLLA */ PMC->PMC_MCKR = SYS_BOARD_MCKR; while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) { } // SystemCoreClock = CHIP_FREQ_CPU_MAX; }
/** * Save clock settings and shutdown PLLs */ __always_inline static void pmc_save_clock_settings( uint32_t *p_osc_setting, uint32_t *p_pll0_setting, uint32_t *p_pll1_setting, uint32_t *p_mck_setting, uint32_t *p_fmr_setting, #if defined(EFC1) uint32_t *p_fmr_setting1, #endif const bool disable_xtal) { uint32_t mor = PMC->CKGR_MOR; uint32_t mckr = PMC->PMC_MCKR; uint32_t fmr = EFC0->EEFC_FMR; # if defined(EFC1) uint32_t fmr1 = EFC1->EEFC_FMR; # endif if (p_osc_setting) { *p_osc_setting = mor; } if (p_pll0_setting) { *p_pll0_setting = PMC->CKGR_PLLAR; } if (p_pll1_setting) { #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) *p_pll1_setting = PMC->CKGR_PLLBR; #elif (SAM3U || SAM3XA) *p_pll1_setting = PMC->CKGR_UCKR; #else *p_pll1_setting = 0; #endif } if (p_mck_setting) { *p_mck_setting = mckr; } if (p_fmr_setting) { *p_fmr_setting = fmr; } #if defined(EFC1) if (p_fmr_setting1) { *p_fmr_setting1 = fmr1; } #endif /* Enable FAST RC */ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor | CKGR_MOR_MOSCRCEN; /* if MCK source is PLL, switch to mainck */ if ((mckr & PMC_MCKR_CSS_Msk) > PMC_MCKR_CSS_MAIN_CLK) { /* MCK -> MAINCK */ mckr = (mckr & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_MAIN_CLK; PMC->PMC_MCKR = mckr; while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); } /* MCK prescale -> 1 */ if (mckr & PMC_MCKR_PRES_Msk) { mckr = (mckr & (~PMC_MCKR_PRES_Msk)); PMC->PMC_MCKR = mckr; while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); } /* Disable PLLs */ pmc_disable_pllack(); #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) pmc_disable_pllbck(); #elif (SAM3U || SAM3XA) pmc_disable_upll_clock(); #endif /* Prepare for entering WAIT mode */ /* Wait fast RC ready */ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); /* Switch mainck to FAST RC */ #if SAMG /** * For the sleepwalking feature, we need an accurate RC clock. Only 24M and * 16M are trimmed in production. Here we select the 24M. * And so wait state need to be 1. */ EFC0->EEFC_FMR = (fmr & (~EEFC_FMR_FWS_Msk)) | EEFC_FMR_FWS(1); PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_MOSCRCF_24_MHz | CKGR_MOR_KEY_PASSWD; #else PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_KEY_PASSWD; #endif while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)); #if (!SAMG) /* FWS update */ EFC0->EEFC_FMR = fmr & (~EEFC_FMR_FWS_Msk); #if defined(EFC1) EFC1->EEFC_FMR = fmr1 & (~EEFC_FMR_FWS_Msk); #endif #endif /* Disable XTALs */ if (disable_xtal) { PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | CKGR_MOR_KEY_PASSWD; } }