__checkReturn int
efx_nic_probe(
__in efx_nic_t *enp)
{
efx_nic_ops_t *enop;
efx_oword_t oword;
int rc;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
#if EFSYS_OPT_MCDI
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
#endif /* EFSYS_OPT_MCDI */
EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
/* Test BIU */
if ((rc = efx_nic_biu_test(enp)) != 0)
goto fail1;
/* Clear the region register */
EFX_POPULATE_OWORD_4(oword,
FRF_AZ_ADR_REGION0, 0,
FRF_AZ_ADR_REGION1, (1 << 16),
FRF_AZ_ADR_REGION2, (2 << 16),
FRF_AZ_ADR_REGION3, (3 << 16));
EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
enop = enp->en_enop;
if ((rc = enop->eno_probe(enp)) != 0)
goto fail2;
if ((rc = efx_phy_probe(enp)) != 0)
goto fail3;
enp->en_mod_flags |= EFX_MOD_PROBE;
return (0);
fail3:
EFSYS_PROBE(fail3);
enop->eno_unprobe(enp);
fail2:
EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE1(fail1, int, rc);
return (rc);
}
__checkReturn efx_rc_t
siena_nic_probe(
__in efx_nic_t *enp)
{
efx_port_t *epp = &(enp->en_port);
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
siena_link_state_t sls;
unsigned int mask;
efx_oword_t oword;
efx_rc_t rc;
EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
/* Test BIU */
if ((rc = efx_nic_biu_test(enp)) != 0)
goto fail1;
/* Clear the region register */
EFX_POPULATE_OWORD_4(oword,
FRF_AZ_ADR_REGION0, 0,
FRF_AZ_ADR_REGION1, (1 << 16),
FRF_AZ_ADR_REGION2, (2 << 16),
FRF_AZ_ADR_REGION3, (3 << 16));
EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
/* Read clear any assertion state */
if ((rc = efx_mcdi_read_assertion(enp)) != 0)
goto fail2;
/* Exit the assertion handler */
if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
goto fail3;
/* Wrestle control from the BMC */
if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
goto fail4;
if ((rc = siena_board_cfg(enp)) != 0)
goto fail5;
if ((rc = siena_phy_cfg(enp)) != 0)
goto fail6;
/* Obtain the default PHY advertised capabilities */
if ((rc = siena_nic_reset(enp)) != 0)
goto fail7;
if ((rc = siena_phy_get_link(enp, &sls)) != 0)
goto fail8;
epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask;
epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
if ((rc = siena_nic_get_partn_mask(enp, &mask)) != 0)
goto fail9;
enp->en_u.siena.enu_partn_mask = mask;
#endif
#if EFSYS_OPT_MAC_STATS
/* Wipe the MAC statistics */
if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
goto fail10;
#endif
#if EFSYS_OPT_LOOPBACK
if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
goto fail11;
#endif
#if EFSYS_OPT_MON_STATS
if ((rc = mcdi_mon_cfg_build(enp)) != 0)
goto fail12;
#endif
encp->enc_features = enp->en_features;
return (0);
#if EFSYS_OPT_MON_STATS
fail12:
EFSYS_PROBE(fail12);
#endif
#if EFSYS_OPT_LOOPBACK
fail11:
EFSYS_PROBE(fail11);
#endif
#if EFSYS_OPT_MAC_STATS
fail10:
EFSYS_PROBE(fail10);
#endif
#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
fail9:
EFSYS_PROBE(fail9);
#endif
fail8:
EFSYS_PROBE(fail8);
fail7:
EFSYS_PROBE(fail7);
fail6:
EFSYS_PROBE(fail6);
fail5:
EFSYS_PROBE(fail5);
fail4:
EFSYS_PROBE(fail4);
fail3:
EFSYS_PROBE(fail3);
fail2:
EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
return (rc);
}
static void falcon_reconfigure_gmac(struct efx_nic *efx)
{
bool loopback, tx_fc, rx_fc, bytemode;
int if_mode;
unsigned int max_frame_len;
efx_oword_t reg;
/* Configuration register 1 */
tx_fc = (efx->link_fc & EFX_FC_TX) || !efx->link_fd;
rx_fc = !!(efx->link_fc & EFX_FC_RX);
loopback = (efx->loopback_mode == LOOPBACK_GMAC);
bytemode = (efx->link_speed == 1000);
EFX_POPULATE_OWORD_5(reg,
GM_LOOP, loopback,
GM_TX_EN, 1,
GM_TX_FC_EN, tx_fc,
GM_RX_EN, 1,
GM_RX_FC_EN, rx_fc);
falcon_write(efx, ®, GM_CFG1_REG);
udelay(10);
/* Configuration register 2 */
if_mode = (bytemode) ? 2 : 1;
EFX_POPULATE_OWORD_5(reg,
GM_IF_MODE, if_mode,
GM_PAD_CRC_EN, 1,
GM_LEN_CHK, 1,
GM_FD, efx->link_fd,
GM_PAMBL_LEN, 0x7/*datasheet recommended */);
falcon_write(efx, ®, GM_CFG2_REG);
udelay(10);
/* Max frame len register */
max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
EFX_POPULATE_OWORD_1(reg, GM_MAX_FLEN, max_frame_len);
falcon_write(efx, ®, GM_MAX_FLEN_REG);
udelay(10);
/* FIFO configuration register 0 */
EFX_POPULATE_OWORD_5(reg,
GMF_FTFENREQ, 1,
GMF_STFENREQ, 1,
GMF_FRFENREQ, 1,
GMF_SRFENREQ, 1,
GMF_WTMENREQ, 1);
falcon_write(efx, ®, GMF_CFG0_REG);
udelay(10);
/* FIFO configuration register 1 */
EFX_POPULATE_OWORD_2(reg,
GMF_CFGFRTH, 0x12,
GMF_CFGXOFFRTX, 0xffff);
falcon_write(efx, ®, GMF_CFG1_REG);
udelay(10);
/* FIFO configuration register 2 */
EFX_POPULATE_OWORD_2(reg,
GMF_CFGHWM, 0x3f,
GMF_CFGLWM, 0xa);
falcon_write(efx, ®, GMF_CFG2_REG);
udelay(10);
/* FIFO configuration register 3 */
EFX_POPULATE_OWORD_2(reg,
GMF_CFGHWMFT, 0x1c,
GMF_CFGFTTH, 0x08);
falcon_write(efx, ®, GMF_CFG3_REG);
udelay(10);
/* FIFO configuration register 4 */
EFX_POPULATE_OWORD_1(reg, GMF_HSTFLTRFRM_PAUSE, 1);
falcon_write(efx, ®, GMF_CFG4_REG);
udelay(10);
/* FIFO configuration register 5 */
falcon_read(efx, ®, GMF_CFG5_REG);
EFX_SET_OWORD_FIELD(reg, GMF_CFGBYTMODE, bytemode);
EFX_SET_OWORD_FIELD(reg, GMF_CFGHDPLX, !efx->link_fd);
EFX_SET_OWORD_FIELD(reg, GMF_HSTDRPLT64, !efx->link_fd);
EFX_SET_OWORD_FIELD(reg, GMF_HSTFLTRFRMDC_PAUSE, 0);
falcon_write(efx, ®, GMF_CFG5_REG);
udelay(10);
/* MAC address */
EFX_POPULATE_OWORD_4(reg,
GM_HWADDR_5, efx->net_dev->dev_addr[5],
GM_HWADDR_4, efx->net_dev->dev_addr[4],
GM_HWADDR_3, efx->net_dev->dev_addr[3],
GM_HWADDR_2, efx->net_dev->dev_addr[2]);
falcon_write(efx, ®, GM_ADR1_REG);
udelay(10);
EFX_POPULATE_OWORD_2(reg,
GM_HWADDR_1, efx->net_dev->dev_addr[1],
GM_HWADDR_0, efx->net_dev->dev_addr[0]);
falcon_write(efx, ®, GM_ADR2_REG);
udelay(10);
falcon_reconfigure_mac_wrapper(efx);
}
