//! Turns on Target Vdd if enabled. //! //! @return //! \ref BDM_RC_OK => Target Vdd confirmed on target \n //! \ref BDM_RC_VDD_NOT_PRESENT => Target Vdd not present //! uint8_t bdm_setTargetVdd( void ) { uint8_t rc = BDM_RC_OK; #if (HW_CAPABILITY&CAP_VDDSENSE) DISABLE_VDD_SENSE_INT(); #endif switch (bdm_option.targetVdd) { case BDM_TARGET_VDD_OFF : VDD_OFF(); // Check for externally supplied target Vdd (> 2 V) WAIT_US(VDD_RISE_TIMEus); // Wait for Vdd to rise & stabilise if (bdm_targetVddMeasure()<VDD_2v) rc = BDM_RC_VDD_NOT_PRESENT; break; case BDM_TARGET_VDD_3V3 : VDD3_ON(); // Wait for Vdd to rise to 90% of 3V WAIT_WITH_TIMEOUT_MS( 100 /* ms */, (bdm_targetVddMeasure()>VDD_3v3)); WAIT_US(VDD_RISE_TIMEus); // Wait for Vdd to rise & stabilise if (bdm_targetVddMeasure()<VDD_3v3) { VDD_OFF(); // In case of Vdd overload rc = BDM_RC_VDD_NOT_PRESENT; } break; case BDM_TARGET_VDD_5V : VDD5_ON(); // Wait for Vdd to rise to 90% of 5V WAIT_WITH_TIMEOUT_MS( 100 /* ms */, (bdm_targetVddMeasure()>VDD_5v)); WAIT_US(VDD_RISE_TIMEus); // Wait for Vdd to rise & stabilise if (bdm_targetVddMeasure()<VDD_5v) { VDD_OFF(); // In case of Vdd overload rc = BDM_RC_VDD_NOT_PRESENT; } break; } #if (HW_CAPABILITY&CAP_VDDSENSE) CLEAR_VDD_SENSE_FLAG(); // Clear Vdd Change Event ENABLE_VDD_SENSE_INT(); #endif (void)bdm_checkTargetVdd(); // Update Target Vdd LED & status return (rc); }
//! Initialises the timers, input captures and interrupts //! uint8_t initTimers(void) { //==================================================================== // Set up timers TPMSC = TIMER_TPMxSC_VALUE; // Set timer tick rate // Set up Input capture & timeout timers TIMEOUT_TPMxCnSC = TIMEOUT_TPMxCnSC_OC_MASK; // TPMx.CHa : Output compare no pin #if (HW_CAPABILITY&CAP_BDM) BKGD_TPMxCnSC = BKGD_TPMxCnSC_FALLING_EDGE_MASK; // TPMx.CHb : Input capture, falling edge on pin #endif #if (HW_CAPABILITY&CAP_VDDSENSE) //==================================================================== // Set up Vdd monitoring (ACMP interrupts or Input capture) // Clear existing flag, enable falling & rising transitions (Vdd rising & falling!), enable Bandgap (~1.2V) CONFIGURE_VDD_SENSE(); // Capture Vdd rising & falling edges CLEAR_VDD_SENSE_FLAG(); // Clear Vdd Change Event ENABLE_VDD_SENSE_INT(); // Enable Vdd IC interrupts #endif #ifdef CONFIGURE_RESET_SENSE //=================================================================== // Setup RESET detection (Input Capture or keyboard interrupt) if (bdm_option.useResetSignal) { CONFIGURE_RESET_SENSE(); // Capture RESET falling edges CLEAR_RESET_SENSE_FLAG(); // Clear RESET IC Event ENABLE_RESET_SENSE_INT(); // Enable RESET IC interrupts } else DISABLE_RESET_SENSE_INT(); // Disable RESET IC interrupts #endif cable_status.reset = NO_RESET_ACTIVITY; // Clear the reset detection flag return BDM_RC_OK; }