/* * setup code for a handoff from a version 2 PMON 2000 PROM */ void setup_wired_tlb_entries(void) { write_c0_wired(0); local_flush_tlb_all(); /* marvell and extra space */ add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K); /* fpga, rtc, and uart */ add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M); }
static __init void wire_stupidity_into_tlb(void) { #ifdef CONFIG_32BIT write_c0_wired(0); local_flush_tlb_all(); /* marvell and extra space */ add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000UL, PM_64K); /* fpga, rtc, and uart */ add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000UL, PM_16M); // /* m-sys and internal SRAM */ // add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), // 0xfe000000UL, PM_16M); marvell_base = 0xf4000000; //mv64340_sram_base = 0xfe000000; /* Currently unused */ #endif }
/* setup code for a handoff from a version 2 PMON 2000 PROM */ void PMON_v2_setup(void) { /* Some wired TLB entries for the MV64340 and perhiperals. The MV64340 is going to be hit on every IRQ anyway - there's absolutely no point in letting it be a random TLB entry, as it'll just cause needless churning of the TLB. And we use the other half for the serial port, which is just a PITA otherwise :) Device Physical Virtual MV64340 Internal Regs 0xf4000000 0xf4000000 Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000 NVRAM (CS1) 0xfc800000 0xfc800000 UARTs (CS2) 0xfd000000 0xfd000000 Internal SRAM 0xfe000000 0xfe000000 M-Systems DOC (CS3) 0xff000000 0xff000000 */ /* marvell and extra space */ add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K); /* fpga, rtc, and uart */ add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M); /* m-sys and internal SRAM */ add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M); mv64340_base = 0xf4000000; }
void __init prom_init(void) { unsigned long extmem = 0, off, data; static unsigned long mem; unsigned long off1, data1; struct nvram_header *header; #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) /* These are not really being used anywhere - LR */ mips_machgroup = MACH_GROUP_BRCM; mips_machtype = MACH_BCM947XX; #endif off = (unsigned long)prom_init; data = *(unsigned long *)prom_init; off1 = off + 4; data1 = *(unsigned long *)off1; /* Figure out memory size by finding aliases */ for (mem = (1 MB); mem < (128 MB); mem <<= 1) { if ((*(unsigned long *)(off + mem) == data) && (*(unsigned long *)(off1 + mem) == data1)) break; } detectmem = mem; #if 0// defined(CONFIG_HIGHMEM) && !defined(CONFIG_BCM80211AC) if (mem == 128 MB) { early_tlb_init(); /* Add one temporary TLB entries to map SDRAM Region 2. * Physical Virtual * 0x80000000 0xc0000000 (1st: 256MB) * 0x90000000 0xd0000000 (2nd: 256MB) */ add_tmptlb_entry(ENTRYLO(SI_SDRAM_R2), ENTRYLO(SI_SDRAM_R2 + (256 MB)), EXTVBASE, PM_256M); off = EXTVBASE + __pa(off); for (extmem = (128 MB); extmem < (512 MB); extmem <<= 1) { if (*(unsigned long *)(off + extmem) == data) break; } extmem -= mem; /* Keep tlb entries back in consistent state */ early_tlb_init(); } #endif /* CONFIG_HIGHMEM */ /* Ignoring the last page when ddr size is 128M. Cached * accesses to last page is causing the processor to prefetch * using address above 128M stepping out of the ddr address * space. */ if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB))) mem -= 0x1000; /* CFE could have loaded nvram during netboot * to top 32KB of RAM, Just check for nvram signature * and copy it to nvram space embedded in linux * image for later use by nvram driver. */ header = (struct nvram_header *)(KSEG0ADDR(mem - NVRAM_SPACE)); if (ltoh32(header->magic) == NVRAM_MAGIC) { uint32 *src = (uint32 *)header; uint32 *dst = (uint32 *)ram_nvram_buf; uint32 i; printk("Copying NVRAM bytes: %d from: 0x%p To: 0x%p\n", ltoh32(header->len), src, dst); for (i = 0; i < ltoh32(header->len) && i < NVRAM_SPACE; i += 4) *dst++ = ltoh32(*src++); } add_memory_region(SI_SDRAM_BASE, mem, BOOT_MEM_RAM); #if 0// defined(CONFIG_HIGHMEM) && !defined(CONFIG_BCM80211AC) if (extmem) { /* We should deduct 0x1000 from the second memory * region, because of the fact that processor does prefetch. * Now that we are deducting a page from second memory * region, we could add the earlier deducted 4KB (from first bank) * to the second region (the fact that 0x80000000 -> 0x88000000 * shadows 0x0 -> 0x8000000) */ if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB))) extmem -= 0x1000; add_memory_region(SI_SDRAM_R2 + (128 MB) - 0x1000, extmem, BOOT_MEM_RAM); } #endif /* CONFIG_HIGHMEM */ }
void __init prom_init(void) { unsigned long mem, extmem = 0, off, data; mips_machgroup = MACH_GROUP_BRCM; mips_machtype = MACH_BCM947XX; off = (unsigned long)prom_init; data = *(unsigned long *)prom_init; /* Figure out memory size by finding aliases */ for (mem = (1 MB); mem < (128 MB); mem <<= 1) { if (*(unsigned long *)(off + mem) == data) break; } #if CONFIG_RAM_SIZE { unsigned long config_mem; config_mem = CONFIG_RAM_SIZE * 0x100000; if (config_mem < mem) mem = config_mem; } #endif #ifdef CONFIG_HIGHMEM if (mem == 128 MB) { early_tlb_init(); /* Add one temporary TLB entries to map SDRAM Region 2. * Physical Virtual * 0x80000000 0xc0000000 (1st: 256MB) * 0x90000000 0xd0000000 (2nd: 256MB) */ add_tmptlb_entry(ENTRYLO(SI_SDRAM_R2), ENTRYLO(SI_SDRAM_R2 + (256 MB)), EXTVBASE, PM_256M); off = EXTVBASE + __pa(off); for (extmem = (128 MB); extmem < (512 MB); extmem <<= 1) { if (*(unsigned long *)(off + extmem) == data) break; } extmem -= mem; /* Keep tlb entries back in consistent state */ early_tlb_init(); } #endif /* CONFIG_HIGHMEM */ /* Ignoring the last page when ddr size is 128M. Cached * accesses to last page is causing the processor to prefetch * using address above 128M stepping out of the ddr address * space. */ if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB))) mem -= 0x1000; add_memory_region(SI_SDRAM_BASE, mem, BOOT_MEM_RAM); #ifdef CONFIG_HIGHMEM if (extmem) { /* We should deduct 0x1000 from the second memory * region, because of the fact that processor does prefetch. * Now that we are deducting a page from second memory * region, we could add the earlier deducted 4KB (from first bank) * to the second region (the fact that 0x80000000 -> 0x88000000 * shadows 0x0 -> 0x8000000) */ if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB))) extmem -= 0x1000; add_memory_region(SI_SDRAM_R2 + (128 MB) - 0x1000, extmem, BOOT_MEM_RAM); } #endif /* CONFIG_HIGHMEM */ }