int spi_claim_bus(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); unsigned char pm = fsl->pm; unsigned int cs = slave->cs; unsigned int mode = fsl->mode; unsigned int div16 = fsl->div16; int i; debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs); /* Enable eSPI interface */ out_be32(&espi->mode, ESPI_MODE_RXTHR(3) | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ /* Init CS mode interface */ for (i = 0; i < ESPI_MAX_CS_NUM; i++) out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); /* Set eSPI BRG clock source */ out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) | ESPI_CSMODE_PM(pm) | div16); /* Set eSPI mode */ if (mode & SPI_CPHA) out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) | ESPI_CSMODE_CP_BEGIN_EDGCLK); if (mode & SPI_CPOL) out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) | ESPI_CSMODE_CI_INACTIVEHIGH); /* Character bit order: msb first */ out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) | ESPI_CSMODE_REV_MSB_FIRST); /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) | ESPI_CSMODE_LEN(7)); return 0; }
// ============================================================================= // 功能:SPI控制寄存器参数配置,如PHA和CPOL、时钟等,根据各种寄存器而异 // 参数:tpSPI,SPI控制器基址 // ptr,参数指针 // 返回:无 // ============================================================================= void __SPI_Config(volatile tagSpiReg *tpSpi,u8 cs,tagSpiConfig *tagpInConfig) { u8 pm; u32 mode,div16; mode = tagpInConfig->Mode; pm = __spi_clk_cal(tagpInConfig->Freq,&div16); /* Enable eSPI interface */ tpSpi->mode = ESPI_MODE_RXTHR(3) | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN; tpSpi->event = 0xffffffff; /* Clear all eSPI events */ tpSpi->mask = 0x00000000; /* Mask all eSPI interrupts */ /* Init CS0,1,2,3 mode interface */ if(cs < 4) { tpSpi->csmode[cs] = ESPI_CSMODE_INIT_VAL; tpSpi->csmode[cs] = tpSpi->csmode[cs] & ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)); /* Set eSPI BRG clock source */ tpSpi->csmode[cs] = tpSpi->csmode[cs] | ESPI_CSMODE_PM(pm) | div16; /* Set eSPI mode */ if (mode & SPI_CPHA) tpSpi->csmode[cs] = tpSpi->csmode[cs] | ESPI_CSMODE_CP_BEGIN_EDGCLK; if (mode & SPI_CPOL) tpSpi->csmode[cs] = tpSpi->csmode[cs] | ESPI_CSMODE_CI_INACTIVEHIGH; /* Character bit order: msb/lsb first */ if(tagpInConfig->ShiftDir == SPI_SHIFT_MSB) tpSpi->csmode[cs] = tpSpi->csmode[cs] | ESPI_CSMODE_REV_MSB_FIRST; else tpSpi->csmode[cs] = tpSpi->csmode[cs] & (~ESPI_CSMODE_REV_MSB_FIRST); /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ tpSpi->csmode[cs] = tpSpi->csmode[cs] | ESPI_CSMODE_LEN(7); } }