/******************************************************************************
* mv_eth_tool_get_regs
* Description:
* ethtool get registers array
* INPUT:
* netdev Network device structure pointer
* regs registers information
* OUTPUT
* p registers array
* RETURN:
* None
*
*******************************************************************************/
void mv_eth_tool_get_regs(struct net_device *netdev,
struct ethtool_regs *regs, void *p)
{
struct eth_port *priv = MV_ETH_PRIV(netdev);
uint32_t *regs_buff = p;
memset(p, 0, MV_ETH_TOOL_REGS_LEN * sizeof(uint32_t));
regs->version = mvCtrlModelRevGet();
/* ETH port registers */
regs_buff[0] = MV_REG_READ(ETH_PORT_STATUS_REG(priv->port));
regs_buff[1] = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(priv->port));
regs_buff[2] = MV_REG_READ(ETH_PORT_CONFIG_REG(priv->port));
regs_buff[3] = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(priv->port));
regs_buff[4] = MV_REG_READ(ETH_SDMA_CONFIG_REG(priv->port));
/* regs_buff[5] = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(priv->port)); */
regs_buff[6] = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(priv->port));
/* regs_buff[7] = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(priv->port)); */
regs_buff[8] = MV_REG_READ(ETH_INTR_CAUSE_REG(priv->port));
regs_buff[9] = MV_REG_READ(ETH_INTR_CAUSE_EXT_REG(priv->port));
regs_buff[10] = MV_REG_READ(ETH_INTR_MASK_REG(priv->port));
regs_buff[11] = MV_REG_READ(ETH_INTR_MASK_EXT_REG(priv->port));
/* ETH Unit registers */
regs_buff[16] = MV_REG_READ(ETH_PHY_ADDR_REG(priv->port));
regs_buff[17] = MV_REG_READ(ETH_UNIT_INTR_CAUSE_REG(priv->port));
regs_buff[18] = MV_REG_READ(ETH_UNIT_INTR_MASK_REG(priv->port));
regs_buff[19] = MV_REG_READ(ETH_UNIT_ERROR_ADDR_REG(priv->port));
regs_buff[20] = MV_REG_READ(ETH_UNIT_INT_ADDR_ERROR_REG(priv->port));
}
/* Print important registers of Ethernet port */
void ethPortRegs(int port)
{
mvOsPrintf("\t ethGiga #%d port Registers:\n", port);
mvOsPrintf("ETH_PORT_STATUS_REG : 0x%X = 0x%08x\n",
ETH_PORT_STATUS_REG(port),
MV_REG_READ( ETH_PORT_STATUS_REG(port) ) );
mvOsPrintf("ETH_PORT_SERIAL_CTRL_REG : 0x%X = 0x%08x\n",
ETH_PORT_SERIAL_CTRL_REG(port),
MV_REG_READ( ETH_PORT_SERIAL_CTRL_REG(port) ) );
mvOsPrintf("ETH_PORT_CONFIG_REG : 0x%X = 0x%08x\n",
ETH_PORT_CONFIG_REG(port),
MV_REG_READ( ETH_PORT_CONFIG_REG(port) ) );
mvOsPrintf("ETH_PORT_CONFIG_EXTEND_REG : 0x%X = 0x%08x\n",
ETH_PORT_CONFIG_EXTEND_REG(port),
MV_REG_READ( ETH_PORT_CONFIG_EXTEND_REG(port) ) );
mvOsPrintf("ETH_SDMA_CONFIG_REG : 0x%X = 0x%08x\n",
ETH_SDMA_CONFIG_REG(port),
MV_REG_READ( ETH_SDMA_CONFIG_REG(port) ) );
mvOsPrintf("ETH_MAX_TRANSMIT_UNIT : 0x%X = 0x%08x\n",
ETH_MAX_TRANSMIT_UNIT_REG(port),
MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) );
mvOsPrintf("ETH_TX_FIFO_URGENT_THRESH_REG : 0x%X = 0x%08x\n",
ETH_TX_FIFO_URGENT_THRESH_REG(port),
MV_REG_READ( ETH_TX_FIFO_URGENT_THRESH_REG(port) ) );
mvOsPrintf("ETH_RX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n",
ETH_RX_QUEUE_COMMAND_REG(port),
MV_REG_READ( ETH_RX_QUEUE_COMMAND_REG(port) ) );
mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n",
ETH_TX_QUEUE_COMMAND_REG(port),
MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) );
mvOsPrintf("ETH_INTR_CAUSE_REG : 0x%X = 0x%08x\n",
ETH_INTR_CAUSE_REG(port),
MV_REG_READ( ETH_INTR_CAUSE_REG(port) ) );
mvOsPrintf("ETH_INTR_EXTEND_CAUSE_REG : 0x%X = 0x%08x\n",
ETH_INTR_CAUSE_EXT_REG(port),
MV_REG_READ( ETH_INTR_CAUSE_EXT_REG(port) ) );
mvOsPrintf("ETH_INTR_MASK_REG : 0x%X = 0x%08x\n",
ETH_INTR_MASK_REG(port),
MV_REG_READ( ETH_INTR_MASK_REG(port) ) );
mvOsPrintf("ETH_INTR_EXTEND_MASK_REG : 0x%X = 0x%08x\n",
ETH_INTR_MASK_EXT_REG(port),
MV_REG_READ( ETH_INTR_MASK_EXT_REG(port) ) );
mvOsPrintf("ETH_ACCESS_PROTECT_REG : 0x%X = 0x%08x\n",
ETH_ACCESS_PROTECT_REG(port),
MV_REG_READ( ETH_ACCESS_PROTECT_REG(port) ) );
mvOsPrintf("ETH_UNIT_DEBUG_0_REG : 0x%X = 0x%08x\n",
ETH_UNIT_DEBUG_0_REG, MV_REG_READ( ETH_UNIT_DEBUG_0_REG ) );
mvOsPrintf("ETH_UNIT_DEBUG_1_REG : 0x%X = 0x%08x\n",
ETH_UNIT_DEBUG_1_REG, MV_REG_READ( ETH_UNIT_DEBUG_1_REG ) );
mvOsPrintf("ETH_PORT_DEBUG_0_REG : 0x%X = 0x%08x\n",
ETH_PORT_DEBUG_0_REG(port), MV_REG_READ( ETH_PORT_DEBUG_0_REG(port)) );
mvOsPrintf("ETH_PORT_DEBUG_1_REG : 0x%X = 0x%08x\n",
ETH_PORT_DEBUG_1_REG(port), MV_REG_READ( ETH_PORT_DEBUG_1_REG(port)) );
mvOsPrintf("ETH_RX_DESCR_STAT_CMD_REG : 0x%X = 0x%08x\n",
ETH_RX_DESCR_STAT_CMD_REG(port, 0),
MV_REG_READ( ETH_RX_DESCR_STAT_CMD_REG(port, 0) ) );
mvOsPrintf("ETH_RX_BYTE_COUNT_REG : 0x%X = 0x%08x\n",
ETH_RX_BYTE_COUNT_REG(port, 0),
MV_REG_READ( ETH_RX_BYTE_COUNT_REG(port, 0) ) );
mvOsPrintf("ETH_RX_BUF_PTR_REG : 0x%X = 0x%08x\n",
ETH_RX_BUF_PTR_REG(port, 0),
MV_REG_READ( ETH_RX_BUF_PTR_REG(port, 0) ) );
mvOsPrintf("ETH_RX_CUR_DESC_PTR_REG : 0x%X = 0x%08x\n",
ETH_RX_CUR_DESC_PTR_REG(port, 0),
MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, 0) ) );
}
