void map_init_Irem(BYTE model) {
switch (model) {
case G101:
EXTCL_CPU_WR_MEM(Irem_G101);
EXTCL_SAVE_MAPPER(Irem_G101);
mapper.internal_struct[0] = (BYTE *) &irem_G101;
mapper.internal_struct_size[0] = sizeof(irem_G101);
if (info.reset >= HARD) {
memset(&irem_G101, 0x00, sizeof(irem_G101));
mapper.rom_map_to[0] = 0;
mapper.rom_map_to[1] = info.prg.rom[0].max.banks_8k;
mapper.rom_map_to[2] = info.prg.rom[0].max.banks_8k_before_last;
mapper.rom_map_to[3] = info.prg.rom[0].max.banks_8k;
if (info.id == MAJORLEAGUE) {
mirroring_SCR0();
}
}
break;
case H3000:
EXTCL_CPU_WR_MEM(Irem_H3000);
EXTCL_SAVE_MAPPER(Irem_H3000);
EXTCL_CPU_EVERY_CYCLE(Irem_H3000);
mapper.internal_struct[0] = (BYTE *) &irem_H3000;
mapper.internal_struct_size[0] = sizeof(irem_H3000);
if (info.reset >= HARD) {
memset(&irem_H3000, 0x00, sizeof(irem_H3000));
}
break;
case LROG017:
EXTCL_CPU_WR_MEM(Irem_LROG017);
EXTCL_SAVE_MAPPER(Irem_LROG017);
EXTCL_WR_CHR(Irem_LROG017);
mapper.internal_struct[0] = (BYTE *) &irem_LROG017;
mapper.internal_struct_size[0] = sizeof(irem_LROG017);
/* utilizza 0x1800 di CHR RAM extra */
map_chr_ram_extra_init(0x1800);
if (info.reset >= HARD) {
memset(&irem_LROG017, 0x00, sizeof(irem_LROG017));
map_chr_ram_extra_reset();
map_prg_rom_8k(4, 0, 0);
}
irem_LROG017_chr_ram();
break;
case TAMS1:
EXTCL_CPU_WR_MEM(Irem_TAMS1);
if (info.reset >= HARD) {
map_prg_rom_8k(2, 0, info.prg.rom[0].max.banks_16k);
map_prg_rom_8k(2, 2, 0);
}
break;
}
}
void map_init_217(void) {
EXTCL_CPU_WR_MEM(217);
EXTCL_SAVE_MAPPER(217);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &m217;
mapper.internal_struct_size[0] = sizeof(m217);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
m217.reg[0] = 0x00;
m217.reg[1] = 0xFF;
m217.reg[2] = 0x03;
}
m217.reg[3] = FALSE;
m217.prg_8k_bank[0] = 0;
m217.prg_8k_bank[1] = 1;
m217.prg_8k_bank[2] = info.prg.rom.max.banks_8k_before_last;
m217.prg_8k_bank[3] = info.prg.rom.max.banks_8k;
info.mapper.extend_wr = TRUE;
irqA12.present = TRUE;
irqA12_delay = 1;
}
void map_init_BMC70IN1(BYTE type) {
EXTCL_CPU_WR_MEM(BMC70IN1);
EXTCL_CPU_RD_MEM(BMC70IN1);
EXTCL_SAVE_MAPPER(BMC70IN1);
mapper.internal_struct[0] = (BYTE *) &bmc70in1;
mapper.internal_struct_size[0] = sizeof(bmc70in1);
memset(&bmc70in1, 0x00, sizeof(bmc70in1));
map_chr_bank_1k_reset();
if (info.reset >= HARD) {
if (type == BMC70IN1) {
bmc70in1_reset = 0x0D;
} else {
bmc70in1_reset = 0x06;
}
} else if (info.reset == RESET) {
bmc70in1_reset++;
bmc70in1_reset = bmc70in1_reset & 0x0F;
}
bmc70in1_type = type;
info.mapper.extend_rd = TRUE;
extcl_cpu_wr_mem_BMC70IN1(0x0000, 0);
}
void map_init_Ntdec(BYTE model) {
switch (model) {
case ASDER:
EXTCL_CPU_WR_MEM(Ntdec_asder);
EXTCL_SAVE_MAPPER(Ntdec_asder);
mapper.internal_struct[0] = (BYTE *) &asder;
mapper.internal_struct_size[0] = sizeof(asder);
if (info.reset >= HARD) {
memset(&asder, 0x00, sizeof(asder));
}
break;
case FHERO:
EXTCL_CPU_WR_MEM(Ntdec_fhero);
info.mapper.extend_wr = TRUE;
if (info.reset >= HARD) {
map_prg_rom_8k(4, 0, info.prg.rom.max.banks_32k);
}
break;
}
mirroring_V();
}
void map_init_CNROM() {
EXTCL_CPU_WR_MEM(CNROM);
mask = state = 0x00;
/*
* "Cybernoid - The Fighting Machine (U) [!].nes" vuole
* la gestione del bus conflict per funzionare correttamente.
*/
if ((info.id >= CNROM_26CE27CE) && (info.id <= CNROM_26NCE27NCE)) {
EXTCL_RD_CHR(CNROM);
EXTCL_SAVE_MAPPER(CNROM);
mapper.internal_struct[0] = (BYTE *) &cnrom_2627;
mapper.internal_struct_size[0] = sizeof(cnrom_2627);
memset(&cnrom_2627, 0x00, sizeof(cnrom_2627));
mask = 0x03;
switch (info.id) {
case CNROM_26CE27CE:
state = 0x03;
break;
case CNROM_26CE27NCE:
state = 0x01;
break;
case CNROM_26NCE27CE:
state = 0x02;
break;
case CNROM_26NCE27NCE:
state = 0x00;
break;
}
}
}
void map_init_121(void) {
EXTCL_CPU_WR_MEM(121);
EXTCL_CPU_RD_MEM(121);
EXTCL_SAVE_MAPPER(121);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &m121;
mapper.internal_struct_size[0] = sizeof(m121);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
info.mapper.extend_wr = TRUE;
if (info.reset >= HARD) {
memset(&m121, 0x00, sizeof(m121));
memset(&mmc3, 0x00, sizeof(mmc3));
m121.bck[0] = mapper.rom_map_to[0];
m121.bck[1] = mapper.rom_map_to[2];
}
memset(&irqA12, 0x00, sizeof(irqA12));
irqA12.present = TRUE;
irqA12_delay = 1;
}
void map_init_AC08(void) {
EXTCL_CPU_WR_MEM(AC08);
EXTCL_CPU_RD_MEM(AC08);
EXTCL_SAVE_MAPPER(AC08);
mapper.internal_struct[0] = (BYTE *) &ac08;
mapper.internal_struct_size[0] = sizeof(ac08);
ac08.reg = 0;
extcl_cpu_wr_mem_AC08(0x8000, 0);
{
BYTE base, value;
base = 1;
_control_bank(base, info.prg.max_chips)
value = 0;
control_bank(info.prg.rom[base].max.banks_32k)
map_prg_rom_8k_chip(4, 0, value, base);
map_prg_rom_8k_update();
}
info.mapper.extend_wr = TRUE;
}
void map_init_83(void) {
EXTCL_CPU_WR_MEM(83);
EXTCL_CPU_RD_MEM(83);
EXTCL_SAVE_MAPPER(83);
EXTCL_CPU_EVERY_CYCLE(83);
mapper.internal_struct[0] = (BYTE *) &m83;
mapper.internal_struct_size[0] = sizeof(m83);
if (info.reset >= HARD) {
memset(&m83, 0x00, sizeof(m83));
}
sync_83();
switch(info.id) {
case MAP83_REG0:
m83.dip = 0;
break;
case MAP83_DGP:
m83.dip = 0xFF;
info.prg.ram.banks_8k_plus = 1;
break;
default:
m83.dip = 0xFF;
break;
}
info.mapper.extend_wr = TRUE;
}
void map_init_91(void) {
EXTCL_CPU_WR_MEM(91);
EXTCL_SAVE_MAPPER(91);
EXTCL_PPU_256_TO_319(91);
mapper.internal_struct[0] = (BYTE *) &m91;
mapper.internal_struct_size[0] = sizeof(m91);
memset(&m91, 0x00, sizeof(m91));
info.mapper.extend_wr = TRUE;
}
void map_init_57(void) {
EXTCL_CPU_WR_MEM(57);
EXTCL_SAVE_MAPPER(57);
mapper.internal_struct[0] = (BYTE *) &m57;
mapper.internal_struct_size[0] = sizeof(m57);
if (info.reset >= HARD) {
memset(&m57, 0x00, sizeof(m57));
extcl_cpu_wr_mem_57(0x8800, 0x00);
}
}
void map_init_SC_127(void) {
EXTCL_CPU_WR_MEM(SC_127);
EXTCL_CPU_RD_MEM(SC_127);
EXTCL_SAVE_MAPPER(SC_127);
EXTCL_PPU_256_TO_319(SC_127);
mapper.internal_struct[0] = (BYTE *) &sc127;
mapper.internal_struct_size[0] = sizeof(sc127);
memset(&sc127, 0x00, sizeof(sc127));
info.prg.ram.banks_8k_plus = 1;
}
void map_init_VRC3(void) {
EXTCL_CPU_WR_MEM(VRC3);
EXTCL_SAVE_MAPPER(VRC3);
EXTCL_CPU_EVERY_CYCLE(VRC3);
mapper.internal_struct[0] = (BYTE *) &vrc3;
mapper.internal_struct_size[0] = sizeof(vrc3);
info.prg.ram.banks_8k_plus = 1;
if (info.reset) {
memset(&vrc3, 0x00, sizeof(vrc3));
vrc3.mask = 0xFFFF;
}
}
void map_init_Whirlwind(void) {
EXTCL_CPU_WR_MEM(Whirlwind);
EXTCL_CPU_RD_MEM(Whirlwind);
EXTCL_SAVE_MAPPER(Whirlwind);
mapper.internal_struct[0] = (BYTE *) &whirlwind;
mapper.internal_struct_size[0] = sizeof(whirlwind);
info.prg.ram.banks_8k_plus = FALSE;
if (info.reset >= HARD) {
memset(&whirlwind, 0x00, sizeof(whirlwind));
map_prg_rom_8k(4, 0, info.prg.rom.max.banks_32k);
}
}
void map_init_KS7037(void) {
EXTCL_AFTER_MAPPER_INIT(KS7037);
EXTCL_CPU_WR_MEM(KS7037);
EXTCL_CPU_RD_MEM(KS7037);
EXTCL_SAVE_MAPPER(KS7037);
mapper.internal_struct[0] = (BYTE *) &ks7037;
mapper.internal_struct_size[0] = sizeof(ks7037);
memset(&ks7037, 0x00, sizeof(ks7037));
info.prg.ram.banks_8k_plus = 1;
info.mapper.extend_rd = TRUE;
info.mapper.extend_wr = TRUE;
info.mapper.ram_plus_op_controlled_by_mapper = TRUE;
}
void map_init_BMC411120C(void) {
EXTCL_CPU_WR_MEM(BMC411120C);
EXTCL_SAVE_MAPPER(BMC411120C);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &bmc411120c;
mapper.internal_struct_size[0] = sizeof(bmc411120c);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
memset(&bmc411120c, 0x00, sizeof(bmc411120c));
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
{
BYTE i;
map_prg_rom_8k_reset();
map_chr_bank_1k_reset();
for (i = 0; i < 8; i++) {
if (i < 4) {
bmc411120c.prg_map[i] = mapper.rom_map_to[i];
}
bmc411120c.chr_map[i] = i;
}
}
if (info.reset >= HARD) {
bmc411120c_reset = 0;
} else if (info.reset == RESET) {
bmc411120c_reset ^= 0x04;
}
bmc411120c_update_prg();
bmc411120c_update_chr();
info.mapper.extend_wr = TRUE;
irqA12.present = TRUE;
irqA12_delay = 1;
}
void map_init_BB(void) {
EXTCL_CPU_WR_MEM(BB);
EXTCL_CPU_RD_MEM(BB);
EXTCL_SAVE_MAPPER(BB);
mapper.internal_struct[0] = (BYTE *) &bb;
mapper.internal_struct_size[0] = sizeof(bb);
{
BYTE value = 0xFF;
control_bank(info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
}
bb.reg = 0xFF;
_control_bank(bb.reg, info.prg.rom[0].max.banks_8k)
bb_prg_6000 = prg_chip_byte_pnt(0, bb.reg << 13);
}
void map_init_186(void) {
EXTCL_CPU_WR_MEM(186);
EXTCL_CPU_RD_MEM(186);
EXTCL_SAVE_MAPPER(186);
mapper.internal_struct[0] = (BYTE *) &m186;
mapper.internal_struct_size[0] = sizeof(m186);
info.mapper.extend_wr = TRUE;
info.prg.ram.banks_8k_plus = 0;
cpu.prg_ram_wr_active = TRUE;
cpu.prg_ram_rd_active = TRUE;
if (info.reset >= HARD) {
memset(&m186, 0x00, sizeof(m186));
m186.prg_ram_bank2 = prg_chip(0);
map_prg_rom_8k(2, 0, 0);
map_prg_rom_8k(2, 2, 0);
}
}
void map_init_164(void) {
EXTCL_CPU_WR_MEM(164);
EXTCL_CPU_RD_MEM(164);
EXTCL_SAVE_MAPPER(164);
mapper.internal_struct[0] = (BYTE *) &m164;
mapper.internal_struct_size[0] = sizeof(m164);
memset(&m164, 0x00, sizeof(m164));
m164.prg = 0x0F;
{
BYTE value = m164.prg;
control_bank(info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
}
info.mapper.extend_wr = TRUE;
}
void map_init_182(void) {
EXTCL_CPU_WR_MEM(182);
EXTCL_SAVE_MAPPER(MMC3);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &mmc3;
mapper.internal_struct_size[0] = sizeof(mmc3);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
}
irqA12.present = TRUE;
irqA12_delay = 1;
}
void map_init_SL1632(void) {
EXTCL_CPU_WR_MEM(SL1632);
EXTCL_SAVE_MAPPER(SL1632);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &sl1632;
mapper.internal_struct_size[0] = sizeof(sl1632);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
memset(&sl1632, 0x00, sizeof(sl1632));
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
{
BYTE i;
map_prg_rom_8k_reset();
map_chr_bank_1k_reset();
for (i = 0; i < 8; i++) {
if (i < 4) {
sl1632.mmc3.prg_map[i] = mapper.rom_map_to[i];
}
sl1632.mmc3.chr_map[i] = sl1632.chr_map[i] = i;
}
sl1632.prg_map[0] = mapper.rom_map_to[0];
sl1632.prg_map[1] = mapper.rom_map_to[1];
}
info.mapper.extend_wr = TRUE;
irqA12.present = TRUE;
irqA12_delay = 1;
}
void map_init_254(void) {
EXTCL_CPU_WR_MEM(254);
EXTCL_CPU_RD_MEM(254);
EXTCL_SAVE_MAPPER(254);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &m254;
mapper.internal_struct_size[0] = sizeof(m254);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
memset(&m254, 0x00, sizeof(m254));
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
irqA12.present = TRUE;
irqA12_delay = 1;
}
void map_init_EH8813A(void) {
EXTCL_CPU_WR_MEM(EH8813A);
EXTCL_CPU_RD_MEM(EH8813A);
EXTCL_SAVE_MAPPER(EH8813A);
mapper.internal_struct[0] = (BYTE *) &eh88131a;
mapper.internal_struct_size[0] = sizeof(eh88131a);
if (info.reset >= HARD) {
eh88131a.address = 0;
eh88131a.hwmode = 0;
}
if (info.reset == RESET) {
eh88131a.address = 0;
eh88131a.hwmode = (eh88131a.hwmode + 1) & 0x0F;
}
map_prg_rom_8k(4, 0, 0);
map_chr_bank_1k_reset();
mirroring_V();
info.mapper.extend_rd = TRUE;
}
void map_init_Waixing(BYTE model) {
switch (model) {
case WPSX:
EXTCL_CPU_WR_MEM(Waixing_PSx);
map_prg_rom_8k(4, 0, 0);
break;
case WTB:
EXTCL_CPU_WR_MEM(Waixing_type_B);
EXTCL_SAVE_MAPPER(Waixing_type_B);
EXTCL_WR_CHR(Waixing_type_B);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &waixing;
mapper.internal_struct_size[0] = sizeof(waixing);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
/* utilizza 0x2000 di CHR RAM extra */
map_chr_ram_extra_init(0x2000);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
memset(&waixing, 0x00, sizeof(waixing));
map_chr_ram_extra_reset();
{
BYTE i;
map_chr_bank_1k_reset();
for (i = 0; i < 8; i++) {
waixing.chr_map[i] = i;
}
}
}
irqA12.present = TRUE;
irqA12_delay = 1;
break;
case WTA:
case WTC:
case WTD:
case WTE:
if (model == WTA) {
min = 0x08;
max = 0x09;
} else if (model == WTC) {
min = 0x08;
max = 0x0B;
} else if (model == WTD) {
min = 0x00;
max = 0x01;
} else if (model == WTE) {
min = 0x00;
max = 0x03;
}
EXTCL_CPU_WR_MEM(Waixing_type_ACDE);
EXTCL_SAVE_MAPPER(Waixing_type_ACDE);
EXTCL_WR_CHR(Waixing_type_ACDE);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &waixing;
mapper.internal_struct_size[0] = sizeof(waixing);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
/* utilizza 0x2000 di CHR RAM extra */
map_chr_ram_extra_init(0x2000);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
memset(&waixing, 0x00, sizeof(waixing));
map_chr_ram_extra_reset();
{
BYTE i;
map_chr_bank_1k_reset();
for (i = 0; i < 8; i++) {
waixing.chr_map[i] = i;
if ((waixing.chr_map[i] >= min) && (waixing.chr_map[i] <= max)) {
chr.bank_1k[i] = &chr.extra.data[(waixing.chr_map[i] - min) << 10];
}
}
}
}
irqA12.present = TRUE;
irqA12_delay = 1;
break;
case WTG:
EXTCL_CPU_WR_MEM(Waixing_type_G);
EXTCL_SAVE_MAPPER(Waixing_type_G);
EXTCL_WR_CHR(Waixing_type_G);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &waixing;
mapper.internal_struct_size[0] = sizeof(waixing);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
/* utilizza 0x2000 di CHR RAM extra */
map_chr_ram_extra_init(0x2000);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
memset(&waixing, 0x00, sizeof(waixing));
map_chr_ram_extra_reset();
{
BYTE i;
map_chr_bank_1k_reset();
for (i = 0; i < 8; i++) {
waixing.chr_map[i] = i;
if (waixing.chr_map[i] < 8) {
chr.bank_1k[i] = &chr.extra.data[waixing.chr_map[i] << 10];
}
}
}
}
irqA12.present = TRUE;
irqA12_delay = 1;
break;
case WTH:
EXTCL_CPU_WR_MEM(Waixing_type_H);
EXTCL_SAVE_MAPPER(Waixing_type_H);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &waixing;
mapper.internal_struct_size[0] = sizeof(waixing);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
/* utilizza 0x2000 di CHR RAM extra */
map_chr_ram_extra_init(0x2000);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
memset(&waixing, 0x00, sizeof(waixing));
map_chr_ram_extra_reset();
{
BYTE i, value;
map_prg_rom_8k_reset();
map_chr_bank_1k_reset();
for (i = 0; i < 8; i++) {
if (i < 4) {
waixing.prg_map[i] = mapper.rom_map_to[i];
}
waixing.chr_map[i] = i;
if (mapper.write_vram) {
chr.bank_1k[i] = &chr.extra.data[waixing.chr_map[i] << 10];
}
}
waixing_type_H_prg_8k_update()
}
}
irqA12.present = TRUE;
irqA12_delay = 1;
break;
case SH2:
EXTCL_CPU_WR_MEM(Waixing_SH2);
EXTCL_SAVE_MAPPER(Waixing_SH2);
EXTCL_AFTER_RD_CHR(Waixing_SH2);
EXTCL_UPDATE_R2006(Waixing_SH2);
EXTCL_WR_CHR(Waixing_SH2);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
mapper.internal_struct[0] = (BYTE *) &waixing;
mapper.internal_struct_size[0] = sizeof(waixing);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
/* utilizza 0x2000 di CHR RAM extra */
map_chr_ram_extra_init(0x2000);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
memset(&waixing, 0x00, sizeof(waixing));
map_chr_ram_extra_reset();
waixing.reg = 0xFD;
waixing.ctrl[0] = 1;
waixing.ctrl[1] = 1;
map_prg_rom_8k_reset();
map_chr_bank_1k_reset();
waixing.chr_map[0] = 0;
waixing.chr_map[1] = 0;
waixing.chr_map[2] = 0;
waixing.chr_map[4] = 0;
waixing_SH2_PPUFD();
}
irqA12.present = TRUE;
irqA12_delay = 1;
break;
}
void map_init_Bandai(BYTE model) {
chr_ram_4k_max = info.chr.rom[0].banks_4k - 1;
switch (model) {
case B161X02X74:
EXTCL_CPU_WR_MEM(Bandai_161x02x74);
EXTCL_SAVE_MAPPER(Bandai_161x02x74);
EXTCL_UPDATE_R2006(Bandai_161x02x74);
EXTCL_RD_NMT(Bandai_161x02x74);
mapper.internal_struct[0] = (BYTE *) &b161x02x74;
mapper.internal_struct_size[0] = sizeof(b161x02x74);
if (info.reset >= HARD) {
b161x02x74.chr_rom_bank = 0;
map_prg_rom_8k(4, 0, 0);
{
BYTE value, save = 0;
DBWORD bank;
b161x02x74_chr_4k_update();
}
}
break;
case FCGx:
case E24C01:
case E24C02:
case DATACH: {
EXTCL_CPU_WR_MEM(Bandai_FCGX);
EXTCL_CPU_RD_MEM(Bandai_FCGX);
EXTCL_SAVE_MAPPER(Bandai_FCGX);
EXTCL_BATTERY_IO(Bandai_FCGX);
EXTCL_CPU_EVERY_CYCLE(Bandai_FCGX);
mapper.internal_struct[0] = (BYTE *) &FCGX;
mapper.internal_struct_size[0] = sizeof(FCGX);
info.mapper.extend_wr = TRUE;
if (info.reset >= HARD) {
memset(&FCGX, 0x00, sizeof(FCGX));
FCGX.e0.output = FCGX.e1.output = 0x10;
if (info.prg.rom[0].banks_16k >= 32) {
map_prg_rom_8k(2, 2, info.prg.rom[0].max.banks_16k);
}
} else {
BYTE i;
for (i = 0; i < 8; i++) {
FCGX.reg[i] = 0;
}
}
switch (model) {
case E24C01:
info.prg.ram.bat.banks = TRUE;
FCGX.e0.size = 128;
break;
case E24C02:
info.prg.ram.bat.banks = TRUE;
FCGX.e0.size = 256;
break;
case DATACH:
info.prg.ram.bat.banks = TRUE;
FCGX.e0.size = 256;
FCGX.e1.size = 128;
break;
}
break;
}
}
switch (info.id) {
case FAMICOMJUMPII:
info.prg.ram.banks_8k_plus = 1;
info.prg.ram.bat.banks = 1;
break;
}
type = model;
}
void map_init_MMC5(void) {
EXTCL_CPU_WR_MEM(MMC5);
EXTCL_CPU_RD_MEM(MMC5);
EXTCL_SAVE_MAPPER(MMC5);
EXTCL_PPU_256_TO_319(MMC5);
EXTCL_PPU_320_TO_34X(MMC5);
EXTCL_AFTER_RD_CHR(MMC5);
EXTCL_RD_NMT(MMC5);
EXTCL_RD_CHR(MMC5);
EXTCL_LENGTH_CLOCK(MMC5);
EXTCL_ENVELOPE_CLOCK(MMC5);
EXTCL_APU_TICK(MMC5);
mapper.internal_struct[0] = (BYTE *) &mmc5;
mapper.internal_struct_size[0] = sizeof(mmc5);
if (info.reset >= HARD) {
BYTE i;
memset(&mmc5, 0x00, sizeof(mmc5));
memset(&irql2f, 0x00, sizeof(irql2f));
mmc5.prg_mode = MODE3;
mmc5.chr_mode = MODE0;
mmc5.ext_mode = MODE0;
mmc5.chr_last = CHR_S;
mmc5.S3.frequency = 1;
mmc5.S4.frequency = 1;
irql2f.scanline = 255;
irql2f.frame_x = 339;
for (i = 0; i < 4; ++i) {
mmc5.prg_bank[i] = 0xFF;
}
for (i = 0; i < 8; ++i) {
mmc5.chr_s[i] = i;
}
for (i = 0; i < 4; ++i) {
mmc5.chr_b[i] = i;
}
use_chr_s();
} else {
mmc5.S3.length.enabled = 0;
mmc5.S3.length.value = 0;
mmc5.S4.length.enabled = 0;
mmc5.S4.length.value = 0;
}
info.mapper.extend_wr = TRUE;
irql2f.present = TRUE;
switch (info.mapper.submapper) {
case EKROM:
info.prg.ram.banks_8k_plus = 1;
info.prg.ram.bat.banks = 1;
prg_ram_mode = PRG_RAM_8K;
break;
case ELROM:
default:
info.prg.ram.banks_8k_plus = FALSE;
info.prg.ram.bat.banks = FALSE;
prg_ram_mode = PRG_RAM_NONE;
break;
case ETROM:
info.prg.ram.banks_8k_plus = 2;
info.prg.ram.bat.banks = 1;
info.prg.ram.bat.start = 0;
prg_ram_mode = PRG_RAM_16K;
break;
case EWROM:
info.prg.ram.banks_8k_plus = 4;
info.prg.ram.bat.banks = 4;
prg_ram_mode = PRG_RAM_32K;
break;
}
}
void map_init_Sachen(BYTE model) {
switch (model) {
case SA0036:
EXTCL_CPU_WR_MEM(Sachen_sa0036);
break;
case SA0037:
EXTCL_CPU_WR_MEM(Sachen_sa0037);
if (info.reset >= HARD) {
if (info.prg.rom.max.banks_32k != 0xFFFF) {
map_prg_rom_8k(4, 0, 0);
}
}
break;
case SA8259A:
case SA8259B:
case SA8259C:
case SA8259D: {
EXTCL_CPU_WR_MEM(Sachen_sa8259x);
EXTCL_SAVE_MAPPER(Sachen_sa8259x);
mapper.internal_struct[0] = (BYTE *) &sa8259;
mapper.internal_struct_size[0] = sizeof(sa8259);
info.mapper.extend_wr = TRUE;
if (info.reset >= HARD) {
memset(&sa8259, 0x00, sizeof(sa8259));
if (info.prg.rom.max.banks_32k != 0xFFFF) {
map_prg_rom_8k(4, 0, 0);
}
}
switch (model) {
case SA8259A:
shift = 1;
ored[0] = 1;
ored[1] = 0;
ored[2] = 1;
break;
case SA8259B:
shift = 0;
ored[0] = 0;
ored[1] = 0;
ored[2] = 0;
break;
case SA8259C:
shift = 2;
ored[0] = 1;
ored[1] = 2;
ored[2] = 3;
break;
case SA8259D:
if (!mapper.write_vram) {
const DBWORD bank = info.chr.rom.max.banks_4k << 12;
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x0C00);
}
break;
}
break;
}
case TCA01:
EXTCL_CPU_WR_MEM(Sachen_tca01);
EXTCL_CPU_RD_MEM(Sachen_tca01);
break;
case TCU01:
EXTCL_CPU_WR_MEM(Sachen_tcu01);
info.mapper.extend_wr = TRUE;
if (info.reset >= HARD) {
if (info.prg.rom.max.banks_32k != 0xFFFF) {
map_prg_rom_8k(4, 0, 0);
}
}
break;
case TCU02:
EXTCL_CPU_WR_MEM(Sachen_tcu02);
EXTCL_CPU_RD_MEM(Sachen_tcu02);
EXTCL_SAVE_MAPPER(Sachen_tcu02);
mapper.internal_struct[0] = (BYTE *) &tcu02;
mapper.internal_struct_size[0] = sizeof(tcu02);
info.mapper.extend_wr = TRUE;
if (info.reset >= HARD) {
memset(&tcu02, 0x00, sizeof(tcu02));
}
break;
case SA72007:
EXTCL_CPU_WR_MEM(Sachen_sa72007);
info.mapper.extend_wr = TRUE;
break;
case SA72008:
EXTCL_CPU_WR_MEM(Sachen_sa72008);
info.mapper.extend_wr = TRUE;
break;
case SA74374A:
case SA74374B: {
BYTE i;
for (i = 0; i < LENGTH(pokeriiichr); i++) {
if (!(memcmp(pokeriiichr[i], info.sha1sum.chr.string, 40))) {
if (i == 0) {
/* Poker III 5-in-1 (Sachen) [!].nes */
info.mapper.id = 150;
model = SA74374B;
} else {
/* Poker III [!].nes */
info.mapper.id = 243;
model = SA74374A;
}
}
}
if (model == SA74374A) {
EXTCL_CPU_WR_MEM(Sachen_sa74374a);
} else {
EXTCL_CPU_WR_MEM(Sachen_sa74374b);
}
EXTCL_SAVE_MAPPER(Sachen_sa74374x);
mapper.internal_struct[0] = (BYTE *) &sa74374x;
mapper.internal_struct_size[0] = sizeof(sa74374x);
info.mapper.extend_wr = TRUE;
if (info.reset >= HARD) {
memset(&sa74374x, 0x00, sizeof(sa74374x));
map_prg_rom_8k(4, 0, 0);
}
break;
}
}
type = model;
}
