void downloadSerialNumberFromEEPROM(void)
{
BYTE i;
char *dscrRAM;
BYTE xdata buf[MAX_NAME_LENGTH];
// get pointer to string descriptor 3
dscrRAM = (char *)EZUSB_GetStringDscr(3);
// read string description from EEPROM
EEPROMRead(STRING_ADDRESS, MAX_NAME_LENGTH, buf);
//write string description (serial number) to RAM
for (i=0;i<MAX_NAME_LENGTH;i++)
{
dscrRAM[2+i*2] = buf[i];
}
}
// Device request parser
void SetupCommand(void)
{
void *dscr_ptr;
switch(SETUPDAT[1])
{
case SC_GET_DESCRIPTOR: // *** Get Descriptor
if(TRUE)//DR_GetDescriptor())
switch(SETUPDAT[3])
{
case GD_DEVICE: // Device
SUDPTRH = MSB(pDeviceDscr);
SUDPTRL = LSB(pDeviceDscr);
break;
case GD_DEVICE_QUALIFIER: // Device Qualifier
// only retuen a device qualifier if this is a high speed
// capable chip.
if (HighSpeedCapable())
{
SUDPTRH = MSB(pDeviceQualDscr);
SUDPTRL = LSB(pDeviceQualDscr);
}
else
{
EZUSB_STALL_EP0();
}
break;
case GD_CONFIGURATION: // Configuration
SUDPTRH = MSB(pConfigDscr);
SUDPTRL = LSB(pConfigDscr);
break;
case GD_OTHER_SPEED_CONFIGURATION: // Other Speed Configuration
SUDPTRH = MSB(pOtherConfigDscr);
SUDPTRL = LSB(pOtherConfigDscr);
break;
case GD_STRING: // String
if(dscr_ptr = (void *)EZUSB_GetStringDscr(SETUPDAT[2]))
{
SUDPTRH = MSB(dscr_ptr);
SUDPTRL = LSB(dscr_ptr);
}
else
EZUSB_STALL_EP0(); // Stall End Point 0
break;
default: // Invalid request
EZUSB_STALL_EP0(); // Stall End Point 0
}
break;
case SC_GET_INTERFACE: // *** Get Interface
DR_GetInterface();
break;
case SC_SET_INTERFACE: // *** Set Interface
//DR_SetInterface();
break;
case SC_SET_CONFIGURATION: // *** Set Configuration
DR_SetConfiguration();
break;
case SC_GET_CONFIGURATION: // *** Get Configuration
DR_GetConfiguration();
break;
case SC_GET_STATUS: // *** Get Status
if(TRUE)//DR_GetStatus())
switch(SETUPDAT[0])
{
case GS_DEVICE: // Device
EP0BUF[0] = ((BYTE)Rwuen << 1) | (BYTE)Selfpwr;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
break;
case GS_INTERFACE: // Interface
EP0BUF[0] = 0;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
break;
case GS_ENDPOINT: // End Point
EP0BUF[0] = *(BYTE xdata *) epcs(SETUPDAT[4]) & bmEPSTALL;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
break;
default: // Invalid Command
EZUSB_STALL_EP0(); // Stall End Point 0
}
break;
case SC_CLEAR_FEATURE: // *** Clear Feature
if(TRUE)//DR_ClearFeature())
switch(SETUPDAT[0])
{
case FT_DEVICE: // Device
if(SETUPDAT[2] == 1)
Rwuen = FALSE; // Disable Remote Wakeup
else
EZUSB_STALL_EP0(); // Stall End Point 0
break;
case FT_ENDPOINT: // End Point
if(SETUPDAT[2] == 0)
{
*(BYTE xdata *) epcs(SETUPDAT[4]) &= ~bmEPSTALL;
EZUSB_RESET_DATA_TOGGLE( SETUPDAT[4] );
}
else
EZUSB_STALL_EP0(); // Stall End Point 0
break;
}
break;
case SC_SET_FEATURE: // *** Set Feature
if(TRUE)//DR_SetFeature())
switch(SETUPDAT[0])
{
case FT_DEVICE: // Device
if(SETUPDAT[2] == 1)
Rwuen = TRUE; // Enable Remote Wakeup
else if(SETUPDAT[2] == 2)
// Set Feature Test Mode. The core handles this request. However, it is
// necessary for the firmware to complete the handshake phase of the
// control transfer before the chip will enter test mode. It is also
// necessary for FX2 to be physically disconnected (D+ and D-)
// from the host before it will enter test mode.
break;
else
EZUSB_STALL_EP0(); // Stall End Point 0
break;
case FT_ENDPOINT: // End Point
*(BYTE xdata *) epcs(SETUPDAT[4]) |= bmEPSTALL;
break;
default:
EZUSB_STALL_EP0(); // Stall End Point 0
}
break;
default: // *** Invalid Command
if(DR_VendorCmnd())
EZUSB_STALL_EP0(); // Stall End Point 0
}
// Acknowledge handshake phase of device request
EP0CS |= bmHSNAK;
}
// Device request parser
void SetupCommand(void)
{
void *dscr_ptr;
switch(SETUPDAT[1])
{
case GET_CUR:
case GET_MIN:
case GET_MAX:
SUDPTRCTL = 0x01;
for (i=0;i<26;i++)
EP0BUF[i] = valuesArray[i];
EP0BCH = 0x00;
SYNCDELAY;
EP0BCL = 26;
break;
case SET_LINE_CODING:
EUSB = 0 ;
SUDPTRCTL = 0x01;
EP0BCL = 0x00;
SUDPTRCTL = 0x00;
EUSB = 1;
while (EP0BCL != 7);
SYNCDELAY;
for (i=0;i<7;i++)
LineCode[i] = EP0BUF[i];
break;
case GET_LINE_CODING:
SUDPTRCTL = 0x01;
for (i=0;i<7;i++)
EP0BUF[i] = LineCode[i];
EP0BCH = 0x00;
SYNCDELAY;
EP0BCL = 7;
SYNCDELAY;
while (EP0CS & 0x02);
SUDPTRCTL = 0x00;
break;
case SET_CONTROL_STATE:
break;
case SC_GET_DESCRIPTOR:
// *** Get Descriptor
SUDPTRCTL = 0x01;
if(DR_GetDescriptor())
switch(SETUPDAT[3])
{
case GD_DEVICE: // Device
SUDPTRH = MSB(pDeviceDscr);
SUDPTRL = LSB(pDeviceDscr);
break;
case GD_DEVICE_QUALIFIER: // Device Qualifier
SUDPTRH = MSB(pDeviceQualDscr);
SUDPTRL = LSB(pDeviceQualDscr);
break;
case GD_CONFIGURATION: // Configuration
SUDPTRH = MSB(pConfigDscr);
SUDPTRL = LSB(pConfigDscr);
break;
case GD_OTHER_SPEED_CONFIGURATION: // Other Speed Configuration
// fx2bug - need to support multi other configs
SUDPTRH = MSB(pOtherConfigDscr);
SUDPTRL = LSB(pOtherConfigDscr);
break;
case GD_STRING: // String
if(dscr_ptr = (void *)EZUSB_GetStringDscr(SETUPDAT[2]))
{
SUDPTRH = MSB(dscr_ptr);
SUDPTRL = LSB(dscr_ptr);
}
else
EZUSB_STALL_EP0(); // Stall End Point 0
break;
default: // Invalid request
EZUSB_STALL_EP0(); // Stall End Point 0
}
break;
case SC_GET_INTERFACE: // *** Get Interface
DR_GetInterface();
break;
case SC_SET_INTERFACE: // *** Set Interface
DR_SetInterface();
break;
case SC_SET_CONFIGURATION: // *** Set Configuration
DR_SetConfiguration();
break;
case SC_GET_CONFIGURATION: // *** Get Configuration
DR_GetConfiguration();
break;
case SC_GET_STATUS: // *** Get Status
if(DR_GetStatus())
switch(SETUPDAT[0])
{
case GS_DEVICE: // Device
EP0BUF[0] = ((BYTE)Rwuen << 1) | (BYTE)Selfpwr;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
break;
case GS_INTERFACE: // Interface
EP0BUF[0] = 0;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
break;
case GS_ENDPOINT: // End Point
// fx2bug EP0BUF[0] = EPIO[EPID(SETUPDAT[4])].cntrl & bmEPSTALL;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
break;
default: // Invalid Command
EZUSB_STALL_EP0(); // Stall End Point 0
}
break;
case SC_CLEAR_FEATURE: // *** Clear Feature
if (SETUPDAT[0]== 0x21)
{
EP0BCH = 0;
EP0BCL = 26;
SYNCDELAY;
while(EP0CS & bmEPBUSY);
while (EP0BCL != 26);
valuesArray[2] = EP0BUF[2]; // formate
valuesArray[3] = EP0BUF[3]; // frame
// fps
valuesArray[4] = fps[EP0BUF[2]-1][0];
valuesArray[5] = fps[EP0BUF[2]-1][1];
valuesArray[6] = fps[EP0BUF[2]-1][2];
valuesArray[7] = fps[EP0BUF[2]-1][3];
valuesArray[18] = frameSize[EP0BUF[3]-1][0];
valuesArray[19] = frameSize[EP0BUF[3]-1][1];
valuesArray[20] = frameSize[EP0BUF[3]-1][2];
valuesArray[21] = frameSize[EP0BUF[3]-1][3];
EP0BCH = 0; // ACK
EP0BCL = 0; // ACK
}
else
if(DR_ClearFeature())
switch(SETUPDAT[0])
{
case FT_DEVICE: // Device
if(SETUPDAT[2] == 1)
Rwuen = FALSE; // Disable Remote Wakeup
else
EZUSB_STALL_EP0(); // Stall End Point 0
break;
case FT_ENDPOINT: // End Point
if(SETUPDAT[2] == 0)
{
// fx2bug EZUSB_UNSTALL_EP( EPID(SETUPDAT[4]) );
// fx2bug EZUSB_RESET_DATA_TOGGLE( SETUPDAT[4] );
}
else
EZUSB_STALL_EP0(); // Stall End Point 0
break;
}
break;
case SC_SET_FEATURE: // *** Set Feature
if(DR_SetFeature())
switch(SETUPDAT[0])
{
case FT_DEVICE: // Device
if(SETUPDAT[2] == 1)
Rwuen = TRUE; // Enable Remote Wakeup
else
EZUSB_STALL_EP0(); // Stall End Point 0
break;
case FT_ENDPOINT: // End Point
// fx2bug if(SETUPDAT[2] == 0)
// fx2bug EZUSB_STALL_EP( EPID(SETUPDAT[4]) );
// fx2bug else
EZUSB_STALL_EP0(); // Stall End Point 0
break;
}
break;
default: // *** Invalid Command
if(DR_VendorCmnd())
EZUSB_STALL_EP0(); // Stall End Point 0
}
// Acknowledge handshake phase of device request
// Required for rev C does not effect rev B
// TGE fx2bug EP0CS |= bmBIT1;
EP0CS |= bmHSNAK;
}
BOOL DR_VendorCmnd(void)
{
WORD value;
WORD len,ind, bc; // xdata used here to conserve data ram; if not EEPROM writes don't work anymore
/*
union {
unsigned short ushort;
unsigned msb,lsb;
unsigned bytes[2]; // big endian, bytes[0] is MSB as far as C51 is concerned
} length;
*/
WORD i;
char *dscrRAM;
unsigned char xdata JTAGdata[400];
switch (SETUPDAT[1]){
case VR_ENABLE_AE_IN: // enable IN transfers
{
startMonitor();
break; // handshake phase triggered below
}
case VR_DISABLE_AE_IN: // disable IN transfers
{
stopMonitor();
break;
}
case VR_RESET_FIFOS: // reset in and out fifo
{
SYNCDELAY;
EP6FIFOCFG = 0x00; //0000_0000 disable auto-in
SYNCDELAY;
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x06;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP6FIFOCFG = 0x08 ; //0000_1000 reenable auto-in
break;
}
case VR_DOWNLOAD_CPLD_CODE:
{
if (SETUPDAT[0]==VR_DOWNLOAD) {
if (JTAGinit)
{
IOC=0x00;
OEC = 0xBD; // configure TDO (bit 6) and TSmaster as input : 1011_1101
xsvfInitialize();
JTAGinit=FALSE;
}
len = SETUPDAT[6];
len |= SETUPDAT[7] << 8;
if (len>400)
{
xsvfReturn=10;
OEC = 0x0D; // configure JTAG pins to float : 0000_1111
JTAGinit=TRUE;
break;
}
value=0;
resetReadCounter(JTAGdata);
while(len) // Move new data through EP0OUT
{ // one packet at a time.
// Arm endpoint - do it here to clear (after sud avail)
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
while(EP0CS & bmEPBUSY);
bc = EP0BCL; // Get the new bytecount
for(i=0; i<bc; i++)
JTAGdata[value+i] = EP0BUF[i];
value += bc;
len -= bc;
}
if (SETUPDAT[2]==0x00) //complete
{
OEC = 0x0D; // configure JTAG pins to float : 0000_1111
JTAGinit=TRUE;
} else
{
xsvfReturn=xsvfRun();
if (xsvfReturn>0) // returns true if error
{
OEC = 0x0D; // configure JTAG pins to float : 0000_1101
JTAGinit=TRUE;
// return TRUE;
}
}
/* EP0BUF[0] = SETUPDAT[1];
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
return(FALSE); */
break;
}
else //case VR_XSVF_ERROR_CODE:
{
EP0BUF[0] = SETUPDAT[1];
EP0BUF[1]= xsvfReturn;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
return(FALSE);
}
}
case VR_SET_DEVICE_NAME:
{
*EP0BUF = SETUPDAT[1];
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
while(EP0CS & bmEPBUSY); //wait for the data packet to arrive
dscrRAM = (char*)EZUSB_GetStringDscr(3); // get address of serial number descriptor-string in RAM
if (EP0BCL > MAX_NAME_LENGTH)
{
len=MAX_NAME_LENGTH;
} else
{
len=EP0BCL;
}
for (i=0;i<len;i++)
{
EEPROMWriteBYTE(STRING_ADDRESS+i, EP0BUF[i]); // write string to EEPROM
dscrRAM[2+i*2] = EP0BUF[i]; // write string to RAM
}
for (i=len; i<MAX_NAME_LENGTH; i++) // fill the rest with stop characters
{
EEPROMWriteBYTE(STRING_ADDRESS+i, ' '); // write string to EEPROM
dscrRAM[2+i*2] = ' '; // write string to RAM
}
EP0BCH = 0;
EP0BCL = 0;
return(FALSE);
}
case VR_RESETTIMESTAMPS:
{
tsReset=1; // RESET_TS=1; // assert RESET_TS pin for one instruction cycle (four clock cycles)
tsReset=0; // RESET_TS=0;
break;
}
case VR_CONFIG: // write bytes to SPI interface
case VR_EEPROM_BIASGEN_BYTES: // falls through and actual command is tested below
{
// the value bytes are the specific config command
// the index bytes are the arguments
// more data comes in the setupdat
SYNCDELAY;
value = SETUPDAT[2]; // Get request value
value |= SETUPDAT[3] << 8; // data comes little endian
ind = SETUPDAT[4]; // Get index
ind |= SETUPDAT[5] << 8;
len = SETUPDAT[6]; // length for data phase
len |= SETUPDAT[7] << 8;
switch(value&0xFF){ // take LSB for specific setup command because equalizer uses MSB for channel
// final short CMD_IPOT = 1, CMD_RESET_EQUALIZER = 2, CMD_SCANNER = 3, CMD_EQUALIZER = 4, CMD_SETBIT = 5, CMD_VDAC = 6;
#define CMD_IPOT 1
#define CMD_RESET_EQUALIZER 2
#define CMD_SCANNER 3
#define CMD_EQUALIZER 4
#define CMD_SETBIT 5
#define CMD_VDAC 6
#define CMD_INITDAC 7
case CMD_IPOT:
selectIPots;
numBiasBytes=len;
while(len){ // Move new data through EP0OUT, one packet at a time,
// eventually will get len down to zero by bc=64,64,15 (for example)
// Arm endpoint - do it here to clear (after sud avail)
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
SYNCDELAY;
while(EP0CS & bmEPBUSY); // spin here until data arrives
bc = EP0BCL; // Get the new bytecount
for(i=0; i<bc; i++){
sendConfigByte(EP0BUF[i]);
}
// value += bc; // inc eeprom value to write to, in case that's what we're doing
len -= bc; // dec total byte count
}
toggleLatch();
selectNone;
LED=!LED;
break;
case CMD_VDAC:
// EP0BUF has b0=channel (same for each DAC), b1=DAC1 MSB, b2=DAC1 LSB, b3=DAC0 MSB, b4=DAC0 LSB
if(len!=6) return TRUE; // error, should have 6 bytes which are just written out to DACs surrounded by dacNSync=0
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
SYNCDELAY;
while(EP0CS & bmEPBUSY); // spin here until data arrives
startDACSync();
for(i=0;i<6;i++){
sendDACByte(EP0BUF[i]);
}
endDACSync();
//toggleLDAC();
LED=!LED;
break;
case CMD_INITDAC:
initDAC();
LED=!LED;
break;
case CMD_SETBIT:
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
SYNCDELAY;
while(EP0CS & bmEPBUSY); // spin here until data arrives
// sends value=CMD_SETBIT, index=portbit with (port(b=0,d=1,e=2)<<8)|bitmask(e.g. 00001000) in MSB/LSB, byte[0]=value (1,0)
// also if button is tristable type in GUI, then byte[0] has tristate in bit1
{
bit bitval=(EP0BUF[0]&1); // 1=set, 0=clear
bit tristate=(EP0BUF[0]&2?1:0); // 1=tristate, 0=drive
unsigned char bitmask=SETUPDAT[4]; // bitmaskit mask, LSB of ind
switch(SETUPDAT[5]){ // this is port, MSB of ind
case 0: // port c
if(bitval) IOC|=bitmask; else IOC&= ~bitmask;
if(tristate) OEC&= ~bitmask; else OEC|=bitmask;
break;
case 1: // port d
if(bitval) IOD|=bitmask; else IOD&= ~bitmask;
if(tristate) OED&= ~bitmask; else OED|=bitmask;
break;
case 2: // port e
if(bitval) IOE|=bitmask; else IOE&= ~bitmask;
if(tristate) OEE&= ~bitmask; else OEE|=bitmask;
break;
default:
return TRUE; // error
}
LED=!LED;
}
break;
case CMD_SCANNER:
// index=1, continuous, index=0 go to channel
// Arm endpoint - do it here to clear (after sud avail) and get the data for channel to scan to if there is one. in any case must read data
// or subsequent requests will fail.
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
SYNCDELAY;
while(EP0CS & bmEPBUSY); // spin here until data arrives
if(ind==0){ // go to channel
ET2=0; // disable timer2 interrupt - IE.5
TR2=0; // stop timer2
i=255; // timeout on scanner clear
while(IOE&ScanSync && i-->0){ // clock scanner to end and timeout if there is no chip there
scanClock=1; // sync happens on falling edge
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
scanClock=0;
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
}
if(i==0) return TRUE; // scan to start failed
bc = EP0BUF[0]; // Get the channel number to scan to
for(i=0; i<bc; i++){
scanClock=1; _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
scanClock=0; _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
}
}else{ // continuous scanning
RCAP2L=0xff-EP0BUF[0]; // load timer 2 low byte reload register with 0xff-period. period=0 reload is 0xff00 (255 counts), period=255, reload is 0x0000, period=64k
ET2=1; // enable timer2 interrupt - this is IE.5 bit addressable
TR2=1; // run timer2
}
LED=!LED;
break;
case CMD_EQUALIZER:
/*
the scheme right now for loading the AERKillBit and the local Vq's go as follows,
start with AddSel, which has 7 bits, RX0 to RX6, toggle bitlatch low/high - this signal
latches the bits for the decoder.
The output of the decoder is not activated till DataSel is chosen, the 10 bits are loaded, 5 bits
for Vq of SOS and 5bits for Iq of bpf, then when bitlatch is toggled low/high, then the
output of the decoder is released.
During this toggle of latch, the selected channel will also latch in the value on AERKillBit.
The only thing that I'm worrying about right now is that this value has to be remembered somewhere,
i.e. if I choose channels 10, 15 neurons to be inactivated, then even if I choose
new values for Vq and Iq, this information has to be stored somewhere. The
AERKillBit in essence is like an additional bit to the bits for the DataSel.
*/
// value has cmd in LSB, channel in MSB
// index has b11=bpfkilled, b10=lpfkilled, b9-5=qbpf, b4-0=qsos
/*All other 16-bit and 32-bit values are stored, contrary to other Intel
processors, in big endian format, with the high-order byte stored first. For
example, the LJMP and LCALL instructions expect 16-bit addresses that are
in big endian format.
*/
// index is channel address, bytes={gain,quality,killed (1=killed,0=active)}
selectAddr;
sendConfigBits(SETUPDAT[3],7); // send 7 bit address
toggleLatch();
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
selectNone;
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
selectData;
sendConfigBits(SETUPDAT[4]&0x1f,5); // what is this for?
sendConfigBits((SETUPDAT[4]>>5)|(SETUPDAT[5]<<3),5);
/* commented out because of bug in cochleaams1b where select of a single kill bit is inverted so everybody but the one you want
is selected. however, the equalizer DAC current splitters still work
// set each killbit
selectLPFKill; // clears ybit
if(SETUPDAT[5]&4){ // kill LPF
aerKillBit=0; // hack
}else{
aerKillBit=0;
}
toggleLatch();
selectBPFKill; // sets ybit
if(SETUPDAT[5]&8){ // kill BPF
aerKillBit=0; // hack
}else{
aerKillBit=0;
}
*/
toggleLatch();
selectNone;
LED=!LED;
break;
case CMD_RESET_EQUALIZER:
return TRUE; // not yet implmented
LED=!LED;
break;
default:
return(TRUE); // don't recognize command
}
EP0BCH = 0;
EP0BCL = 0; // Arm endpoint with 0 byte to transfer
return(FALSE); // very important, otherwise get stall
}
case VR_SET_POWERDOWN: // control powerDown output bit
{
if (SETUPDAT[2])
{
powerDown=1;
} else
{
powerDown=0;
}
*EP0BUF=VR_SET_POWERDOWN;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with 1 byte to transfer
SYNCDELAY;
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break; // very important, otherwise get stall
}
/*
case VR_SETARRAYRESET: // set array reset, based on lsb of argument
{
if (SETUPDAT[2]&0x01)
{
IOE=IOE|ARRAY_RESET_MASK; //IOE|=arrayReset;
} else
{
IOE=IOE&NOT_ARRAY_RESET_MASK;
}
*EP0BUF=VR_SETARRAYRESET;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with 1 byte to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
return(FALSE); // very important, otherwise get stall
}
case VR_DOARRAYRESET: // reset array for fixed reset time
{
IOE=IOE&NOT_ARRAY_RESET_MASK;
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_(); // a few us
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
IOE=IOE|ARRAY_RESET_MASK; //IOE|=arrayReset;
*EP0BUF=VR_DOARRAYRESET;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with 1 byte to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
return (FALSE); // very important, otherwise get stall
}
*/
/* case VR_TIMESTAMP_TICK:
{
if (SETUPDAT[0]==VR_UPLOAD) //1010_0000 :vendor request to device, direction IN
{
EP0BUF[0] = SETUPDAT[1];
EP0BUF[1]= operationMode;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
} else
{
operationMode=SETUPDAT[2];
if (operationMode==0)
{
TIMESTAMP_MODE = 0;
CFG_TIMESTAMP_COUNTER = 0;
}else if (operationMode==1)
{
CFG_TIMESTAMP_COUNTER = 1;
TIMESTAMP_MODE = 0;
}else if (operationMode==2)
{
CFG_TIMESTAMP_COUNTER = 0;
TIMESTAMP_MODE = 1;
}else if (operationMode==3)
{
CFG_TIMESTAMP_COUNTER = 1;
TIMESTAMP_MODE = 1;
}
*EP0BUF = SETUPDAT[1];
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
}
return(FALSE);
}*/
case VR_IS_TS_MASTER:
{
EP0BUF[0] = SETUPDAT[1];
EP0BUF[1]= TIMESTAMP_MASTER;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
return(FALSE);
}
/* case VR_MISSED_EVENTS:
{
EX1=0;
EP0BUF[0] = SETUPDAT[1];
EP0BUF[4]= (missedEvents & 0xFF000000) >> 24;
EP0BUF[3]= (missedEvents & 0x00FF0000) >> 16;
EP0BUF[2]= (missedEvents & 0x0000FF00) >> 8;
EP0BUF[1]= missedEvents & 0x000000FF;
EP0BCH = 0;
EP0BCL = 5;
EP0CS |= bmHSNAK;
missedEvents=0;
EX1=1;
return(FALSE);
}*/
case VR_RAM:
case VR_EEPROM:
{
value = SETUPDAT[2]; // Get address and length
value |= SETUPDAT[3] << 8;
len = SETUPDAT[6];
len |= SETUPDAT[7] << 8;
// Is this an upload command ?
if(SETUPDAT[0] == VR_UPLOAD) // this is automatically defined on host from direction of vendor request
{
while(len) // Move requested data through EP0IN
{ // one packet at a time.
while(EP0CS & bmEPBUSY);
if(len < EP0BUFF_SIZE)
bc = len;
else
bc = EP0BUFF_SIZE;
// Is this a RAM upload ?
if(SETUPDAT[1] == VR_RAM)
{
for(i=0; i<bc; i++)
*(EP0BUF+i) = *((BYTE xdata *)value+i);
}
else
{
for(i=0; i<bc; i++)
*(EP0BUF+i) = 0xcd;
EEPROMRead(value,(WORD)bc,(WORD)EP0BUF);
}
EP0BCH = 0;
EP0BCL = (BYTE)bc; // Arm endpoint with # bytes to transfer
value += bc;
len -= bc;
}
}
// Is this a download command ?
else if(SETUPDAT[0] == VR_DOWNLOAD) // this is automatically defined on host from direction of vendor request
{
while(len) // Move new data through EP0OUT
{ // one packet at a time.
// Arm endpoint - do it here to clear (after sud avail)
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
while(EP0CS & bmEPBUSY);
bc = EP0BCL; // Get the new bytecount
// Is this a RAM download ?
if(SETUPDAT[1] == VR_RAM)
{
for(i=0; i<bc; i++)
*((BYTE xdata *)value+i) = *(EP0BUF+i);
}
else
EEPROMWrite(value,bc,(WORD)EP0BUF);
value += bc;
len -= bc;
}
}
return(FALSE);
}
default:
{ // we received an invalid command
return(TRUE);
}
}
*EP0BUF = SETUPDAT[1];
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
return(FALSE);
}
