// Called from OEMPowerOff - no system calls, critical sections, OALMSG, etc., are allowed
//------------------------------------------------------------------------------
// WARNING: This function is called from OEMPowerOff - no system calls, critical
// sections, OALMSG, etc., may be used by this function or any function that it calls.
//------------------------------------------------------------------------------
void OALWatchdogEnable(BOOL bEnable)
{
if (g_WatchdogDevice != OMAP_DEVICE_NONE)
{
if (bEnable == TRUE)
{
// Enable clock
EnableDeviceClocks(g_WatchdogDevice, TRUE);
// Refresh the watchdog timer
while( INREG32(&g_pWatchogTimerRegs->WWPS) );
OUTREG32(&g_pWatchogTimerRegs->WTGR, INREG32(&g_pWatchogTimerRegs->WTGR) + 1);
// Start Watchdog
OUTREG32(&g_pWatchogTimerRegs->WSPR, WDOG_ENABLE_SEQ1);
while( INREG32(&g_pWatchogTimerRegs->WWPS) );
OUTREG32(&g_pWatchogTimerRegs->WSPR, WDOG_ENABLE_SEQ2);
}
else
{
// Ensure the timer is stopped
OUTREG32(&g_pWatchogTimerRegs->WSPR, WDOG_DISABLE_SEQ1);
while( INREG32(&g_pWatchogTimerRegs->WWPS) );
OUTREG32(&g_pWatchogTimerRegs->WSPR, WDOG_DISABLE_SEQ2);
while( INREG32(&g_pWatchogTimerRegs->WWPS) );
// Disable clock
EnableDeviceClocks(g_WatchdogDevice, FALSE);
}
}
}
void main()
{
UINT32 CpuRevision;
// Get CPU family
g_CPUFamily = CPU_FAMILY_OMAP35XX;
CpuRevision = Get_CPUVersion();
g_CPUFamily = CPU_FAMILY(CpuRevision);
EnableDeviceClocks(BSPGetDebugUARTConfig()->dev,TRUE);
BootloaderMain();
}
//------------------------------------------------------------------------------
//
// Function: DMA_Deinit
//
// Called by device manager to uninitialize device.
//
BOOL
DMA_Deinit(
DWORD context
)
{
BOOL rc = FALSE;
Device_t *pDevice = (Device_t*)context;
DEBUGMSG(ZONE_FUNCTION, (L"+DMA_Deinit(0x%08x)\r\n", context));
// Check if we get correct context
if ((pDevice == NULL) || (pDevice->cookie != DMA_DEVICE_COOKIE))
{
DEBUGMSG (ZONE_ERROR, (L"ERROR: DMA_Deinit: "
L"Incorrect context paramer\r\n"
));
goto cleanUp;
}
// Check for open instances
if (pDevice->instances > 0)
{
DEBUGMSG (ZONE_ERROR, (L"ERROR: DMA_Deinit: "
L"Deinit with active instance (%d instances active)\r\n",
pDevice->instances
));
goto cleanUp;
}
if (pDevice->pSystemController != NULL)
{
pDevice->pSystemController->Uninitialize();
delete pDevice->pSystemController;
}
// Set hardware to D4
EnableDeviceClocks(pDevice->SdmaDevice, FALSE);
// Delete critical section
DeleteCriticalSection(&pDevice->cs);
// Free device structure
LocalFree(pDevice);
// Done
rc = TRUE;
cleanUp:
DEBUGMSG(ZONE_FUNCTION, (L"-DMA_Deinit(rc = %d)\r\n", rc));
return rc;
}
static void WatchdogRefresh(void)
{
static BOOL fWatchdogInit = FALSE;
if (fWatchdogInit == FALSE)
{
// Initialize watchdog hardware
g_WatchdogDevice = BPSGetWatchdogDevice();
g_pWatchogTimerRegs = OALPAtoUA(GetAddressByDevice(g_WatchdogDevice));
// Make sure interface/functional clocks are running
EnableDeviceClocks(g_WatchdogDevice, TRUE);
#if 0
SetDeviceIdleMode(g_WatchdogDevice,OMAP_SMART_IDLE_FLAG);
#endif
// Ensure the timer is stopped
// Note - writes are posted; must ensure they have completed before
// writing to the same register again.
OUTREG32(&g_pWatchogTimerRegs->WSPR, WDOG_DISABLE_SEQ1);
while( INREG32(&g_pWatchogTimerRegs->WWPS) );
OUTREG32(&g_pWatchogTimerRegs->WSPR, WDOG_DISABLE_SEQ2);
while( INREG32(&g_pWatchogTimerRegs->WWPS) );
// Set prescaler, so that the watcdog counter is incremented around every 1 ms (32768 Hz / 32 => 1024 Hz)
OUTREG32(&g_pWatchogTimerRegs->WCLR, WDOG_WCLR_PRESCALE(5) | WDOG_WCLR_PRES_ENABLE);
// Set reload value in both the reload register and base counter register
OUTREG32(&g_pWatchogTimerRegs->WLDR, (DWORD) (0-g_dwWatchdogPeriod));
OUTREG32(&g_pWatchogTimerRegs->WCRR, (DWORD) (0-g_dwWatchdogPeriod));
while( INREG32(&g_pWatchogTimerRegs->WWPS) );
// Refresh the watchdog timer before starting it
while( INREG32(&g_pWatchogTimerRegs->WWPS) );
OUTREG32(&g_pWatchogTimerRegs->WTGR, INREG32(&g_pWatchogTimerRegs->WTGR) + 1);
// Start the watchdog timer
OUTREG32(&g_pWatchogTimerRegs->WSPR, WDOG_ENABLE_SEQ1);
while( INREG32(&g_pWatchogTimerRegs->WWPS) );
OUTREG32(&g_pWatchogTimerRegs->WSPR, WDOG_ENABLE_SEQ2);
fWatchdogInit = TRUE;
}
// Refresh the watchdog timer
while( INREG32(&g_pWatchogTimerRegs->WWPS) );
OUTREG32(&g_pWatchogTimerRegs->WTGR, INREG32(&g_pWatchogTimerRegs->WTGR) + 1);
}
//------------------------------------------------------------------------------
//
// Function: OEMPlatformDeinit
//
static
VOID
OEMPlatformDeinit(
)
{
OMAP_GPTIMER_REGS *pTimerRegs = OALPAtoUA(OMAP_GPTIMER1_REGS_PA);
// Soft reset GPTIMER
OUTREG32(&pTimerRegs->TIOCP, SYSCONFIG_SOFTRESET);
// While until done
while ((INREG32(&pTimerRegs->TISTAT) & GPTIMER_TISTAT_RESETDONE) == 0);
// Disable device clocks that were used by the bootloader
EnableDeviceClocks(OMAP_DEVICE_GPIO1,FALSE);
EnableDeviceClocks(OMAP_DEVICE_GPIO2,FALSE);
EnableDeviceClocks(OMAP_DEVICE_GPIO3,FALSE);
EnableDeviceClocks(OMAP_DEVICE_GPIO4,FALSE);
EnableDeviceClocks(OMAP_DEVICE_GPIO5,FALSE);
EnableDeviceClocks(OMAP_DEVICE_GPIO6,FALSE);
EnableDeviceClocks(OMAP_DEVICE_GPTIMER2,FALSE);
EnableDeviceClocks(OMAP_DEVICE_UART1,FALSE);
EnableDeviceClocks(OMAP_DEVICE_UART2,FALSE);
EnableDeviceClocks(OMAP_DEVICE_UART3,FALSE);
EnableDeviceClocks(OMAP_DEVICE_MMC1,FALSE);
EnableDeviceClocks(OMAP_DEVICE_MMC2,FALSE);
EnableDeviceClocks(OMAP_DEVICE_I2C1,FALSE);
EnableDeviceClocks(OMAP_DEVICE_I2C2,FALSE);
EnableDeviceClocks(OMAP_DEVICE_I2C3,FALSE);
}
//------------------------------------------------------------------------------
//
// Function: OEMPlatformInit
//
// This function provide platform initialization functions. It is called
// from boot loader after OEMDebugInit is called. Note that boot loader
// BootloaderMain is called from s/init.s code which is run after reset.
//
BOOL
OEMPlatformInit(
)
{
OMAP_GPTIMER_REGS *pTimerRegs;
UINT32 CpuRevision, version;
HANDLE hTwl,hGPIO;
static UCHAR allocationPool[512];
static const PAD_INFO ebootPinMux[] = {
DSS_PADS
GPIO_PADS
USBOTG_PADS
END_OF_PAD_ARRAY
};
static const PAD_INFO ebootPinMux_37XX[] = {
DSS_PADS_37XX
GPIO_PADS_37XX
USBOTG_PADS
END_OF_PAD_ARRAY
};
OALLocalAllocInit(allocationPool,sizeof(allocationPool));
// Get processor and companion chip versions
g_CPUFamily = CPU_FAMILY_OMAP35XX;
CpuRevision = Get_CPUVersion();
version = CPU_REVISION(CpuRevision);
g_CPUFamily = CPU_FAMILY(CpuRevision);
// Set GPTIMER1 regs pointer
pTimerRegs = OALPAtoUA(OMAP_GPTIMER1_REGS_PA);
if(g_CPUFamily == CPU_FAMILY_DM37XX)
{
ConfigurePadArray(ebootPinMux_37XX);
}
else
{
ConfigurePadArray(ebootPinMux);
}
//OALLogSetZones(
// (1<<OAL_LOG_VERBOSE) |
// (1<<OAL_LOG_INFO) |
// (1<<OAL_LOG_ERROR) |
// (1<<OAL_LOG_WARN) |
// (1<<OAL_LOG_FUNC) |
// (1<<OAL_LOG_IO) |
// 0);
OALLog(
L"\r\nTexas Instruments Windows CE EBOOT for OMAP35xx/37xx, "
L"Built %S at %S\r\n", __DATE__, __TIME__
);
OALLog(
L"EBOOT Version %d.%d, BSP " BSP_VERSION_STRING L"\r\n",
EBOOT_VERSION_MAJOR, EBOOT_VERSION_MINOR
);
// Soft reset GPTIMER1
OUTREG32(&pTimerRegs->TIOCP, SYSCONFIG_SOFTRESET);
// While until done
while ((INREG32(&pTimerRegs->TISTAT) & GPTIMER_TISTAT_RESETDONE) == 0);
// Enable posted mode
OUTREG32(&pTimerRegs->TSICR, GPTIMER_TSICR_POSTED);
// Start timer
OUTREG32(&pTimerRegs->TCLR, GPTIMER_TCLR_AR|GPTIMER_TCLR_ST);
// Enable device clocks used by the bootloader
EnableDeviceClocks(OMAP_DEVICE_GPIO1,TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO2,TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO3,TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO4,TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO5,TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO6,TRUE);
// configure i2c devices
OALI2CInit(OMAP_DEVICE_I2C1);
OALI2CInit(OMAP_DEVICE_I2C2);
OALI2CInit(OMAP_DEVICE_I2C3);
GPIOInit();
// Note that T2 accesses must occur after I2C initialization
hTwl = TWLOpen();
hGPIO = GPIOOpen();
// Clear Reset on ethernet controller
GPIOSetBit(hGPIO,LAN9115_RESET_GPIO);
GPIOSetMode(hGPIO, LAN9115_RESET_GPIO,GPIO_DIR_OUTPUT);
//rst usb hub
GPIOClrBit(hGPIO,13);
GPIOSetMode(hGPIO, 13,GPIO_DIR_OUTPUT);
OALStall(10000);
GPIOSetBit(hGPIO,13);
OALStall(1000);
GPIOClrBit(hGPIO,13);
OALLog(L"\r\nTI OMAP%x Version 0x%08x (%s)\r\n", CPU_ID(CpuRevision), CPU_REVISION(CpuRevision),
version == CPU_FAMILY_35XX_REVISION_ES_1_0 ? L"ES1.0" :
version == CPU_FAMILY_35XX_REVISION_ES_2_0 ? L"ES2.0" :
version == CPU_FAMILY_35XX_REVISION_ES_2_1 ? L"ES2.1" :
version == CPU_FAMILY_35XX_REVISION_ES_2_0_CRC ? L"ES2.0, ID determined using CRC" :
version == CPU_FAMILY_35XX_REVISION_ES_2_1_CRC ? L"ES2.1, ID determined using CRC" :
version == CPU_FAMILY_35XX_REVISION_ES_3_0 ? L"ES3.0" :
version == CPU_FAMILY_35XX_REVISION_ES_3_1 ? L"ES3.1" :
version == CPU_FAMILY_37XX_REVISION_ES_1_0? L"ES1.0" :
version == CPU_FAMILY_37XX_REVISION_ES_1_1? L"ES1.1" :
version == CPU_FAMILY_37XX_REVISION_ES_1_2? L"ES1.2" :
L"Unknown" );
/* Initialize Device Prefix */
if(g_CPUFamily == CPU_FAMILY_DM37XX)
{
gDevice_prefix = BSP_DEVICE_37xx_PREFIX;
}
else if (g_CPUFamily == CPU_FAMILY_OMAP35XX)
{
gDevice_prefix = BSP_DEVICE_35xx_PREFIX;
}
else
{
OALLog(L"INFO: UnKnown CPU family:%d....\r\n", g_CPUFamily);
gDevice_prefix = BSP_DEVICE_35xx_PREFIX;
}
version = TWLReadIDCode(hTwl);
OALLog(L"TPS659XX Version 0x%02x (%s)\r\n", version,
version == 0x00 ? L"ES1.0" :
version == 0x10 ? L"ES1.1" :
version == 0x20 ? L"ES1.2" :
version == 0x30 ? L"ES1.3" : L"Unknown" );
g_ecctype = (UCHAR)dwEbootECCtype;
// Done
return TRUE;
}
//------------------------------------------------------------------------------
//
// Function: OALTimerInit
//
// General purpose timer 1 is used for system tick. It supports
// count/compare mode on 32kHz clock
//
BOOL
OALTimerInit(
UINT32 sysTickMSec,
UINT32 countsPerMSec,
UINT32 countsMargin
)
{
BOOL rc = FALSE;
UINT srcClock;
UINT32 sysIntr;
UNREFERENCED_PARAMETER(sysTickMSec);
UNREFERENCED_PARAMETER(countsPerMSec);
UNREFERENCED_PARAMETER(countsMargin);
OALMSG(1&&OAL_FUNC, (L"+OALTimerInit(%d, %d, %d)\r\n", sysTickMSec, countsPerMSec, countsMargin ));
// Initialize timer state information
g_oalTimerContext.maxPeriodMSec = dwOEMMaxIdlePeriod; // Maximum period the timer will interrupt on, in mSec
g_oalTimerContext.margin = DELTA_TIME; // Time needed to reprogram the timer interrupt
g_oalTimerContext.curCounts = 0;
g_oalTimerContext.base = 0;
g_oalTimerContext.match = 0xFFFFFFFF;
g_oalTimerContext.Posted = 0;
// Set idle conversion constant and counters
idleconv = MSEC_TO_TICK(1);
curridlehigh = 0;
curridlelow = 0;
// Use variable system tick
pOEMUpdateRescheduleTime = OALTimerUpdateRescheduleTime;
// Get virtual addresses for hardware
g_TimerDevice = BSPGetSysTimerDevice(); // OMAP_DEVICE_GPTIMER1
g_pTimerRegs = OALPAtoUA(GetAddressByDevice(g_TimerDevice));
OALMSG(1 && OAL_FUNC, (L" TimerPA: 0x%x\r\n", GetAddressByDevice(g_TimerDevice)));
OALMSG(1 && OAL_FUNC, (L" TimerUA: 0x%x\r\n", g_pTimerRegs));
// Select 32K frequency source clock
srcClock = BSPGetSysTimer32KClock(); // k32K_FCLK
//PrcmDeviceSetSourceClocks(g_TimerDevice,1,&srcClock);
// enable gptimer
EnableDeviceClocks(g_TimerDevice, TRUE);
// stop timer
OALTimerSetReg(&g_pTimerRegs->TCLR, 0);
// Soft reset GPTIMER
OALTimerSetReg(&g_pTimerRegs->TIOCP, SYSCONFIG_SOFTRESET);
// While until done
while ((OALTimerGetReg(&g_pTimerRegs->TISTAT) & GPTIMER_TISTAT_RESETDONE) == 0);
// Set smart idle
OALTimerSetReg(
&g_pTimerRegs->TIOCP,
SYSCONFIG_SMARTIDLE|SYSCONFIG_ENAWAKEUP|
SYSCONFIG_AUTOIDLE
);
// Enable posted mode
OALTimerSetReg(&g_pTimerRegs->TSICR, GPTIMER_TSICR_POSTED);
g_oalTimerContext.Posted = 1;
// Set match register to avoid unwanted interrupt
OALTimerSetReg(&g_pTimerRegs->TMAR, 0xFFFFFFFF);
// Enable match interrupt
OALTimerSetReg(&g_pTimerRegs->TIER, GPTIMER_TIER_MATCH);
// Enable match wakeup
OALTimerSetReg(&g_pTimerRegs->TWER, GPTIMER_TWER_MATCH);
// Enable timer in auto-reload and compare mode
OALTimerSetReg(&g_pTimerRegs->TCLR, GPTIMER_TCLR_CE|GPTIMER_TCLR_AR|GPTIMER_TCLR_ST);
// Wait until write is done
//while ((INREG32(&g_pTimerRegs->TWPS) & GPTIMER_TWPS_TCLR) != 0);
// Set global variable to tell interrupt module about timer used
g_oalTimerIrq = GetIrqByDevice(g_TimerDevice,NULL); // 37
// Request SYSINTR for timer IRQ, it is done to reserve it...
sysIntr = OALIntrRequestSysIntr(1, &g_oalTimerIrq, OAL_INTR_FORCE_STATIC); // 17
// Enable System Tick interrupt
if (!OEMInterruptEnable(sysIntr, NULL, 0))
{
OALMSG(OAL_ERROR, (
L"ERROR: OALTimerInit: Interrupt enable for system timer failed"
));
goto cleanUp;
}
// Initialize timer to maximum period
UpdatePeriod(g_oalTimerContext.maxPeriodMSec);
// Done
rc = TRUE;
cleanUp:
OALMSG(1 && OAL_FUNC, (L"-OALTimerInit(rc = %d)\r\n", rc));
return rc;
}
//------------------------------------------------------------------------------
//
// Function: DMA_Init
//
// Called by device manager to initialize device.
//
DWORD
DMA_Init(
LPCWSTR szContext,
LPCVOID pBusContext
)
{
DWORD rc = (DWORD)NULL;
UNREFERENCED_PARAMETER(pBusContext);
UNREFERENCED_PARAMETER(szContext);
DEBUGMSG(ZONE_FUNCTION, (
L"+DMA_Init(%s, 0x%08x)\r\n", szContext, pBusContext
));
// Create device structure
Device_t *pDevice = (Device_t *)LocalAlloc(LPTR, sizeof(Device_t));
if (pDevice == NULL)
{
DEBUGMSG(ZONE_ERROR, (L"ERROR: DMA_Init: "
L"Failed allocate DMA controller structure\r\n"
));
goto cleanUp;
}
// initialize memory
memset(pDevice, 0, sizeof(Device_t));
// Set cookie
pDevice->cookie = DMA_DEVICE_COOKIE;
// Initalize critical section
InitializeCriticalSection(&pDevice->cs);
// Read device parameters
if (GetDeviceRegistryParams(
szContext, pDevice, dimof(s_deviceRegParams), s_deviceRegParams
) != ERROR_SUCCESS)
{
DEBUGMSG(ZONE_ERROR, (L"ERROR: DMA_Init: "
L"Failed read DMA driver registry parameters\r\n"
));
goto cleanUp;
}
// Retrieve device ID
pDevice->SdmaDevice = SOCGetDMADevice(pDevice->SdmaIndex);
// Set hardware to full power
EnableDeviceClocks(pDevice->SdmaDevice, TRUE);
// DMA will be in smart idle mode so we don't need to
// ever set the power state of the DMA to D4
// initialize general dma controller
if (InitializeDevice(pDevice) == FALSE)
{
DEBUGMSG (ZONE_ERROR, (L"ERROR: DMA_Init: "
L"Failed to initialize device\r\n"
));
goto cleanUp;
}
rc = (DWORD)pDevice;
cleanUp:
if (rc == 0) DMA_Deinit((DWORD)pDevice);
DEBUGMSG(ZONE_FUNCTION, (L"-DMA_Init(rc = %d)\r\n", rc));
return rc;
}
//------------------------------------------------------------------------------
//
// Function: OEMPlatformInit
//
// This function provide platform initialization functions. It is called
// from boot loader after OEMDebugInit is called. Note that boot loader
// BootloaderMain is called from s/init.s code which is run after reset.
//
BOOL OEMPlatformInit()
{
OMAP_GPTIMER_REGS *pTimerRegs;
UINT32 CpuRevision, version;
HANDLE hTwl,hGPIO;
static UCHAR allocationPool[512];
/*static const PAD_INFO ebootPinMux[] = {
DSS_PADS
GPIO_PADS
USBOTG_PADS
END_OF_PAD_ARRAY
};*/
static const PAD_INFO ebootPinMux_37XX[] =
{
DSS_PADS_37XX
GPIO_PADS_37XX
USBOTG_PADS
MCSPI1_PADS //Addition to MCSPI1 functional, Ray 13-09-24
I2C3_PADS //Addition to MCSPI1 functional, Ray 13-10-21
END_OF_PAD_ARRAY
};
OALLocalAllocInit(allocationPool, sizeof(allocationPool));
// Get processor and companion chip versions
g_CPUFamily = CPU_FAMILY_OMAP35XX;
CpuRevision = Get_CPUVersion();
version = CPU_REVISION(CpuRevision);
g_CPUFamily = CPU_FAMILY(CpuRevision);
// Set GPTIMER1 regs pointer
pTimerRegs = OALPAtoUA(OMAP_GPTIMER1_REGS_PA);
//if(g_CPUFamily == CPU_FAMILY_DM37XX)
//{
ConfigurePadArray(ebootPinMux_37XX);
//}
//else
//{
// ConfigurePadArray(ebootPinMux);
//}
OALLog(L"ZEBEX Windows CE EBOOT for Z-2170 plus - Ray Testing" //Ray 13-07-31
//OALLog(L"ZEBEX Windows CE EBOOT for Z-2170 plus - Brain"
L"\r\nBuilt %S at %S\r\n", __DATE__, __TIME__ );
/*OALLog(
L"EBOOT Version %d.%d, BSP " BSP_VERSION_STRING L"\r\n",
EBOOT_VERSION_MAJOR, EBOOT_VERSION_MINOR
);*/
// Soft reset GPTIMER1
OUTREG32(&pTimerRegs->TIOCP, SYSCONFIG_SOFTRESET);
// While until done
while ((INREG32(&pTimerRegs->TISTAT) & GPTIMER_TISTAT_RESETDONE) == 0)
;
// Enable posted mode
OUTREG32(&pTimerRegs->TSICR, GPTIMER_TSICR_POSTED);
// Start timer
OUTREG32(&pTimerRegs->TCLR, GPTIMER_TCLR_AR|GPTIMER_TCLR_ST);
// Enable device clocks used by the bootloader
EnableDeviceClocks(OMAP_DEVICE_GPIO1, TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO2, TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO3, TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO4, TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO5, TRUE);
EnableDeviceClocks(OMAP_DEVICE_GPIO6, TRUE);
// configure i2c devices
OALI2CInit(OMAP_DEVICE_I2C1);
OALI2CInit(OMAP_DEVICE_I2C2);
OALI2CInit(OMAP_DEVICE_I2C3);
GPIOInit();
// Note that T2 accesses must occur after I2C initialization
hTwl = TWLOpen();
hGPIO = GPIOOpen();
// Clear Reset on ethernet controller
//GPIOSetBit(hGPIO,LAN9115_RESET_GPIO);
//GPIOSetMode(hGPIO, LAN9115_RESET_GPIO,GPIO_DIR_OUTPUT);
// test GPIO
GPIOClrBit(hGPIO, 136); // VIBRATOR
GPIOSetMode(hGPIO, 136, GPIO_DIR_OUTPUT);
GPIOClrBit(hGPIO, 16); // WLAN_EN
GPIOSetMode(hGPIO, 16, GPIO_DIR_OUTPUT);
GPIOClrBit(hGPIO, 15); // BT_EN
GPIOSetMode(hGPIO, 15, GPIO_DIR_OUTPUT);
GPIOSetBit(hGPIO, 61); // BACKLIGHT_EN, Ray
GPIOSetMode(hGPIO, 61, GPIO_DIR_OUTPUT);
//Initialization Side key GPIO, Ray 13-08-12
GPIOSetMode(hGPIO, 114, GPIO_DIR_INPUT); // SIDE_KEY1(KEY_2_4)
GPIOSetMode(hGPIO, 115, GPIO_DIR_INPUT); // SIDE_KEY3(KEY_1_4)
//Initialization the "MC serial port interface (SPI1)" buses, Ray 13-09-24
GPIOSetMode(hGPIO, SPI_CS0_PIN, GPIO_DIR_OUTPUT);
GPIOSetMode(hGPIO, SPI_CLK_PIN, GPIO_DIR_OUTPUT);
GPIOSetMode(hGPIO, SPI_DOUT_PIN, GPIO_DIR_OUTPUT);
GPIOSetMode(hGPIO, SPI_DIN_PIN, GPIO_DIR_INPUT);
//Initialization the "I-suqare-c (i2c3)" buses, Ray 13-10-07
/*GPIOSetMode(hGPIO, I2C3_SCL_GPIO, INPUT_ENABLED);
GPIOSetMode(hGPIO, I2C3_SDA_GPIO, INPUT_ENABLED);*/
/*GPIOSetBit(hGPIO, I2C3_SCL_GPIO);
GPIOSetMode(hGPIO, I2C3_SCL_GPIO, GPIO_DIR_OUTPUT);
GPIOSetBit(hGPIO, I2C3_SDA_GPIO);
GPIOSetMode(hGPIO, I2C3_SDA_GPIO, GPIO_DIR_OUTPUT);*/
//SPI LCM setup
/*XX
GPIOSetBit(hGPIO,184); // PCM_EN serial clock
GPIOSetMode(hGPIO, 184, GPIO_PULLUP_ENABLE);
//GPIOSetMode(hGPIO, 184, GPIO_DIR_OUTPUT);
GPIOSetBit(hGPIO,185); // PCM_EN serial data
GPIOSetMode(hGPIO, 185, GPIO_PULLUP_ENABLE);
//GPIOSetMode(hGPIO, 185, GPIO_DIR_OUTPUT);*/
OALLog(L"\r\nTI OMAP%x Version 0x%08x (%s)\r\n", CPU_ID(CpuRevision), CPU_REVISION(CpuRevision),
version == CPU_FAMILY_35XX_REVISION_ES_1_0 ? L"ES1.0" :
version == CPU_FAMILY_35XX_REVISION_ES_2_0 ? L"ES2.0" :
version == CPU_FAMILY_35XX_REVISION_ES_2_1 ? L"ES2.1" :
version == CPU_FAMILY_35XX_REVISION_ES_2_0_CRC ? L"ES2.0, ID determined using CRC" :
version == CPU_FAMILY_35XX_REVISION_ES_2_1_CRC ? L"ES2.1, ID determined using CRC" :
version == CPU_FAMILY_35XX_REVISION_ES_3_0 ? L"ES3.0" :
version == CPU_FAMILY_35XX_REVISION_ES_3_1 ? L"ES3.1" :
version == CPU_FAMILY_37XX_REVISION_ES_1_0? L"ES1.0" :
version == CPU_FAMILY_37XX_REVISION_ES_1_1? L"ES1.1" :
version == CPU_FAMILY_37XX_REVISION_ES_1_2? L"ES1.2" :
L"Unknown" );
/* Initialize Device Prefix */
if(g_CPUFamily == CPU_FAMILY_DM37XX)
{
gDevice_prefix = BSP_DEVICE_37xx_PREFIX;
}
else if (g_CPUFamily == CPU_FAMILY_OMAP35XX)
{
gDevice_prefix = BSP_DEVICE_35xx_PREFIX;
}
else
{
OALLog(L"INFO: UnKnown CPU family:%d....\r\n", g_CPUFamily);
gDevice_prefix = BSP_DEVICE_35xx_PREFIX;
}
version = TWLReadIDCode(hTwl);
OALLog(L"TPS659XX Version 0x%02x (%s)\r\n", version,
version == 0x00 ? L"ES1.0" :
version == 0x10 ? L"ES1.1" :
version == 0x20 ? L"ES1.2" :
version == 0x30 ? L"ES1.3" : L"Unknown" );
g_ecctype = (UCHAR)dwEbootECCtype;
// Done
return TRUE;
}
//------------------------------------------------------------------------------
//
// Function: OEMPowerOff
//
// Called when the system is to transition to it's lowest power mode (off)
//
VOID
OEMPowerOff(
)
{
DWORD i;
UINT32 sysIntr;
UINT intr[3];
BOOL bPowerOn;
BOOL bPrevIntrState;
UINT irq = 0;
UINT32 mask = 0;
// disable interrupts (note: this should not be needed)
bPrevIntrState = INTERRUPTS_ENABLE(FALSE);
// UNDONE: verify if this is still necessary
// Disable hardware watchdog
OALWatchdogEnable(FALSE);
// Make sure that KITL is powered off
bPowerOn = FALSE;
KITLIoctl(IOCTL_KITL_POWER_CALL, &bPowerOn, sizeof(bPowerOn), NULL, 0, NULL);
//Save Perf Timer
OALContextSavePerfTimer();
// Disable GPTimer2 (used for high perf/monte carlo profiling)
EnableDeviceClocks(BSPGetGPTPerfDevice(), FALSE);
// Give chance to do board specific stuff
BSPPowerOff();
//----------------------------------------------
// capture all enabled interrupts and disable interrupts
intr[0] = INREG32(&g_pIntr->pICLRegs->INTC_MIR0);
intr[1] = INREG32(&g_pIntr->pICLRegs->INTC_MIR1);
intr[2] = INREG32(&g_pIntr->pICLRegs->INTC_MIR2);
OUTREG32(&g_pIntr->pICLRegs->INTC_MIR_SET0, OMAP_MPUIC_MASKALL);
OUTREG32(&g_pIntr->pICLRegs->INTC_MIR_SET1, OMAP_MPUIC_MASKALL);
OUTREG32(&g_pIntr->pICLRegs->INTC_MIR_SET2, OMAP_MPUIC_MASKALL);
//----------------------------------------------
// Context Save/Restore
// Save state then mask all GPIO interrupts
for (i=0; i<g_pIntr->nbGpioBank; i++)
{
INTR_GPIO_CTXT* pCurrGpioCtxt = &g_pIntr->pGpioCtxt[i];
// Save current state
pCurrGpioCtxt->restoreCtxt.IRQENABLE1 = INREG32(&pCurrGpioCtxt->pRegs->IRQENABLE1);
pCurrGpioCtxt->restoreCtxt.WAKEUPENABLE = INREG32(&pCurrGpioCtxt->pRegs->WAKEUPENABLE);
// Disable all GPIO interrupts in the bank
OUTREG32(&pCurrGpioCtxt->pRegs->IRQENABLE1, 0);
OUTREG32(&pCurrGpioCtxt->pRegs->WAKEUPENABLE, 0);
OALIntrEnableIrqs(1,&pCurrGpioCtxt->bank_irq);
}
//----------------------------------------------
// Clear all enabled IO PAD wakeups for GPIOs
for (i = 0; i < g_pIntr->nbGpioBank; ++i)
{
INTR_GPIO_CTXT* pCurrGpioCtxt = &g_pIntr->pGpioCtxt[i];
irq = BSPGetGpioIrq(0) + (i * 32);
mask = pCurrGpioCtxt->restoreCtxt.WAKEUPENABLE;
while (mask != 0)
{
// If a GPIO was wakeup enabled, then clear the wakeup
if (mask & 0x1)
{
OEMEnableIOPadWakeup((irq - BSPGetGpioIrq(0)), FALSE);
}
irq++;
mask >>= 1;
}
}
//----------------------------------------------
// Enable wake sources interrupts
for (sysIntr = SYSINTR_DEVICES; sysIntr < SYSINTR_MAXIMUM; sysIntr++)
{
// Skip if sysIntr isn't allowed as wake source
if (!OALPowerWakeSource(sysIntr))
continue;
// Enable it as interrupt
OEMInterruptEnable(sysIntr, NULL, 0);
}
// enter full retention
PrcmSuspend();
//----------------------------------------------
// Find wakeup source
for (sysIntr = SYSINTR_DEVICES; sysIntr < SYSINTR_MAXIMUM; sysIntr++)
{
// Skip if sysIntr isn't allowed as wake source
if (!OALPowerWakeSource(sysIntr))
continue;
// When this sysIntr is pending we find wake source
if (OEMInterruptPending(sysIntr))
{
g_oalWakeSource = sysIntr;
break;
}
}
//----------------------------------------------
// Context Save/Restore
// Put GPIO interrupt state back to the way it was before suspend
for (i=0; i<g_pIntr->nbGpioBank; i++)
{
INTR_GPIO_CTXT* pCurrGpioCtxt = &g_pIntr->pGpioCtxt[i];
// Write registers with the previously saved values
OUTREG32(&pCurrGpioCtxt->pRegs->IRQENABLE1, pCurrGpioCtxt->restoreCtxt.IRQENABLE1);
OUTREG32(&pCurrGpioCtxt->pRegs->WAKEUPENABLE, pCurrGpioCtxt->restoreCtxt.WAKEUPENABLE);
}
//-------------------------------------------------------
// Enable all previously enabled IO PAD wakeups for GPIOs
for (i = 0; i < g_pIntr->nbGpioBank; ++i)
{
INTR_GPIO_CTXT* pCurrGpioCtxt = &g_pIntr->pGpioCtxt[i];
irq = BSPGetGpioIrq(0) + (i * 32);
mask = pCurrGpioCtxt->restoreCtxt.WAKEUPENABLE;
while (mask != 0)
{
// If a GPIO was wakeup enabled, then clear the wakeup
if (mask & 0x1)
{
OEMEnableIOPadWakeup((irq - BSPGetGpioIrq(0)), TRUE);
}
irq++;
mask >>= 1;
}
}
//----------------------------------------------
// Re-enable interrupts
OUTREG32(&g_pIntr->pICLRegs->INTC_MIR_CLEAR0, ~intr[0]);
OUTREG32(&g_pIntr->pICLRegs->INTC_MIR_CLEAR1, ~intr[1]);
OUTREG32(&g_pIntr->pICLRegs->INTC_MIR_CLEAR2, ~intr[2]);
//----------------------------------------------
// Do board specific stuff
BSPPowerOn();
//Sync to Hardware RTC after suspend\resume
OALIoCtlHalRtcTime( 0, NULL, 0, NULL, 0, NULL);
// Enable GPTimer (used for high perf/monte carlo profiling)
EnableDeviceClocks(BSPGetGPTPerfDevice(), TRUE);
//Restore Perf Timer
OALContextRestorePerfTimer();
// Reinitialize KITL
bPowerOn = TRUE;
KITLIoctl(IOCTL_KITL_POWER_CALL, &bPowerOn, sizeof(bPowerOn), NULL, 0, NULL);
// Enable hardware watchdog
OALWatchdogEnable(TRUE);
#ifndef SHIP_BUILD
if (g_PrcmDebugSuspendResume)
{
OALMSG(1, (L"Enabled wake sources:\r\n"));
for (sysIntr = SYSINTR_FIRMWARE; sysIntr < SYSINTR_MAXIMUM; sysIntr++)
{
if (OALPowerWakeSource(sysIntr))
OALMSG(1, (L" SYSINTR %d\r\n", sysIntr));
}
OALMSG(1, (L"\r\nWake due to SYSINTR %d\r\n", g_oalWakeSource));
OALWakeupLatency_DumpSnapshot();
PrcmDumpSavedRefCounts();
DumpPrcmRegsSnapshot();
}
#endif
// restore interrupts
INTERRUPTS_ENABLE(bPrevIntrState);
}
