GpTimer::GpTimer(volatile unsigned int* pBase,
volatile unsigned int* pClockBase, unsigned int whichTimer)
: PeriodicTimer(pBase),
m_pClockBase(pClockBase),
m_whichTimer(whichTimer)
{
ASSERT(whichTimer == 1 || whichTimer == 2 || whichTimer == 10);
//reset it
m_pBase[sm_tiocp_cfg_1ms] = 2;
while (m_pBase[sm_tiocp_cfg_1ms] & 2);
//disable idling and clock activity
m_pBase[sm_tiocp_cfg_1ms] = (1 << 3) | (3 << 8);
unsigned int current = m_pBase[sm_tclr] & 0xffff8000;
//disable the timer [0]=0
//set autoreload mode [1]=1
current |= 2;
//disable prescaling[4:2]=0, [5]=0
//disable compare[6]=0
//disable pwm[7]=0
//disable capture[9:8]=0
m_pBase[sm_tclr] = current;
//enable the interrupt
EnableInterrupt(true);
}
/*
* Setup the timer 0 to generate the tick interrupts at the required frequency.
*/
static void prvSetupTimerInterrupt( void )
{
uint32_t ulCompareMatch;
/* Calculate the match value required for our wanted tick rate. */
ulCompareMatch = 1000000 / configTICK_RATE_HZ;
/* Protect against divide by zero. Using an if() statement still results
in a warning - hence the #if. */
#if portPRESCALE_VALUE != 0
{
ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
}
#endif
DisableInterrupts();
pRegs->CTL = 0x003E0000;
pRegs->LOD = ulCompareMatch;
pRegs->RLD = ulCompareMatch;
pRegs->DIV = portTIMER_PRESCALE;
pRegs->CLI = 0;
pRegs->CTL = 0x003E00A2;
RegisterInterrupt(64, vTickISR, NULL);
EnableInterrupt(64);
EnableInterrupts();
}
static void SetVGAHorizontalSync31kHzAtInterrupt(InterruptHandler *handler,int dier)
{
WaitForLastLineIfVGAEnabled();
TIM2->DIER=dier;
TIM2->CCER=TIM_CCER_CC4E|TIM_CCER_CC4P; // Channel 4 enabled, reversed polarity (active low).
// Enable HSync timer interrupt and set highest priority.
InstallInterruptHandler(TIM2_IRQn,handler);
EnableInterrupt(TIM2_IRQn);
SetInterruptPriority(TIM2_IRQn,0);
}
status_t
VirtioQueue::Interrupt()
{
CALLED();
DisableInterrupt();
while (fRingUsedIndex != fRing.used->idx)
Finish();
EnableInterrupt();
return B_OK;
}
static void SetVGAHorizontalSync31kHzActiveHighAtInterrupt(InterruptHandler *handler,int dier)
{
WaitForLastLineIfVGAEnabled();
TIM2->DIER=dier; // Enable update interrupt.
TIM2->CCER=TIM_CCER_CC4E; // Channel 4 enabled, normal polarity (active high).
// Enable HSync timer interrupt and set highest priority.
InstallInterruptHandler(TIM2_IRQn,handler);
EnableInterrupt(TIM2_IRQn);
SetInterruptPriority(TIM2_IRQn,0);
}
BOOL CPdd6410Uart::InitialEnableInterrupt(BOOL bEnable )
{
m_HardwareLock.Lock();
if (bEnable)
{
EnableInterrupt(S6410UART_INT_RXD | S6410UART_INT_ERR | S6410UART_INT_MODEM);
}
else
{
DisableInterrupt(S6410UART_INT_RXD | S6410UART_INT_ERR | S6410UART_INT_MODEM);
}
m_HardwareLock.Unlock();
return TRUE;
}
static void InitializePixelDMA(int pixelclock)
{
// Configure timer 8 as the pixel clock.
TIM8->CR1=TIM_CR1_ARPE;
TIM8->DIER=TIM_DIER_UDE; // Enable update DMA request.
TIM8->PSC=0; // Prescaler = 1
TIM8->ARR=pixelclock-1; // TODO: Should this be -1?
// DMA2 stream 1 channel 7 is triggered by timer 8.
// Stop it and configure interrupts.
DMA2_Stream1->CR&=~DMA_SxCR_EN;
InstallInterruptHandler(DMA2_Stream1_IRQn,DMACompleteHandler);
EnableInterrupt(DMA2_Stream1_IRQn);
SetInterruptPriority(DMA2_Stream1_IRQn,0);
}
bool ProvideAudioBufferWithoutBlocking(void *samples,int numsamples)
{
if(NextBufferSamples) return false;
DisableInterrupt(DMA1_Stream7_IRQn);
NextBufferSamples=samples;
NextBufferLength=numsamples;
if(!DMARunning) StartAudioDMAAndRequestBuffers();
EnableInterrupt(DMA1_Stream7_IRQn);
return true;
}
NTSTATUS
BalloonInterruptEnable(
IN WDFINTERRUPT WdfInterrupt,
IN WDFDEVICE WdfDevice
)
{
PDEVICE_CONTEXT devCtx = NULL;
TraceEvents(TRACE_LEVEL_VERBOSE, DBG_PNP, "--> %s\n", __FUNCTION__);
devCtx = GetDeviceContext(WdfDevice);
EnableInterrupt(WdfInterrupt, devCtx);
TraceEvents(TRACE_LEVEL_VERBOSE, DBG_PNP, "<-- %s\n", __FUNCTION__);
return STATUS_SUCCESS;
}
void timer_init( void )
{
DisableInterrupt(64);
g_VectorTable[64].pfnHandler=tickISR;
timerRegs->CTL = 0x003E0000;
timerRegs->LOD = 1000000/OS_TICKS_PER_SEC - 1;
timerRegs->RLD = 1000000/OS_TICKS_PER_SEC - 1;
timerRegs->DIV = 0xF9;
timerRegs->CLI = 0;
timerRegs->CTL = 0x003E00A2;
EnableInterrupt(64);
}
void PlayAudioWithCallback(AudioCallbackFunction *callback,void *context)
{
StopAudioDMA();
InstallInterruptHandler(DMA1_Stream7_IRQn,DMACompleteHandler);
EnableInterrupt(DMA1_Stream7_IRQn);
SetInterruptPriority(DMA1_Stream7_IRQn,4);
SPI3->CR2|=SPI_CR2_TXDMAEN; // Enable I2S TX DMA request.
CallbackFunction=callback;
CallbackContext=context;
BufferNumber=0;
if(CallbackFunction) CallbackFunction(CallbackContext,BufferNumber);
}
int main(void)
{
uint8 test[64],i;
DisableInterrupt();
sys_init();
EnableInterrupt();
for(;;)
{
//Process_Event();
}
// for(i=0;i<64;i++)
// {
// test[i]=i;
// }
// /********************send test***********************/
//
// while(1)
// {
// A7139_StrobeCmd(CMD_PLL);
// delay_us(1);
// A7139_WriteFIFO(test,64);
// delay_us(1);
// A7139_StrobeCmd(CMD_TX);
// delay_us(1);
// while(GIO2);
// //delay_ms(11); delay_ms(1000);
// LED1_REV();
// delay_ms(50);
// }
/*******************************************************/
/*****************receive test**************************///ÓÃÖжϲâ½ÓÊÕ
// while(1)
// {
// A7139_StrobeCmd(CMD_PLL);
// delay_us(2);
// A7139_StrobeCmd(CMD_RX);
// delay_us(1);
// while(GIO1);
// A7139_ReadFIFO(DataRecv,64);
// LED2_REV();
// }
/*******************************************************/
}
static void InitializePixelDMA(int pixelclock,int pixelsperrow)
{
// Configure timer 8 as the pixel clock.
TIM8->CR1=TIM_CR1_ARPE;
TIM8->DIER=TIM_DIER_UDE; // Enable update DMA request.
TIM8->PSC=0; // Prescaler = 1.
TIM8->ARR=pixelclock-1;
TIM8->SMCR=(5*TIM_SMCR_SMS_0)|(1*TIM_SMCR_TS_0); // Only run TIM8 when TIM2 trigger-out is high.
// DMA2 stream 1 channel 7 is triggered by timer 8.
// Stop it and configure interrupts.
DMA2_Stream1->CR&=~DMA_SxCR_EN;
InstallInterruptHandler(DMA2_Stream1_IRQn,DMACompleteHandler);
EnableInterrupt(DMA2_Stream1_IRQn);
SetInterruptPriority(DMA2_Stream1_IRQn,0);
VGAPixelsPerRow=pixelsperrow;
}
void InitializeVGAHorizontalSync31kHz(InterruptHandler *handler)
{
// Configure timer 9 as the HSYNC timer.
TIM9->CR1=TIM_CR1_ARPE;
TIM9->DIER=TIM_DIER_UIE|TIM_DIER_CC1IE|TIM_DIER_CC2IE; // Enable update, compare 1 and 2 interrupts.
TIM9->CCMR1=0;
TIM9->CCER=0;
TIM9->PSC=0; // Prescaler = 1
TIM9->ARR=5337; // 168 MHz / 31.4686 kHz = 5338.65504
TIM9->CCR1=633; // 168 MHz * 3.77 microseconds = 633.36 - sync pulse end
TIM9->CCR2=950; // 168 MHz * (3.77 + 1.89) microseconds = 950.88 - back porch end
// Enable HSYNC timer interrupt and set highest priority.
InstallInterruptHandler(TIM1_BRK_TIM9_IRQn,handler);
EnableInterrupt(TIM1_BRK_TIM9_IRQn);
SetInterruptPriority(TIM1_BRK_TIM9_IRQn,0);
// Enable HSYNC timer.
TIM9->CR1|=TIM_CR1_CEN;
}
/**
* @brief Main program
* @param None
* @retval None
*/
int main(void)
{
/*!< At this stage the microcontroller clock setting is already configured,
this is done through SystemInit() function which is called from startup
file (startup_stm32f30x.s) before to branch to application main.
To reconfigure the default setting of SystemInit() function, refer to
system_stm32f30x.c file
*/
if (SysTick_Config(SystemCoreClock / 1000))
{
/* Capture error */
while (1);
}
//All Init here
led_init();
usart_init();
TIM_Config();
PWM_Config();
EnableInterrupt();
while (1)
{
/*
if((asn % N_TIME_SLOT == TSLOT_ID) && (ts_enable_transmision == 1))
{
ts_enable_transmision = 0;
for(int i=0; i < 4; i++)
{
while (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET);
USART_SendData(USART1, message[i]);
}
}*/
}
}
//
//Create a thread,and put the thread's control block into array g_pKThreadQueue,
//and update the corresponding queue.
//If failed,it returns 0,otherwise,returns the created kernal thread's ID.
//
DWORD CreateKThread(DWORD dwStackSize, //Thread's stack size.
DWORD dwFlags, //Flags.
DWORD dwPriority, //Priority.
LPKTHREAD_ROUTINE pStartAddress, //Start running address.
LPVOID pData, //Parameter.
LPVOID /*pReserved*/) //Reserved.
{
DWORD dwKThreadID = 0x00000000;
struct __KTHREAD_CONTROL_BLOCK* pControlBlock = NULL;
LPVOID pStackPointer = NULL;
BOOL bFind = FALSE;
RoundTo4k(dwStackSize); //Round the stack size to 4k times.
pControlBlock = (struct __KTHREAD_CONTROL_BLOCK*) KMemAlloc(dwStackSize,KMEM_SIZE_TYPE_4K);
if(NULL == pControlBlock) //If can not allocate the memory.
{
return dwKThreadID;
}
MemZero((LPVOID)pControlBlock,dwStackSize); //Zero the memory allocated just now.
pControlBlock->pKThreadRoutine = pStartAddress; //Members initialization.
pControlBlock->dwKThreadPriority = dwPriority;
pControlBlock->pData = pData;
pControlBlock->wCurrentMsgNum = 0x0000;
pControlBlock->wHeader = 0x0000;
pControlBlock->wTrial = 0x0000;
//DisableInterrupt(); //Disable interrupt.
// ****************
for(dwKThreadID = 0;dwKThreadID < MAX_KTHREAD_NUM;dwKThreadID ++)
{
if(0 == g_bKThreadQueueStatus[dwKThreadID]) //Find a free control block slot.
{
bFind = TRUE;
break;
}
}
if(FALSE == bFind) //If can not find a free control block slot.
{
KMemFree((LPVOID)pControlBlock,KMEM_SIZE_TYPE_4K,dwStackSize); //Free the memory.
return 0L;
}
DisableInterrupt(); //Disable interrupt.
//******************
g_pKThreadQueue[dwKThreadID] = pControlBlock;
g_bKThreadQueueStatus[dwKThreadID] = 1; //Set the occupied flag.
dwKThreadID ++; //Increase the KThreadID.
pControlBlock->dwKThreadID = dwKThreadID;
pControlBlock->dwStackSize = dwStackSize;
switch(dwFlags) //Update the proper kernal thread queues.
//Insert the created kernal thread into
//the status queue.
{
case KTHREAD_STATUS_BLOCKED: //Insert into blocked queue.
pControlBlock->dwKThreadStatus = KTHREAD_STATUS_BLOCKED;
pControlBlock->pNext = g_pBlockedQueue;
g_pBlockedQueue = pControlBlock;
break;
case KTHREAD_STATUS_SUSPEND: //Insert it into suspended queue.
pControlBlock->dwKThreadStatus = KTHREAD_STATUS_SUSPEND;
pControlBlock->pNext = g_pSuspendQueue;
g_pSuspendQueue = pControlBlock;
break;
default: //All other status,insert into ready queue.
case KTHREAD_STATUS_READY:
case KTHREAD_STATUS_RUNNING:
pControlBlock->dwKThreadStatus = KTHREAD_STATUS_READY;
pControlBlock->pNext = g_pReadyQueue;
g_pReadyQueue = pControlBlock;
break;
}
#ifdef __I386__ //Update the x86 CPU's context.
pControlBlock->dwESP = (DWORD)pControlBlock + dwStackSize;
pControlBlock->dwEIP = (DWORD)pStartAddress;
pControlBlock->dwEFlags = 512; //*****************************
#else
#endif
EnableInterrupt(); //Enable interrupt.
//*****************
return dwKThreadID;
}
void UART_IRQHandler(void)
{
uint32_t iir = LPC_USART->IIR;
uint32_t data;
int cnt;
uint32_t iid = iir & LPCUART_IIR_ID_MASK;
if ((iir & LPCUART_IIR_STATUS) == 0)
{
switch (iid)//r & LPCUART_IIR_ID_MASK)
{
case LPCUART_IIR_ID_MS:
// data = LPC_USART->MCR;
// break;
case LPCUART_IIR_ID_RLS: // Line status
{
uint32_t r = LPC_USART->LSR;
if (g_LpcUartDev->pUartDev->EvtCallback)
{
data = (r & LPCUART_LSR_OE) ? UART_LINESTATE_OVR : 0;
data |= (r & LPCUART_LSR_PE) ? UART_LINESTATE_PARERR : 0;
data |= (r & LPCUART_LSR_FE) ? UART_LINESTATE_FRMERR : 0;
data |= (r & LPCUART_LSR_BI) ? UART_LINESTATE_BRK : 0;
data |= (r << 16L);
r = LPC_USART->MSR;
if (r & LPCUART_MSR_DCTS)
{
g_LpcUartDev->pUartDev->LineState ^= UART_LINESTATE_CTS;
data |= (g_LpcUartDev->pUartDev->LineState & UART_LINESTATE_CTS);
}
//data |= (r & LPCUART_MSR_CTS) ? UART_LINESTATE_CTS : 0;
data |= (r & LPCUART_MSR_DDSR) ? UART_LINESTATE_DSR : 0;
data |= (r & LPCUART_MSR_RI) ? UART_LINESTATE_RI : 0;
data |= (r & LPCUART_MSR_DCD) ? UART_LINESTATE_DCD : 0;
data |= (r << 24L);
g_LpcUartDev->pUartDev->EvtCallback(g_LpcUartDev->pUartDev, UART_EVT_LINESTATE, (uint8_t*)&data, 1);
}
}
//break;
case LPCUART_IIR_ID_CTIMOUT:
//flushrx = true;
//break;
case LPCUART_IIR_ID_RDA:
//case LPCUART_IIR_ID_THRE:
{
cnt = 0;
uint32_t state = DisableInterrupt();
while ((g_LpcUartDev->pUartReg->LSR & LPCUART_LSR_RDR) && cnt < 14) {
//while (LpcUARTWaitForRxFifo(&g_LpcUartDev, 10) && cnt < 8) {
//do {
uint8_t *p = CFifoPut(g_LpcUartDev->pUartDev->hRxFifo);
if (p)
{
//d[cnt++] = g_LpcUartDev->pUartReg->RBR;
*p = g_LpcUartDev->pUartReg->RBR;
cnt++;
}
else
{
//printf("drop2\r\n");
break;
}
}
//while ((g_LpcUartDev->pUartReg->LSR & LPCUART_LSR_RDR) && cnt < 14);
cnt = CFifoUsed(g_LpcUartDev->pUartDev->hRxFifo);
EnableInterrupt(state);
//data = LPC_USART->RBR;
if (g_LpcUartDev->pUartDev->EvtCallback)
{
if (iid == LPCUART_IIR_ID_CTIMOUT)
g_LpcUartDev->pUartDev->EvtCallback(g_LpcUartDev->pUartDev, UART_EVT_RXTIMEOUT, NULL, cnt);
else //if (cnt > 8)
g_LpcUartDev->pUartDev->EvtCallback(g_LpcUartDev->pUartDev, UART_EVT_RXDATA, NULL, cnt);
}
}
break;
case LPCUART_IIR_ID_THRE:
//data = LPC_USART->LSR;
{
cnt = 0;
uint32_t state = DisableInterrupt();
g_LpcUartDev->bTxReady = false;
do {
uint8_t *p = CFifoGet(g_LpcUartDev->pUartDev->hTxFifo);
if (p == NULL)
{
g_LpcUartDev->bTxReady = true;
break;
}
LPC_USART->THR = *p;
cnt++;
} //while (LpcUARTWaitForTxFifo(&g_LpcUartDev, 10) && cnt < 14);
while (g_LpcUartDev->pUartReg->LSR & (LPCUART_LSR_TEMT | LPCUART_LSR_THRE) && cnt < 14);
EnableInterrupt(state);
if (g_LpcUartDev->pUartDev->EvtCallback)
{
int len = CFifoAvail(g_LpcUartDev->pUartDev->hTxFifo);
len = g_LpcUartDev->pUartDev->EvtCallback(g_LpcUartDev->pUartDev, UART_EVT_TXREADY, NULL, len);
if (len > 0)
{
//LpcUARTTxData(&g_LpcUartDev->pUartDev->SerIntrf, d, len);
// LPC_USART->THR = d[0];
}
if (g_LpcUartDev->bTxReady)
{
if (g_LpcUartDev->pUartReg->LSR & (LPCUART_LSR_TEMT | LPCUART_LSR_THRE))
{
uint8_t *p = CFifoGet(g_LpcUartDev->pUartDev->hTxFifo);
if (p == NULL)
{
g_LpcUartDev->bTxReady = true;
break;
}
LPC_USART->THR = *p;
}
}
}
}
break;
default:
;
}
}
}
void S3C2450DISP::SetVisibleSurface( GPESurf *pTempSurf, BOOL bWaitForVBlank)
{
static int timeoutcnt=0;
DWORD we;
#ifdef HIGH_PRIORITY_INTR
int iPriority;
HANDLE hThread;
hThread = GetCurrentThread();
iPriority = CeGetThreadPriority(hThread);
CeSetThreadPriority(hThread, DISPDRV_IST_PRIORITY);
#endif
S3C2450Surf *pSurf = (S3C2450Surf *) pTempSurf;
EnterCriticalSection(&m_CS);
// assume Synchronous to VSYNC
EnableInterrupt();
we = WaitForSingleObject(m_hVSYNCInterruptEvent,1000/*INFINITE*/);
DisableInterrupt();
InterruptDone(m_dwVSYNCSysIntr);
if(we != WAIT_OBJECT_0)
{
timeoutcnt++;
RETAILMSG(1,(TEXT("Surface Flipping Time Out %d !!!\n"), timeoutcnt));
for(int i=0;i<78;i++)
RETAILMSG(1,(TEXT("0x%08X = 0x%08X\n"),(DWORD*)((DWORD*)m_pLCDReg + i),*(DWORD*)((DWORD*)m_pLCDReg + i)));
RETAILMSG(1,(TEXT("saved_x=%d"),saved_x));
RETAILMSG(1,(TEXT("saved_y=%d"),saved_y));
RETAILMSG(1,(TEXT("saved_width=%d"),saved_width));
RETAILMSG(1,(TEXT("saved_height=%d"),saved_height));
while(1);
}
if(pSurf->m_bIsOverlay == FALSE)
{
//RETAILMSG(1,(TEXT("pSurf->OffsetInVideoMemory()=0x%08X\n"),pSurf->OffsetInVideoMemory()));
m_pVisibleSurface = pSurf;
m_pLCDReg->VIDW00ADD0B0 = (UINT32)(pSurf->OffsetInVideoMemory() + IMAGE_FRAMEBUFFER_DMA_BASE);
// buffer end address
m_pLCDReg->VIDW00ADD1B0 = (UINT32)(pSurf->OffsetInVideoMemory() + IMAGE_FRAMEBUFFER_DMA_BASE) + (LCD_XSIZE_TFT*LCD_YSIZE_TFT*2);
// buffer size
m_pLCDReg->VIDW00ADD2B0 = (0<<VIDWxADD2_OFFSET_SIZE_S)|(LCD_XSIZE_TFT*2);
}
else
{
m_pLCDReg->VIDW01ADD0 = (UINT32)(pSurf->OffsetInVideoMemory() + IMAGE_FRAMEBUFFER_DMA_BASE);
// buffer end address
m_pLCDReg->VIDW01ADD1 = (UINT32)(pSurf->OffsetInVideoMemory() + IMAGE_FRAMEBUFFER_DMA_BASE) +
(pSurf->Width()*pSurf->Height()*2);
// buffer size
m_pLCDReg->VIDW01ADD2 = (0<<VIDWxADD2_OFFSET_SIZE_S)|(pSurf->Width()*2);
}
RETAILMSG(DBGLCD, (TEXT("S3C2450DISP::SetVisibleSurface\r\n")));
LeaveCriticalSection(&m_CS);
#ifdef HIGH_PRIORITY_INTR
CeSetThreadPriority(hThread, iPriority);
#endif
}
int USBTesting()
{
UINT ch; // channel number
UINT TX_Status;
CHAR *dma_src_addr;
#ifdef UDC_SOCLE_PHY
ASSERT_SOFT_POR();
#if 0
isr_time_value = 0;
isr_waiting_time = 1;
setup_1ms_timer(1);
#else
MSDELAY(1);
#endif
while (isr_time_value != isr_waiting_time);
DEASSERT_SOFT_POR();
#endif
#ifdef UDC_SOCLE_PHY
#if 0
isr_time_value = 0;
isr_waiting_time = 8;
setup_1ms_timer(8);
#else
MSDELAY(8);
#endif
while (isr_time_value != isr_waiting_time);
// SET_PHY_16_BIT();
#endif
ResetFlag = 0;
bIsConnected = VBUS_OK();
// if (bIsConnected)
// printf(" -> USB VBus connect\n");
// else
// printf(" -> USB VBus disconnect");
// enable interrupt
INT0_ENABLE(LDK_INTC_UDC);
// setup interrupt handler
connectInterrupt( LDK_INTC_UDC, UDCIintHandler, NULL);
INT0_SET_MASK(LDK_INTC_UDC);
while (1) {
// ;printf("\n USB cable disconnected!\n");
SOFT_DISCONNECT();
// wait for plugin stable on vbus
printf("\nWait for USB Host connect...");
// while ( !bIsConnected );
//CY++ for checking USB Host connect waiting
int wait=0;
while ( !bIsConnected ){
MSDELAY(60);
printf("%4d", wait);
wait++;
if(wait > 100)
return USB_NO_CONNECT_ERROR;
printf("\b\b\b\b");
}
#ifdef UDC_SOCLE_PHY
ASSERT_SOFT_POR();
#if 0
isr_time_value = 0;
isr_waiting_time = 1;
setup_1ms_timer(1);
#else
MSDELAY(1);
#endif
while (isr_time_value != isr_waiting_time);
DEASSERT_SOFT_POR();
#endif
#ifdef UDC_SOCLE_PHY
#if 0
isr_time_value = 0;
isr_waiting_time = 8;
setup_1ms_timer(8);
#else
MSDELAY(8);
#endif
while (isr_time_value != isr_waiting_time);
// SET_PHY_16_BIT();
#endif
initUDCController(); // initialize UDC Controller
initUDCTestingEnv(); // initialize UDC testing environment
SOFT_CONNECT();
;//printf("\n USB cable connected!\n");
uNeedDoProcCtrlBlockNum = 0;
for (ch = 0; ch < NUM_OF_USB_CHANNEL; ch++) {
ChannelSet[ch].uLoopbackCount = 0;
ChannelSet[ch].uIntrINCount = 0;
// start receive from Bulk_OUT pipe
writew(virt_to_phy( (u32_t)ChannelSet[ch].pBulkOutBuffer), UDC_DMALM_OADDR(ChannelSet[ch].uBulk_OUT));
writew( ENP_DMA_START, UDC_DMACTRLO(ChannelSet[ch].uBulk_OUT));
}
while ( bIsConnected ) {
// check ENP 0 transmit request
if ( uNeedDoProcCtrlBlockNum > 0 ) {
int dma_size;
// dma done now, polling for empty data set
if (!( readw(UDC_TX0BUF) & TxFULL)) {
// critical section
DisableInterrupt();
uNeedDoProcCtrlBlockNum--;
dma_src_addr = CtrlInBuffer + uCurrentCtrlBlockNum++ * uCurrentCtrlPacketSize;
if ( uControlDataSize > uCurrentCtrlPacketSize ) {
dma_size = uCurrentCtrlPacketSize;
}
else {
dma_size = uControlDataSize;
}
// calculate remaining bytes need transfer
uControlDataSize -= dma_size;
writew( dma_size, UDC_TX0STAT );
writew( virt_to_phy((u32_t)dma_src_addr) , UDC_DMA0LM_IADDR );
writew( ENP_DMA_START , UDC_DMA0CTLI );
EnableInterrupt();
// set ACK--after we have overwritten the previously incorrect data
writew( readw( UDC_TX0CON ) & ~TxNAK, UDC_TX0CON );
}
}
// check channel group transmit request
for (ch = 0; ch < NUM_OF_USB_CHANNEL; ch++) {
// check each Bulk_IN End Point transmit request
if ( ChannelSet[ch].uLoopbackCount > 0 ) {
if (ChannelSet[ch].bBulkDMAOnGoing == false) {
// check buffer is available for transmit data
TX_Status = readw(UDC_TXBUF(ChannelSet[ch].uBulk_IN)); // get buffer status
if ((TX_Status & TxFULL) == 0) {
#if 0
if ((TX_Status & TxDS0) == 0)
DEBUG_OUT('0');
if ((TX_Status & TxDS1) == 0)
DEBUG_OUT('1');
#endif
//DEBUG_OUT('i');
// enter critical section, protect share variable
DisableInterrupt();
//DEBUG_OUT('+');
ChannelSet[ch].uLoopbackCount--;
// get transmit buffer address & move buffer to next position
dma_src_addr = ChannelSet[ch].pBulkInBuffer + ChannelSet[ch].uCurrentBulkInBlockNum * uBulkBlockSize;
// setup DMA
writew( ChannelSet[ch].sBulkBlockSizeBuffer[ChannelSet[ch].uCurrentBulkInBlockNum],
UDC_TXSTAT(ChannelSet[ch].uBulk_IN) ); // write transmit count
writew( virt_to_phy((u32_t)dma_src_addr), // set transmit buffer pointer
UDC_DMALM_IADDR(ChannelSet[ch].uBulk_IN) );
writew( ENP_DMA_START , UDC_DMACTRLI(ChannelSet[ch].uBulk_IN) ); // start transmit DMA
// move to next buffer
ChannelSet[ch].uCurrentBulkInBlockNum = ++ChannelSet[ch].uCurrentBulkInBlockNum % uMaxBlockNumber;
#if 0
WAIT_DMA_DONE(UDC_TXSTAT(ChannelSet[ch].uBulk_IN));
#endif
#if 0
for (delay = 0; delay < 1000; delay++) {
TX2_DMAOnGoing = true;
}
#endif
ChannelSet[ch].bBulkDMAOnGoing = true;
//DEBUG_OUT('-');
EnableInterrupt();
// leave critical section
}
}
}
// check each Intr_IN End Point transmit request
if ( ChannelSet[ch].uIntrINCount > 0 ) {
// if (!( readw(UDC_TXBUF(ChannelSet[ch].uIntr_IN)) & TxFULL)) {
if (ChannelSet[ch].bIntrDMAOnGoing == false) {
// critical section
DisableInterrupt();
ChannelSet[ch].uCurrentIntrInBlockNum--;
dma_src_addr = ChannelSet[ch].pIntrInBuffer + ChannelSet[ch].uCurrentIntrInBlockNum * INTR_BLOCK_SIZE;
EnableInterrupt();
writew( INTR_BLOCK_SIZE, UDC_TXSTAT(ChannelSet[ch].uIntr_IN) );
writew( virt_to_phy((u32_t)dma_src_addr), UDC_DMALM_IADDR(ChannelSet[ch].uIntr_IN) );
writew( ENP_DMA_START, UDC_DMACTRLI(ChannelSet[ch].uIntr_IN) );
ChannelSet[ch].bIntrDMAOnGoing = true;
#if 0
WAIT_DMA_DONE(UDC_DMACTRLI(ChannelSet[ch].uIntr_IN) );
#endif
ChannelSet[ch].uCurrentBulkInBlockNum = ++ChannelSet[ch].uCurrentBulkInBlockNum % MAX_INTR_NUM;
}
}
}
}
}
// leave usb test now, should never been here
return 0;
}
/**
Start function of Driver binding protocol which start this driver on Controller
by detecting all disks and installing BlockIo protocol on them.
@param This Protocol instance pointer.
@param Controller Handle of device to bind driver to.
@param RemainingDevicePath produce all possible children.
@retval EFI_SUCCESS This driver is added to ControllerHandle.
@retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.
@retval other This driver does not support this device.
**/
EFI_STATUS
EFIAPI
IDEBusDriverBindingStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
EFI_STATUS Status;
EFI_STATUS SavedStatus;
EFI_PCI_IO_PROTOCOL *PciIo;
EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
EFI_DEV_PATH *Node;
UINT8 IdeChannel;
UINT8 BeginningIdeChannel;
UINT8 EndIdeChannel;
UINT8 IdeDevice;
UINT8 BeginningIdeDevice;
UINT8 EndIdeDevice;
IDE_BLK_IO_DEV *IdeBlkIoDevice[IdeMaxChannel][IdeMaxDevice];
IDE_BLK_IO_DEV *IdeBlkIoDevicePtr;
IDE_REGISTERS_BASE_ADDR IdeRegsBaseAddr[IdeMaxChannel];
ATA_TRANSFER_MODE TransferMode;
ATA_DRIVE_PARMS DriveParameters;
EFI_DEV_PATH NewNode;
UINT8 ConfigurationOptions;
UINT16 CommandBlockBaseAddr;
UINT16 ControlBlockBaseAddr;
UINTN DataSize;
IDE_BUS_DRIVER_PRIVATE_DATA *IdeBusDriverPrivateData;
UINT64 Supports;
//
// Local variables declaration for IdeControllerInit support
//
EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
BOOLEAN EnumAll;
BOOLEAN ChannelEnabled;
UINT8 MaxDevices;
EFI_IDENTIFY_DATA IdentifyData;
EFI_ATA_COLLECTIVE_MODE *SupportedModes;
IdeBusDriverPrivateData = NULL;
SupportedModes = NULL;
//
// Perform IdeBus initialization
//
Status = gBS->OpenProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
(VOID **) &ParentDevicePath,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
if ((EFI_ERROR (Status)) && (Status != EFI_ALREADY_STARTED)) {
return Status;
}
//
// Now open the IDE_CONTROLLER_INIT protocol. Step7.1
//
Status = gBS->OpenProtocol (
Controller,
&gEfiIdeControllerInitProtocolGuid,
(VOID **) &IdeInit,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
//
// The following OpenProtocol function with _GET_PROTOCOL attribute and
// will not return EFI_ALREADY_STARTED, so save it for now
//
SavedStatus = Status;
if ((EFI_ERROR (Status)) && (Status != EFI_ALREADY_STARTED)) {
DEBUG ((EFI_D_ERROR, "Open Init, Status=%x", Status));
//
// open protocol is not SUCCESS or not ALREADY_STARTED, error exit
//
goto ErrorExit;
}
//
// Save Enumall. Step7.2
//
EnumAll = IdeInit->EnumAll;
//
// Consume PCI I/O protocol. Note that the OpenProtocol with _GET_PROTOCOL
// attribute will not return EFI_ALREADY_STARTED
//
Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
(VOID **) &PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "Open PciIo, Status=%x", Status));
goto ErrorExit;
}
//
// We must check EFI_ALREADY_STARTED because many ATAPI devices are removable
//
if (SavedStatus != EFI_ALREADY_STARTED) {
IdeBusDriverPrivateData = AllocatePool (sizeof (IDE_BUS_DRIVER_PRIVATE_DATA));
if (IdeBusDriverPrivateData == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto ErrorExit;
}
ZeroMem (IdeBusDriverPrivateData, sizeof (IDE_BUS_DRIVER_PRIVATE_DATA));
Status = gBS->InstallMultipleProtocolInterfaces (
&Controller,
&gEfiCallerIdGuid,
IdeBusDriverPrivateData,
NULL
);
if (EFI_ERROR (Status)) {
goto ErrorExit;
}
} else {
Status = gBS->OpenProtocol (
Controller,
&gEfiCallerIdGuid,
(VOID **) &IdeBusDriverPrivateData,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
);
if (EFI_ERROR (Status)) {
IdeBusDriverPrivateData = NULL;
goto ErrorExit;
}
}
Status = PciIo->Attributes (
PciIo,
EfiPciIoAttributeOperationSupported,
0,
&Supports
);
if (!EFI_ERROR (Status)) {
Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
Status = PciIo->Attributes (
PciIo,
EfiPciIoAttributeOperationEnable,
Supports,
NULL
);
}
if (EFI_ERROR (Status)) {
goto ErrorExit;
}
//
// Read the environment variable that contains the IDEBus Driver's
// Config options that were set by the Driver Configuration Protocol
//
DataSize = sizeof (ConfigurationOptions);
Status = gRT->GetVariable (
(CHAR16 *) L"Configuration",
&gEfiCallerIdGuid,
NULL,
&DataSize,
&ConfigurationOptions
);
if (EFI_ERROR (Status)) {
ConfigurationOptions = 0x0f;
}
if (EnumAll || RemainingDevicePath == NULL) {
//
// If IdeInit->EnumAll is TRUE or RemainingDevicePath is NULL,
// must enumerate all IDE devices anyway
//
BeginningIdeChannel = IdePrimary;
EndIdeChannel = IdeSecondary;
BeginningIdeDevice = IdeMaster;
EndIdeDevice = IdeSlave;
} else if (!IsDevicePathEnd (RemainingDevicePath)) {
//
// If RemainingDevicePath isn't the End of Device Path Node,
// only scan the specified device by RemainingDevicePath
//
Node = (EFI_DEV_PATH *) RemainingDevicePath;
BeginningIdeChannel = Node->Atapi.PrimarySecondary;
EndIdeChannel = BeginningIdeChannel;
BeginningIdeDevice = Node->Atapi.SlaveMaster;
EndIdeDevice = BeginningIdeDevice;
if (BeginningIdeChannel >= IdeMaxChannel || EndIdeChannel >= IdeMaxChannel) {
Status = EFI_INVALID_PARAMETER;
goto ErrorExit;
}
if (BeginningIdeDevice >= IdeMaxDevice|| EndIdeDevice >= IdeMaxDevice) {
Status = EFI_INVALID_PARAMETER;
goto ErrorExit;
}
} else {
//
// If RemainingDevicePath is the End of Device Path Node,
// skip enumerate any device and return EFI_SUCESSS
//
BeginningIdeChannel = IdeMaxChannel;
EndIdeChannel = IdeMaxChannel - 1;
BeginningIdeDevice = IdeMaxDevice;
EndIdeDevice = IdeMaxDevice - 1;
}
//
// Obtain IDE IO port registers' base addresses
//
Status = GetIdeRegistersBaseAddr (PciIo, IdeRegsBaseAddr);
if (EFI_ERROR (Status)) {
goto ErrorExit;
}
//
// Report status code: begin IdeBus initialization
//
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
EFI_PROGRESS_CODE,
(EFI_IO_BUS_ATA_ATAPI | EFI_IOB_PC_RESET),
ParentDevicePath
);
//
// Strictly follow the enumeration based on IDE_CONTROLLER_INIT protocol
//
for (IdeChannel = BeginningIdeChannel; IdeChannel <= EndIdeChannel; IdeChannel++) {
IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, IdeChannel);
//
// now obtain channel information fron IdeControllerInit protocol. Step9
//
Status = IdeInit->GetChannelInfo (
IdeInit,
IdeChannel,
&ChannelEnabled,
&MaxDevices
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "[GetChannel, Status=%x]", Status));
continue;
}
if (!ChannelEnabled) {
continue;
}
EndIdeDevice = (UINT8) MIN ((MaxDevices - 1), EndIdeDevice);
ASSERT (EndIdeDevice < IdeMaxDevice);
//
// Now inform the IDE Controller Init Module. Sept10
//
IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelReset, IdeChannel);
//
// No reset channel function implemented. Sept11
//
IdeInit->NotifyPhase (IdeInit, EfiIdeAfterChannelReset, IdeChannel);
//
// Step13
//
IdeInit->NotifyPhase (
IdeInit,
EfiIdeBusBeforeDevicePresenceDetection,
IdeChannel
);
//
// Prepare to detect IDE device of this channel
//
InitializeIDEChannelData ();
//
// -- 1st inner loop --- Master/Slave ------------ Step14
//
for (IdeDevice = BeginningIdeDevice; IdeDevice <= EndIdeDevice; IdeDevice++) {
//
// Check whether the configuration options allow this device
//
if ((ConfigurationOptions & (1 << (IdeChannel * 2 + IdeDevice))) == 0) {
continue;
}
//
// The device has been scanned in another Start(), No need to scan it again
// for perf optimization.
//
if (IdeBusDriverPrivateData->HaveScannedDevice[IdeChannel * 2 + IdeDevice]) {
continue;
}
//
// create child handle for the detected device.
//
IdeBlkIoDevice[IdeChannel][IdeDevice] = AllocatePool (sizeof (IDE_BLK_IO_DEV));
if (IdeBlkIoDevice[IdeChannel][IdeDevice] == NULL) {
continue;
}
IdeBlkIoDevicePtr = IdeBlkIoDevice[IdeChannel][IdeDevice];
ZeroMem (IdeBlkIoDevicePtr, sizeof (IDE_BLK_IO_DEV));
IdeBlkIoDevicePtr->Signature = IDE_BLK_IO_DEV_SIGNATURE;
IdeBlkIoDevicePtr->Channel = (EFI_IDE_CHANNEL) IdeChannel;
IdeBlkIoDevicePtr->Device = (EFI_IDE_DEVICE) IdeDevice;
//
// initialize Block IO interface's Media pointer
//
IdeBlkIoDevicePtr->BlkIo.Media = &IdeBlkIoDevicePtr->BlkMedia;
//
// Initialize IDE IO port addresses, including Command Block registers
// and Control Block registers
//
IdeBlkIoDevicePtr->IoPort = AllocatePool (sizeof (IDE_BASE_REGISTERS));
if (IdeBlkIoDevicePtr->IoPort == NULL) {
continue;
}
ZeroMem (IdeBlkIoDevicePtr->IoPort, sizeof (IDE_BASE_REGISTERS));
CommandBlockBaseAddr = IdeRegsBaseAddr[IdeChannel].CommandBlockBaseAddr;
ControlBlockBaseAddr = IdeRegsBaseAddr[IdeChannel].ControlBlockBaseAddr;
IdeBlkIoDevicePtr->IoPort->Data = CommandBlockBaseAddr;
(*(UINT16 *) &IdeBlkIoDevicePtr->IoPort->Reg1) = (UINT16) (CommandBlockBaseAddr + 0x01);
IdeBlkIoDevicePtr->IoPort->SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);
IdeBlkIoDevicePtr->IoPort->SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);
IdeBlkIoDevicePtr->IoPort->CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);
IdeBlkIoDevicePtr->IoPort->CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);
IdeBlkIoDevicePtr->IoPort->Head = (UINT16) (CommandBlockBaseAddr + 0x06);
(*(UINT16 *) &IdeBlkIoDevicePtr->IoPort->Reg) = (UINT16) (CommandBlockBaseAddr + 0x07);
(*(UINT16 *) &IdeBlkIoDevicePtr->IoPort->Alt) = ControlBlockBaseAddr;
IdeBlkIoDevicePtr->IoPort->DriveAddress = (UINT16) (ControlBlockBaseAddr + 0x01);
IdeBlkIoDevicePtr->IoPort->MasterSlave = (UINT16) ((IdeDevice == IdeMaster) ? 1 : 0);
IdeBlkIoDevicePtr->PciIo = PciIo;
IdeBlkIoDevicePtr->IdeBusDriverPrivateData = IdeBusDriverPrivateData;
IdeBlkIoDevicePtr->IoPort->BusMasterBaseAddr = IdeRegsBaseAddr[IdeChannel].BusMasterBaseAddr;
//
// Report Status code: is about to detect IDE drive
//
REPORT_STATUS_CODE_EX (
EFI_PROGRESS_CODE,
(EFI_IO_BUS_ATA_ATAPI | EFI_P_PC_PRESENCE_DETECT),
0,
&gEfiCallerIdGuid,
NULL,
NULL,
0
);
//
// Discover device, now!
//
PERF_START (NULL, "DiscoverIdeDevice", "IDE", 0);
Status = DiscoverIdeDevice (IdeBlkIoDevicePtr);
PERF_END (NULL, "DiscoverIdeDevice", "IDE", 0);
IdeBusDriverPrivateData->HaveScannedDevice[IdeChannel * 2 + IdeDevice] = TRUE;
IdeBusDriverPrivateData->DeviceProcessed[IdeChannel * 2 + IdeDevice] = FALSE;
if (!EFI_ERROR (Status)) {
//
// Set Device Path
//
ZeroMem (&NewNode, sizeof (NewNode));
NewNode.DevPath.Type = MESSAGING_DEVICE_PATH;
NewNode.DevPath.SubType = MSG_ATAPI_DP;
SetDevicePathNodeLength (&NewNode.DevPath, sizeof (ATAPI_DEVICE_PATH));
NewNode.Atapi.PrimarySecondary = (UINT8) IdeBlkIoDevicePtr->Channel;
NewNode.Atapi.SlaveMaster = (UINT8) IdeBlkIoDevicePtr->Device;
NewNode.Atapi.Lun = IdeBlkIoDevicePtr->Lun;
IdeBlkIoDevicePtr->DevicePath = AppendDevicePathNode (
ParentDevicePath,
&NewNode.DevPath
);
if (IdeBlkIoDevicePtr->DevicePath == NULL) {
ReleaseIdeResources (IdeBlkIoDevicePtr);
continue;
}
//
// Submit identify data to IDE controller init driver
//
CopyMem (&IdentifyData, IdeBlkIoDevicePtr->IdData, sizeof (IdentifyData));
IdeBusDriverPrivateData->DeviceFound[IdeChannel * 2 + IdeDevice] = TRUE;
IdeInit->SubmitData (IdeInit, IdeChannel, IdeDevice, &IdentifyData);
} else {
//
// Device detection failed
//
IdeBusDriverPrivateData->DeviceFound[IdeChannel * 2 + IdeDevice] = FALSE;
IdeInit->SubmitData (IdeInit, IdeChannel, IdeDevice, NULL);
ReleaseIdeResources (IdeBlkIoDevicePtr);
IdeBlkIoDevicePtr = NULL;
}
//
// end of 1st inner loop ---
//
}
//
// end of 1st outer loop =========
//
}
//
// = 2nd outer loop == Primary/Secondary =================
//
for (IdeChannel = BeginningIdeChannel; IdeChannel <= EndIdeChannel; IdeChannel++) {
//
// -- 2nd inner loop --- Master/Slave --------
//
for (IdeDevice = BeginningIdeDevice; IdeDevice <= EndIdeDevice; IdeDevice++) {
ASSERT (IdeChannel * 2 + IdeDevice < MAX_IDE_DEVICE);
if (IdeBusDriverPrivateData->DeviceProcessed[IdeChannel * 2 + IdeDevice]) {
continue;
}
if (!IdeBusDriverPrivateData->DeviceFound[IdeChannel * 2 + IdeDevice]) {
continue;
}
Status = IdeInit->CalculateMode (
IdeInit,
IdeChannel,
IdeDevice,
&SupportedModes
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "[bStStp20S=%x]", Status));
continue;
}
ASSERT (IdeChannel < IdeMaxChannel && IdeDevice < IdeMaxDevice);
IdeBlkIoDevicePtr = IdeBlkIoDevice[IdeChannel][IdeDevice];
//
// Set best supported PIO mode on this IDE device
//
if (SupportedModes->PioMode.Mode <= AtaPioMode2) {
TransferMode.ModeCategory = ATA_MODE_CATEGORY_DEFAULT_PIO;
} else {
TransferMode.ModeCategory = ATA_MODE_CATEGORY_FLOW_PIO;
}
TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);
if (SupportedModes->ExtModeCount == 0){
Status = SetDeviceTransferMode (IdeBlkIoDevicePtr, &TransferMode);
if (EFI_ERROR (Status)) {
IdeBusDriverPrivateData->DeviceFound[IdeChannel * 2 + IdeDevice] = FALSE;
ReleaseIdeResources (IdeBlkIoDevicePtr);
IdeBlkIoDevicePtr = NULL;
continue;
}
}
//
// Set supported DMA mode on this IDE device. Note that UDMA & MDMA cann't
// be set together. Only one DMA mode can be set to a device. If setting
// DMA mode operation fails, we can continue moving on because we only use
// PIO mode at boot time. DMA modes are used by certain kind of OS booting
//
if (SupportedModes->UdmaMode.Valid) {
TransferMode.ModeCategory = ATA_MODE_CATEGORY_UDMA;
TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
Status = SetDeviceTransferMode (IdeBlkIoDevicePtr, &TransferMode);
if (EFI_ERROR (Status)) {
IdeBusDriverPrivateData->DeviceFound[IdeChannel * 2 + IdeDevice] = FALSE;
ReleaseIdeResources (IdeBlkIoDevicePtr);
IdeBlkIoDevicePtr = NULL;
continue;
}
//
// Record Udma Mode
//
IdeBlkIoDevicePtr->UdmaMode.Valid = TRUE;
IdeBlkIoDevicePtr->UdmaMode.Mode = SupportedModes->UdmaMode.Mode;
EnableInterrupt (IdeBlkIoDevicePtr);
} else if (SupportedModes->MultiWordDmaMode.Valid) {
TransferMode.ModeCategory = ATA_MODE_CATEGORY_MDMA;
TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
Status = SetDeviceTransferMode (IdeBlkIoDevicePtr, &TransferMode);
if (EFI_ERROR (Status)) {
IdeBusDriverPrivateData->DeviceFound[IdeChannel * 2 + IdeDevice] = FALSE;
ReleaseIdeResources (IdeBlkIoDevicePtr);
IdeBlkIoDevicePtr = NULL;
continue;
}
EnableInterrupt (IdeBlkIoDevicePtr);
}
//
// Init driver parameters
//
DriveParameters.Sector = (UINT8) ((ATA5_IDENTIFY_DATA *) IdeBlkIoDevicePtr->IdData)->sectors_per_track;
DriveParameters.Heads = (UINT8) (((ATA5_IDENTIFY_DATA *) IdeBlkIoDevicePtr->IdData)->heads - 1);
DriveParameters.MultipleSector = (UINT8) IdeBlkIoDevicePtr->IdData->AtaData.multi_sector_cmd_max_sct_cnt;
//
// Set Parameters for the device:
// 1) Init
// 2) Establish the block count for READ/WRITE MULTIPLE (EXT) command
//
if ((IdeBlkIoDevicePtr->Type == IdeHardDisk) || (IdeBlkIoDevicePtr->Type == Ide48bitAddressingHardDisk)) {
Status = SetDriveParameters (IdeBlkIoDevicePtr, &DriveParameters);
}
//
// Record PIO mode used in private data
//
IdeBlkIoDevicePtr->PioMode = (ATA_PIO_MODE) SupportedModes->PioMode.Mode;
//
// Set IDE controller Timing Blocks in the PCI Configuration Space
//
IdeInit->SetTiming (IdeInit, IdeChannel, IdeDevice, SupportedModes);
//
// Add Component Name for the IDE/ATAPI device that was discovered.
//
IdeBlkIoDevicePtr->ControllerNameTable = NULL;
ADD_IDE_ATAPI_NAME (IdeBlkIoDevicePtr);
Status = gBS->InstallMultipleProtocolInterfaces (
&IdeBlkIoDevicePtr->Handle,
&gEfiDevicePathProtocolGuid,
IdeBlkIoDevicePtr->DevicePath,
&gEfiBlockIoProtocolGuid,
&IdeBlkIoDevicePtr->BlkIo,
&gEfiDiskInfoProtocolGuid,
&IdeBlkIoDevicePtr->DiskInfo,
NULL
);
if (EFI_ERROR (Status)) {
ReleaseIdeResources (IdeBlkIoDevicePtr);
}
gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
(VOID **) &PciIo,
This->DriverBindingHandle,
IdeBlkIoDevicePtr->Handle,
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
);
IdeBusDriverPrivateData->DeviceProcessed[IdeChannel * 2 + IdeDevice] = TRUE;
//
// Report status code: device eanbled!
//
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
EFI_PROGRESS_CODE,
(EFI_IO_BUS_ATA_ATAPI | EFI_P_PC_ENABLE),
IdeBlkIoDevicePtr->DevicePath
);
//
// Create event to clear pending IDE interrupt
//
Status = gBS->CreateEventEx (
EVT_NOTIFY_SIGNAL,
TPL_NOTIFY,
ClearInterrupt,
IdeBlkIoDevicePtr,
&gEfiEventExitBootServicesGuid,
&IdeBlkIoDevicePtr->ExitBootServiceEvent
);
//
// end of 2nd inner loop ----
//
}
//
// end of 2nd outer loop ==========
//
}
//
// All configurations done! Notify IdeController to do post initialization
// work such as saving IDE controller PCI settings for S3 resume
//
IdeInit->NotifyPhase (IdeInit, EfiIdeBusPhaseMaximum, 0);
if (SupportedModes != NULL) {
FreePool (SupportedModes);
}
PERF_START (NULL, "Finish IDE detection", "IDE", 1);
PERF_END (NULL, "Finish IDE detection", "IDE", 0);
return EFI_SUCCESS;
ErrorExit:
//
// Report error code: controller error
//
REPORT_STATUS_CODE_WITH_DEVICE_PATH (
EFI_ERROR_CODE | EFI_ERROR_MINOR,
(EFI_IO_BUS_ATA_ATAPI | EFI_IOB_EC_CONTROLLER_ERROR),
ParentDevicePath
);
gBS->CloseProtocol (
Controller,
&gEfiIdeControllerInitProtocolGuid,
This->DriverBindingHandle,
Controller
);
gBS->UninstallMultipleProtocolInterfaces (
Controller,
&gEfiCallerIdGuid,
IdeBusDriverPrivateData,
NULL
);
if (IdeBusDriverPrivateData != NULL) {
gBS->FreePool (IdeBusDriverPrivateData);
}
if (SupportedModes != NULL) {
gBS->FreePool (SupportedModes);
}
gBS->CloseProtocol (
Controller,
&gEfiPciIoProtocolGuid,
This->DriverBindingHandle,
Controller
);
gBS->CloseProtocol (
Controller,
&gEfiDevicePathProtocolGuid,
This->DriverBindingHandle,
Controller
);
return Status;
}
int USBTesting()
{
UINT ch; // channel number
UINT TX_Status;
CHAR *dma_src_addr;
char Continue_test = 1;
//cyli++ 01/17/07
if (IS_16_ENDPT()) {
printf("16 end-points\n");
} else if (IS_10_ENDPT()) {
printf("10 end-points\n");
} else if (IS_4_ENDPT()) {
printf("4 end-points\n");
} else {
printf("Error end-point number!\n");
printf("DEV_INFO = 0x%08x", readw(UDC_DEVINFO) & ENDPT_NUM_MASK);
}
// CY+ to fix program reload Socle phy hang up problem
#ifdef UDC_SOCLE_PHY
ASSERT_SOFT_POR();
#if 0
isr_time_value = 0;
isr_waiting_time = 1;
setup_1ms_timer(1);
#else
MSDELAY(1);
#endif
while (isr_time_value != isr_waiting_time);
DEASSERT_SOFT_POR();
#endif
#ifdef UDC_SOCLE_PHY
#if 0
isr_time_value = 0;
isr_waiting_time = 8;
setup_1ms_timer(8);
#else
MSDELAY(8);
#endif
while (isr_time_value != isr_waiting_time);
// SET_PHY_16_BIT();
#endif
ResetFlag = 0;
bIsConnected = VBUS_OK();
// if (bIsConnected)
// printf(" -> USB VBus connect\n");
// else
// printf(" -> USB VBus disconnect");
// enable interrupt
INT0_ENABLE(LDK_INTC_UDC);
// setup interrupt handler
connectInterrupt( LDK_INTC_UDC, UDCIintHandler, NULL);
INT0_SET_MASK(LDK_INTC_UDC);
while (1) {
// ;printf("\n USB cable disconnected!\n");
SOFT_DISCONNECT();
// wait for plugin stable on vbus
// printf("\nWait for USB Host connect...");
// while ( !bIsConnected );
//CY++ for checking USB Host connect waiting
int wait=0;
while ( !bIsConnected ){
MSDELAY(60);
printf("%4d", wait);
wait++;
if(wait > 100)
return USB_NO_CONNECT_ERROR;
printf("\b\b\b\b");
}
#ifdef UDC_SOCLE_PHY
ASSERT_SOFT_POR();
#if 0
isr_time_value = 0;
isr_waiting_time = 1;
setup_1ms_timer(1);
#else
MSDELAY(1);
#endif
while (isr_time_value != isr_waiting_time);
DEASSERT_SOFT_POR();
#endif
#ifdef UDC_SOCLE_PHY
#if 0
isr_time_value = 0;
isr_waiting_time = 8;
setup_1ms_timer(8);
#else
MSDELAY(8);
#endif
while (isr_time_value != isr_waiting_time);
// SET_PHY_16_BIT();
#endif
initUDCController(); // initialize UDC Controller
initUDCTestingEnv(); // initialize UDC testing environment
SOFT_CONNECT();
;//printf("\n USB cable connected!\n");
uNeedDoProcCtrlBlockNum = 0;
while ( bIsConnected ) {
// check ENP 0 transmit request
if ( uNeedDoProcCtrlBlockNum > 0 ) {
int dma_size;
// dma done now, polling for empty data set
if (!( readw(UDC_TX0BUF) & TxFULL)) {
// critical section
DisableInterrupt();
uNeedDoProcCtrlBlockNum--;
dma_src_addr = CtrlInBuffer + uCurrentCtrlBlockNum++ * uCurrentCtrlPacketSize;
if ( uControlDataSize > uCurrentCtrlPacketSize ) {
dma_size = uCurrentCtrlPacketSize;
}
else {
dma_size = uControlDataSize;
}
// calculate remaining bytes need transfer
uControlDataSize -= dma_size;
writew( dma_size, UDC_TX0STAT );
writew( virt_to_phy((u32_t)dma_src_addr) , UDC_DMA0LM_IADDR );
writew( ENP_DMA_START , UDC_DMA0CTLI );
EnableInterrupt();
// set ACK--after we have overwritten the previously incorrect data
writew( readw( UDC_TX0CON ) & ~TxNAK, UDC_TX0CON );
}
}
if (Continue_test){
printf("Done\n");
printf("USB initialize...Done\n");
printf("HandShaking...Done\n");
printf("Waiting for Bulk Read/Write test...\n");
printf("Remove Socle USB Bulk device Hardware from Windows and USB cable to Exit !!!\n");
Continue_test = 0;
}
// check channel group transmit request
for (ch = 0; ch < NUM_OF_USB_CHANNEL; ch++) {
// check each Bulk_IN End Point transmit request
if ( ChannelSet[ch].uLoopbackCount > 0 ) {
if (ChannelSet[ch].bBulkDMAOnGoing == false) {
// check buffer is available for transmit data
TX_Status = readw(UDC_TXBUF(ChannelSet[ch].uBulk_IN)); // get buffer status
if ((TX_Status & TxFULL) == 0) {
#if 0
if ((TX_Status & TxDS0) == 0)
DEBUG_OUT('0');
if ((TX_Status & TxDS1) == 0)
DEBUG_OUT('1');
#endif
//DEBUG_OUT('i');
// enter critical section, protect share variable
DisableInterrupt();
//DEBUG_OUT('+');
ChannelSet[ch].uLoopbackCount--;
// get transmit buffer address & move buffer to next position
dma_src_addr = ChannelSet[ch].pBulkInBuffer + ChannelSet[ch].uCurrentBulkInBlockNum * uBulkBlockSize;
// setup DMA
writew( ChannelSet[ch].sBulkBlockSizeBuffer[ChannelSet[ch].uCurrentBulkInBlockNum],
UDC_TXSTAT(ChannelSet[ch].uBulk_IN) ); // write transmit count
writew( virt_to_phy((u32_t)dma_src_addr), // set transmit buffer pointer
UDC_DMALM_IADDR(ChannelSet[ch].uBulk_IN) );
writew( ENP_DMA_START , UDC_DMACTRLI(ChannelSet[ch].uBulk_IN) ); // start transmit DMA
// move to next buffer
ChannelSet[ch].uCurrentBulkInBlockNum = ++ChannelSet[ch].uCurrentBulkInBlockNum % uMaxBlockNumber;
#if 0
WAIT_DMA_DONE(UDC_TXSTAT(ChannelSet[ch].uBulk_IN));
#endif
#if 0
for (delay = 0; delay < 1000; delay++) {
TX2_DMAOnGoing = true;
}
#endif
ChannelSet[ch].bBulkDMAOnGoing = true;
//DEBUG_OUT('-');
EnableInterrupt();
// leave critical section
}
}
}
// check each Intr_IN End Point transmit request
if ( ChannelSet[ch].uIntrINCount > 0 ) {
// if (!( readw(UDC_TXBUF(ChannelSet[ch].uIntr_IN)) & TxFULL)) {
if (ChannelSet[ch].bIntrDMAOnGoing == false) {
// critical section
DisableInterrupt();
ChannelSet[ch].uCurrentIntrInBlockNum--;
dma_src_addr = ChannelSet[ch].pIntrInBuffer + ChannelSet[ch].uCurrentIntrInBlockNum * INTR_BLOCK_SIZE;
EnableInterrupt();
writew( INTR_BLOCK_SIZE, UDC_TXSTAT(ChannelSet[ch].uIntr_IN) );
writew( virt_to_phy((u32_t)dma_src_addr), UDC_DMALM_IADDR(ChannelSet[ch].uIntr_IN) );
writew( ENP_DMA_START, UDC_DMACTRLI(ChannelSet[ch].uIntr_IN) );
ChannelSet[ch].bIntrDMAOnGoing = true;
#if 0
WAIT_DMA_DONE(UDC_DMACTRLI(ChannelSet[ch].uIntr_IN) );
#endif
ChannelSet[ch].uCurrentBulkInBlockNum = ++ChannelSet[ch].uCurrentBulkInBlockNum % MAX_INTR_NUM;
}
}
}
}
// CY+ for disconnect detect and exit testing program
printf ("USB Host disconnected !!!\n");
printf ("Press Y to continue and any other Key to exit? ");
char i;
i=getchar();
if((i!='Y')&&(i!='y'))
{
printf ("\n");
return UPF_TEST_SUCCESS;
}
else
Continue_test = 1;
}
// leave usb test now, should never been here
return USB_UNKONW_ERROR;
}
void FlashOperation(UINT32 op, void* addr, UINT32 data32)
{
//UINT32 status;
// NVMADDR only accept Physical Address
NVMADDR = ConvertToPhysicalAddress(addr);
#if 0 && defined(DEBUG)
SerialPrint("FlashOperation / ");
if (op == FLASH_WORD_WRITE)
{
SerialPrint("Write Address 0x");
SerialPrintNumber(NVMADDR,16);
SerialPrint("\r\n");
mLED_1_Toggle();
}
if (op == FLASH_PAGE_ERASE)
{
SerialPrint("Erase Address 0x");
SerialPrintNumber(NVMADDR,16);
SerialPrint("\r\n");
mLED_2_Toggle();
}
#endif
// Load data into NVMDATA register
NVMDATA = data32;
// Suspend or Disable all Interrupts
//status = DisableInterrupt();
// Enable Flash Write/Erase Operations
// 1-Select Flash operation to perform
// Enable writes to WR bit and LVD circuit
NVMCON = _NVMCON_WREN_MASK | op;
// 2-Wait for LVD to become stable (at least 6us).
Delayus(7);
// 3-Write unlock sequence before the WR bit is set
NVMKEY = 0xAA996655;
NVMKEY = 0x556699AA;
// 4-Start the operation (WR=1)
NVMCONSET = _NVMCON_WR_MASK;
// 5-Wait for operation to complete (WR=0)
while (NVMCON & _NVMCON_WR_MASK);
// 6-Disable Flash Write/Erase operations
NVMCONCLR = _NVMCON_WREN_MASK;
// Restore Interrupts if necessary
#if 0
if (status & 1)
{
EnableInterrupt();
}
else
DisableInterrupt();
#endif
#if 0
// Return NVMERR and LVDERR Error Status Bits
if (NVMCON & (_NVMCON_WRERR_MASK | _NVMCON_LVDERR_MASK))
{
while (1)
{
mLED_2_Toggle();
DelayUs(500);
}
}
#endif
}
