/* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
MEM_DATA_STRUCT *MemData = ConfigPtr;
printk(BIOS_INFO, "Setting DDR3 voltage: ");
FCH_IOMUX(65) = 1; // GPIO65: VMEM_LV_EN# lowers VMEM from 1.5 to 1.35V
switch (MemData->ParameterListPtr->DDR3Voltage) {
case VOLT1_25: // board is not able to provide this
MemData->ParameterListPtr->DDR3Voltage = VOLT1_35; // sorry
printk(BIOS_INFO, "can't provide 1.25 V, using ");
// fall through
default: // AGESA.h says in mixed case 1.5V DIMMs get excluded
case VOLT1_35:
FCH_GPIO(65) = 0x08; // = output, disable PU, set to 0
printk(BIOS_INFO, "1.35 V\n");
break;
case VOLT1_5:
FCH_GPIO(65) = 0xC8; // = output, disable PU, set to 1
printk(BIOS_INFO, "1.5 V\n");
}
return AGESA_SUCCESS;
}
static void init(struct device *dev)
{
volatile u8 *spi_base; // base addr of Hudson's SPI host controller
int i;
printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
/* Init Hudson GPIOs. */
printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed
FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS#
FCH_GPIO (197) = 0x28; // = input, disable int. pull-up
FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0
FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups
FCH_IOMUX( 57) = 1;
FCH_GPIO ( 57) = 0x28;
FCH_IOMUX( 58) = 1;
FCH_GPIO ( 58) = 0x28;
FCH_IOMUX(187) = 2; // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector
FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0
FCH_IOMUX(188) = 2;
FCH_GPIO (188) = 0x08;
FCH_IOMUX(166) = 2;
FCH_GPIO (166) = 0x08;
// needed to make GPO160 work (Hudson Register Reference section 2.3.6.1)
FCH_PMIO(0xDC) &= ~0x80; FCH_PMIO(0xE6) = (FCH_PMIO(0xE6) & ~0x02) | 0x01;
FCH_IOMUX(160) = 1;
FCH_GPIO (160) = 0x08;
FCH_IOMUX(189) = 1; // GPIO189-192: GPI0-3 on COM Express connector
FCH_IOMUX(190) = 1; // default to inputs with int. PU
FCH_IOMUX(191) = 1;
FCH_IOMUX(192) = 1;
if (!fch_gpio_state(197)) // just in case anyone cares
printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
printk(BIOS_INFO, "Board revision ID: %u\n",
fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
spi_base = (u8*)(pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0xA0) & 0xFFFFFFE0);
spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register
/* Notify the SMC we're alive and kicking, or after a while it will
* effect a power cycle and switch to the alternate BIOS chip.
* Should be done as late as possible. */
printk(BIOS_INFO, "Sending BIOS alive message\n");
const u8 i_am_alive[] = { 0x03 }; //bit2=SEL_DP0: 0=DDI2, 1=LVDS
if ((i = smb_write_blk(0x50, 0x25, sizeof(i_am_alive), i_am_alive)))
printk(BIOS_ERR, "smb_write_blk failed: %d\n", i);
printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__);
}
static void init(struct device *dev)
{
volatile u8 *spi_base; // base addr of Hudson's SPI host controller
int i;
printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
/* Init Hudson GPIOs. */
printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed
FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# = input (int. PU)
FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0
FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups
FCH_IOMUX( 57) = 1;
FCH_GPIO ( 57) = 0x28;
FCH_IOMUX( 58) = 1;
FCH_GPIO ( 58) = 0x28;
FCH_IOMUX( 96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU)
FCH_IOMUX( 52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector
FCH_IOMUX( 61) = 2; // default to inputs with int. PU
FCH_IOMUX( 62) = 2;
FCH_IOMUX(187) = 2;
FCH_IOMUX(188) = 2;
FCH_IOMUX(189) = 1;
FCH_IOMUX(190) = 1;
FCH_IOMUX(191) = 1;
FCH_IOMUX(192) = 1;
if (!fch_gpio_state(197)) // just in case anyone cares
printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
printk(BIOS_INFO, "Board revision ID: %u\n",
fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
/* Init SIO GPIOs. */
printk(BIOS_DEBUG, "Init SIO GPIOs @ 0x%04x\n", SIO_RUNTIME_BASE);
for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
u16 val = sio_init_table[i];
outb((u8)val, SIO_RUNTIME_BASE + (val >> 8));
}
/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
spi_base = (u8*)((uintptr_t)pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0xA0) & 0xFFFFFFE0);
spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register
/* Notify the SMC we're alive and kicking, or after a while it will
* effect a power cycle and switch to the alternate BIOS chip.
* Should be done as late as possible. */
printk(BIOS_INFO, "Sending BIOS alive message\n");
const u8 i_am_alive[] = { 0x03 };
if ((i = smb_write_blk(0x50, 0x25, sizeof(i_am_alive), i_am_alive)))
printk(BIOS_ERR, "smb_write_blk failed: %d\n", i);
printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__);
}
static void init(struct device *dev)
{
volatile u8 *spi_base; // base addr of Hudson's SPI host controller
printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
/* Init Hudson GPIOs. */
printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed
FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS#
FCH_GPIO (197) = 0x28; // = input, disable int. pull-up
FCH_IOMUX(56) = 1; // GPIO58-56: REV_ID2-0
FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups
FCH_IOMUX(57) = 1;
FCH_GPIO (57) = 0x28;
FCH_IOMUX(58) = 1;
FCH_GPIO (58) = 0x28;
FCH_IOMUX(187) = 2; // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector
FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0
FCH_IOMUX(188) = 2;
FCH_GPIO (188) = 0x08;
FCH_IOMUX(166) = 2;
FCH_GPIO (166) = 0x08;
// needed to make GPO160 work (Hudson Register Reference section 2.3.6.1)
FCH_PMIO(0xDC) &= ~0x80; FCH_PMIO(0xE6) = (FCH_PMIO(0xE6) & ~0x02) | 0x01;
FCH_IOMUX(160) = 1;
FCH_GPIO (160) = 0x08;
FCH_IOMUX(189) = 1; // GPIO189-192: GPI0-3 on COM Express connector
FCH_IOMUX(190) = 1; // default to inputs with int. PU
FCH_IOMUX(191) = 1;
FCH_IOMUX(192) = 1;
if (!fch_gpio_state(197)) // just in case anyone cares
printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
printk(BIOS_INFO, "Board revision ID: %u\n",
fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3),
0xA0) & 0xFFFFFFE0);
spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register
/* Notify the SMC we're alive and kicking, or after a while it will
* effect a power cycle and switch to the alternate BIOS chip.
* Should be done as late as possible.
* Failure here does not matter if watchdog was already disabled,
* by configuration or previous boot, so ignore return value.
*/
sema_send_alive();
printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__);
}