/*---------------------------------------------------------------------------*/
int
cc2420_init(void)
{
uint16_t reg;
{
int s = splhigh();
cc2420_arch_init(); /* Initalize ports and SPI. */
DISABLE_FIFOP_INT();
FIFOP_INT_INIT();
splx(s);
}
/* Turn on voltage regulator and reset. */
SET_VREG_ACTIVE();
//clock_delay(250); OK
SET_RESET_ACTIVE();
clock_delay(127);
SET_RESET_INACTIVE();
//clock_delay(125); OK
/* Turn on the crystal oscillator. */
strobe(CC2420_SXOSCON);
/* Turn on/off automatic packet acknowledgment and address decoding. */
reg = getreg(CC2420_MDMCTRL0);
reg |= 0x40; /* XXX CCA mode 1 */
#if CC2420_CONF_AUTOACK
reg |= AUTOACK | ADR_DECODE;
#else
reg &= ~(AUTOACK | ADR_DECODE);
#endif /* CC2420_CONF_AUTOACK */
setreg(CC2420_MDMCTRL0, reg);
/* Change default values as recomended in the data sheet, */
/* correlation threshold = 20, RX bandpass filter = 1.3uA. */
setreg(CC2420_MDMCTRL1, CORR_THR(20));
reg = getreg(CC2420_RXCTRL1);
reg |= RXBPF_LOCUR;
setreg(CC2420_RXCTRL1, reg);
/* Set the FIFOP threshold to maximum. */
setreg(CC2420_IOCFG0, FIFOP_THR(127));
/* Turn off "Security enable" (page 32). */
reg = getreg(CC2420_SECCTRL0);
reg &= ~RXFIFO_PROTECTION;
setreg(CC2420_SECCTRL0, reg);
cc2420_set_pan_addr(0xffff, 0x0000, NULL);
cc2420_set_channel(26);
process_start(&cc2420_process, NULL);
return 1;
}
void
cc2420_init(void)
{
u16_t reg;
{
int s = splhigh();
__cc2420_arch_init(); /* Initalize ports and SPI. */
DISABLE_FIFOP_INT();
FIFOP_INT_INIT();
splx(s);
}
/* Turn on voltage regulator and reset. */
SET_VREG_ACTIVE();
//clock_delay(250); OK
SET_RESET_ACTIVE();
clock_delay(127);
SET_RESET_INACTIVE();
//clock_delay(125); OK
/* Turn on the crystal oscillator. */
cc2420_strobe(CC2420_SXOSCON);
/* Turn on automatic packet acknowledgment. */
reg = cc2420_getreg(CC2420_MDMCTRL0);
reg |= AUTOACK;
cc2420_setreg(CC2420_MDMCTRL0, reg);
/* Change default values as recomended in the data sheet, */
/* correlation threshold = 20, RX bandpass filter = 1.3uA. */
cc2420_setreg(CC2420_MDMCTRL1, CORR_THR(20));
reg = cc2420_getreg(CC2420_RXCTRL1);
reg |= RXBPF_LOCUR;
cc2420_setreg(CC2420_RXCTRL1, reg);
/* Set the FIFOP threshold to maximum. */
cc2420_setreg(CC2420_IOCFG0, FIFOP_THR(127));
/* Turn off "Security enable" (page 32). */
reg = cc2420_getreg(CC2420_SECCTRL0);
reg &= ~RXFIFO_PROTECTION;
cc2420_setreg(CC2420_SECCTRL0, reg);
cc2420_set_chan_pan_addr(11, 0xffff, 0x0000, NULL);
}
//-------------------------------------------------------------------------------------------------------
// void rf_rx_on(void)
//
// DESCRIPTION:
// Enables the CC2420 receiver and the FIFOP interrupt. When a packet is received through this
// interrupt, it will call rf_rx_callback(...), which must be defined by the application
//-------------------------------------------------------------------------------------------------------
void rf_rx_on(void) {
#ifdef RADIO_PRIORITY_CEILING
nrk_sem_pend (radio_sem);
#endif
rfSettings.receiveOn = TRUE;
#ifdef CC2420_OSC_OPT
FASTSPI_STROBE(CC2420_SXOSCON);
nrk_spin_wait_us(OSC_STARTUP_DELAY);
#endif
FASTSPI_STROBE(CC2420_SRXON);
FASTSPI_STROBE(CC2420_SFLUSHRX);
rx_ready=0;
#ifdef RADIO_PRIORITY_CEILING
nrk_sem_post(radio_sem);
#endif
FIFOP_INT_INIT();
ENABLE_FIFOP_INT();
} // rf_rx_on()
