static void prvSetupHardware( void )
{
/* Configuration taken from the ST code.
Set Flash banks size & address */
FMI_BankRemapConfig( 4, 2, 0, 0x80000 );
/* FMI Waite States */
FMI_Config( FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH );
/* Configure the FPLL = 96MHz, and APB to 48MHz. */
SCU_PCLKDivisorConfig( SCU_PCLK_Div2 );
SCU_PLLFactorsConfig( 192, 25, 2 );
SCU_PLLCmd( ENABLE );
SCU_MCLKSourceConfig( SCU_MCLK_PLL );
WDG_Cmd( DISABLE );
VIC_DeInit();
/* GPIO8 clock source enable, used by the LCD. */
SCU_APBPeriphClockConfig(__GPIO8, ENABLE);
GPIO_DeInit(GPIO8);
/* GPIO 9 clock source enable, used by the LCD. */
SCU_APBPeriphClockConfig(__GPIO9, ENABLE);
GPIO_DeInit(GPIO9);
/* Enable VIC clock */
SCU_AHBPeriphClockConfig(__VIC, ENABLE);
SCU_AHBPeriphReset(__VIC, DISABLE);
/* Peripheral initialisation. */
vParTestInitialise();
}
void systemInit(void)
{
//Default configuration
SCU_MCLKSourceConfig(SCU_MCLK_OSC);
//Configure the FMI
FMI_Config(FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0,
FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH);
//Configure PLL factors
SCU_PLLFactorsConfig(192, 25, 2);
//Enable PLL and wait for the the PLL to lock
SCU_PLLCmd(ENABLE);
//Set clock dividers
SCU_RCLKDivisorConfig(SCU_RCLK_Div1);
SCU_HCLKDivisorConfig(SCU_HCLK_Div1);
SCU_FMICLKDivisorConfig(SCU_FMICLK_Div1);
SCU_PCLKDivisorConfig(SCU_PCLK_Div2);
//Switch to PLL clock
SCU_MCLKSourceConfig(SCU_MCLK_PLL);
//Enable VIC clock
SCU_AHBPeriphClockConfig(__VIC, ENABLE);
//Reset VIC peripheral
VIC_DeInit();
//Assign default vectors
VIC_InitDefaultVectors();
}
