static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
{
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
struct ftgmac100_data *priv = dev->priv;
struct ftgmac100_txdes *txdes;
struct ftgmac100_rxdes *rxdes;
unsigned int maccr;
void *buf;
int i;
debug("%s()\n", __func__);
if (!priv->txdes) {
txdes = dma_alloc_coherent(
sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
if (!txdes)
panic("ftgmac100: out of memory\n");
memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
priv->txdes = txdes;
}
txdes = priv->txdes;
if (!priv->rxdes) {
rxdes = dma_alloc_coherent(
sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
if (!rxdes)
panic("ftgmac100: out of memory\n");
memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
priv->rxdes = rxdes;
}
rxdes = priv->rxdes;
/* set the ethernet address */
ftgmac100_set_mac_from_env(dev);
/* disable all interrupts */
writel(0, &ftgmac100->ier);
/* initialize descriptors */
priv->tx_index = 0;
priv->rx_index = 0;
txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
for (i = 0; i < PKTBUFSTX; i++) {
/* TXBUF_BADR */
if (!txdes[i].txdes2) {
buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
if (!buf)
panic("ftgmac100: out of memory\n");
txdes[i].txdes3 = virt_to_phys(buf);
txdes[i].txdes2 = (uint)buf;
}
txdes[i].txdes1 = 0;
}
for (i = 0; i < PKTBUFSRX; i++) {
/* RXBUF_BADR */
if (!rxdes[i].rxdes2) {
buf = net_rx_packets[i];
rxdes[i].rxdes3 = virt_to_phys(buf);
rxdes[i].rxdes2 = (uint)buf;
}
rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
}
/* transmit ring */
writel(priv->txdes_dma, &ftgmac100->txr_badr);
/* receive ring */
writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
/* poll receive descriptor automatically */
writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
/* config receive buffer size register */
writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr);
/* enable transmitter, receiver */
maccr = FTGMAC100_MACCR_TXMAC_EN |
FTGMAC100_MACCR_RXMAC_EN |
FTGMAC100_MACCR_TXDMA_EN |
FTGMAC100_MACCR_RXDMA_EN |
FTGMAC100_MACCR_CRC_APD |
FTGMAC100_MACCR_FULLDUP |
FTGMAC100_MACCR_RX_RUNT |
FTGMAC100_MACCR_RX_BROADPKT;
writel(maccr, &ftgmac100->maccr);
if (!ftgmac100_phy_init(dev)) {
if (!ftgmac100_update_link_speed(dev))
return -1;
}
return 0;
}
static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
unsigned int size)
{
size = FTGMAC100_RBSR_SIZE(size);
iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
}
static int ftgmac100_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_platdata(dev);
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
struct phy_device *phydev = priv->phydev;
unsigned int maccr;
ulong start, end;
int ret;
int i;
debug("%s()\n", __func__);
ftgmac100_reset(priv);
/* set the ethernet address */
ftgmac100_set_mac(priv, plat->enetaddr);
/* disable all interrupts */
writel(0, &ftgmac100->ier);
/* initialize descriptors */
priv->tx_index = 0;
priv->rx_index = 0;
for (i = 0; i < PKTBUFSTX; i++) {
priv->txdes[i].txdes3 = 0;
priv->txdes[i].txdes0 = 0;
}
priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
start = (ulong)&priv->txdes[0];
end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
for (i = 0; i < PKTBUFSRX; i++) {
priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
priv->rxdes[i].rxdes0 = 0;
}
priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
start = (ulong)&priv->rxdes[0];
end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
/* transmit ring */
writel((u32)priv->txdes, &ftgmac100->txr_badr);
/* receive ring */
writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
/* poll receive descriptor automatically */
writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
/* config receive buffer size register */
writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
/* enable transmitter, receiver */
maccr = FTGMAC100_MACCR_TXMAC_EN |
FTGMAC100_MACCR_RXMAC_EN |
FTGMAC100_MACCR_TXDMA_EN |
FTGMAC100_MACCR_RXDMA_EN |
FTGMAC100_MACCR_CRC_APD |
FTGMAC100_MACCR_FULLDUP |
FTGMAC100_MACCR_RX_RUNT |
FTGMAC100_MACCR_RX_BROADPKT;
writel(maccr, &ftgmac100->maccr);
ret = phy_startup(phydev);
if (ret) {
dev_err(phydev->dev, "Could not start PHY\n");
return ret;
}
ret = ftgmac100_phy_adjust_link(priv);
if (ret) {
dev_err(phydev->dev, "Could not adjust link\n");
return ret;
}
printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
return 0;
}
