/*FUNCTION**********************************************************************
*
* Function Name : FTM_DRV_CounterStop
* Description : Stops the FTM counter.
*
*END**************************************************************************/
void FTM_DRV_CounterStop(uint32_t instance)
{
/* Stop the FTM counter */
FTM_HAL_SetClockSource(g_ftmBase[instance], kClock_source_FTM_None);
FTM_HAL_SetCpwms(g_ftmBase[instance], 0);
/* Disable the overflow interrupt */
FTM_DRV_SetTimeOverflowIntCmd(instance, false);
}
/*FUNCTION**********************************************************************
*
* Function Name : FTM_DRV_CounterStart
* Description : Starts the FTM counter. This function provides access to the
* FTM counter. The counter can be run in Up-counting and Up-down counting modes.
* To run the counter in Free running mode, choose Up-counting option and provide
* 0x0 for the countStartVal and 0xFFFF for countFinalVal.
*
*END**************************************************************************/
void FTM_DRV_CounterStart(uint32_t instance, ftm_counting_mode_t countMode, uint32_t countStartVal,
uint32_t countFinalVal, bool enableOverflowInt)
{
assert(instance < FTM_INSTANCE_COUNT);
FTM_Type *ftmBase = g_ftmBase[instance];
uint32_t channel = 0;
/* Clear the overflow flag */
FTM_HAL_ClearTimerOverflow(ftmBase);
FTM_HAL_SetCounterInitVal(ftmBase, countStartVal);
FTM_HAL_SetMod(ftmBase, countFinalVal);
FTM_HAL_SetCounter(ftmBase, 0);
/* Use FTM as counter, disable all the channels */
for (channel = 0; channel < g_ftmChannelCount[instance]; channel++)
{
FTM_HAL_SetChnEdgeLevel(ftmBase, channel, 0);
}
if (countMode == kCounting_FTM_UP)
{
FTM_HAL_SetQuadDecoderCmd(ftmBase, false);
FTM_HAL_SetCpwms(ftmBase, 0);
}
else if (countMode == kCounting_FTM_UpDown)
{
FTM_HAL_SetQuadDecoderCmd(ftmBase, false);
FTM_HAL_SetCpwms(ftmBase, 1);
}
/* Activate interrupts if required */
FTM_DRV_SetTimeOverflowIntCmd(instance, enableOverflowInt);
/* Set clock source to start the counter */
FTM_HAL_SetClockSource(ftmBase, s_ftmClockSource);
}
void FTM_DRV_CounterStart(uint8_t instance, ftm_counting_mode_t countMode, uint32_t countStartVal,
uint32_t countFinalVal, bool enableOverflowInt)
{
assert(instance < HW_FTM_INSTANCE_COUNT);
uint32_t ftmBaseAddr = g_ftmBaseAddr[instance];
uint32_t channel = 0;
/* Clear the overflow flag */
FTM_HAL_ClearTimerOverflow(ftmBaseAddr);
FTM_HAL_SetCounterInitVal(ftmBaseAddr, countStartVal);
FTM_HAL_SetMod(ftmBaseAddr, countFinalVal);
FTM_HAL_SetCounter(ftmBaseAddr, 0);
/* Use FTM as counter, disable all the channels */
for (channel = 0; channel < FSL_FEATURE_FTM_CHANNEL_COUNTn(instance); channel++)
{
FTM_HAL_SetChnEdgeLevel(ftmBaseAddr, channel, 0);
}
if (countMode == kCounting_FTM_UP)
{
FTM_HAL_SetQuadDecoderCmd(ftmBaseAddr, false);
FTM_HAL_SetCpwms(ftmBaseAddr, 0);
}
else if (countMode == kCounting_FTM_UpDown)
{
FTM_HAL_SetQuadDecoderCmd(ftmBaseAddr, false);
FTM_HAL_SetCpwms(ftmBaseAddr, 1);
}
/* Activate interrupts if required */
FTM_DRV_SetTimeOverflowIntCmd(instance, enableOverflowInt);
/* Set clock source to start the counter */
FTM_HAL_SetClockSource(ftmBaseAddr, kClock_source_FTM_SystemClk);
}
