void reset_cpu(ulong ignored) { disable_interrupts(); FW_NandDeInit(); #ifndef CONFIG_SYS_L2CACHE_OFF v7_outer_cache_disable(); #endif #ifndef CONFIG_SYS_DCACHE_OFF flush_dcache_all(); #endif #ifndef CONFIG_SYS_ICACHE_OFF invalidate_icache_all(); #endif #ifndef CONFIG_SYS_DCACHE_OFF dcache_disable(); #endif #ifndef CONFIG_SYS_ICACHE_OFF icache_disable(); #endif #if defined(CONFIG_RKCHIP_RK3288) /* pll enter slow mode */ writel(PLL_MODE_SLOW(APLL_ID) | PLL_MODE_SLOW(GPLL_ID) | PLL_MODE_SLOW(CPLL_ID) | PLL_MODE_SLOW(NPLL_ID), RKIO_GRF_PHYS + CRU_MODE_CON); /* soft reset */ writel(0xeca8, RKIO_CRU_PHYS + CRU_GLB_SRST_SND); #elif defined(CONFIG_RKCHIP_RK3036) /* pll enter slow mode */ writel(PLL_MODE_SLOW(APLL_ID) | PLL_MODE_SLOW(GPLL_ID), RKIO_GRF_PHYS + CRU_MODE_CON); /* soft reset */ writel(0xeca8, RKIO_CRU_PHYS + CRU_GLB_SRST_SND); #elif defined(CONFIG_RKCHIP_RK3126) || defined(CONFIG_RKCHIP_RK3128) /* pll enter slow mode */ writel(PLL_MODE_SLOW(APLL_ID) | PLL_MODE_SLOW(CPLL_ID) | PLL_MODE_SLOW(GPLL_ID), RKIO_GRF_PHYS + CRU_MODE_CON); /* soft reset */ writel(0xeca8, RKIO_CRU_PHYS + CRU_GLB_SRST_SND); #else #error "PLS config platform for reset.c!" #endif /* CONFIG_RKPLATFORM */ }
void reset_cpu(ulong ignored) { disable_interrupts(); FW_NandDeInit(); #ifndef CONFIG_SYS_L2CACHE_OFF v7_outer_cache_disable(); #endif #ifndef CONFIG_SYS_DCACHE_OFF flush_dcache_all(); #endif #ifndef CONFIG_SYS_ICACHE_OFF invalidate_icache_all(); #endif #ifndef CONFIG_SYS_DCACHE_OFF dcache_disable(); #endif #ifndef CONFIG_SYS_ICACHE_OFF icache_disable(); #endif #if (CONFIG_RKCHIPTYPE == CONFIG_RK3288) /* disable remap */ /* rk3288 address remap control bit: SGRF soc con0 bit 11 */ writel(1 << (11 + 16), RKIO_SECURE_GRF_PHYS + SGRF_SOC_CON0); /* pll enter slow mode */ writel(PLL_MODE_SLOW(APLL_ID) | PLL_MODE_SLOW(GPLL_ID) | PLL_MODE_SLOW(CPLL_ID) | PLL_MODE_SLOW(NPLL_ID), RKIO_GRF_PHYS + CRU_MODE_CON); /* soft reset */ writel(0xeca8, RKIO_CRU_PHYS + CRU_GLB_SRST_SND); #else #error "PLS config platform for reset.c!" #endif /* CONFIG_RKPLATFORM */ }
void reset_cpu(ulong ignored) { disable_interrupts(); FW_NandDeInit(); #ifndef CONFIG_SYS_L2CACHE_OFF v7_outer_cache_disable(); #endif #ifndef CONFIG_SYS_DCACHE_OFF flush_dcache_all(); #endif #ifndef CONFIG_SYS_ICACHE_OFF invalidate_icache_all(); #endif #ifndef CONFIG_SYS_DCACHE_OFF dcache_disable(); #endif #ifndef CONFIG_SYS_ICACHE_OFF icache_disable(); #endif #if defined(CONFIG_RKCHIP_RK3368) /* pll enter slow mode */ cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(APLLB_ID, 3)); cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(APLLL_ID, 3)); cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(GPLL_ID, 3)); cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(CPLL_ID, 3)); cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(NPLL_ID, 3)); /* soft reset */ writel(0xeca8, RKIO_CRU_PHYS + CRU_GLB_SRST_SND); #else #error "PLS config platform for reset.c!" #endif /* CONFIG_RKPLATFORM */ }