/*----------------------------------------------------------------------------*/
VOID
HifPdmaInit (
GL_HIF_INFO_T *HifInfo
)
{
/* IO remap GDMA register memory */
HifInfo->DmaRegBaseAddr = ioremap(AP_DMA_HIF_BASE, AP_DMA_HIF_0_LENGTH);
/* assign GDMA operators */
HifInfo->DmaOps = &HifGdmaOps;
/* enable GDMA mode */
HifInfo->fgDmaEnable = TRUE;
#if 0 // MPU Setting, we need to enable it after MPU ready
// WIFI using TOP 512KB
printk("[wlan] MPU region 12, 0x%08x - 0x%08x\n", (UINT_32)gConEmiPhyBase, (UINT_32)(gConEmiPhyBase + 512*1024));
emi_mpu_set_region_protection(gConEmiPhyBase,
gConEmiPhyBase + 512*1024 - 1,
12,
SET_ACCESS_PERMISSON(NO_PROTECTION,FORBIDDEN,FORBIDDEN,FORBIDDEN,FORBIDDEN,NO_PROTECTION,FORBIDDEN,FORBIDDEN));
#endif
GDMA_DBG(("GDMA> HifGdmaInit ok!\n"));
}
/*----------------------------------------------------------------------------*/
VOID
HifPdmaInit (
GL_HIF_INFO_T *HifInfo
)
{
/* IO remap GDMA register memory */
HifInfo->DmaRegBaseAddr = ioremap(AP_DMA_HIF_BASE, AP_DMA_HIF_0_LENGTH);
/* assign GDMA operators */
HifInfo->DmaOps = &HifGdmaOps;
/* enable GDMA mode */
HifInfo->fgDmaEnable = TRUE;
GDMA_DBG(("GDMA> HifGdmaInit ok!\n"));
}
/*----------------------------------------------------------------------------*/
static VOID
HifGdmaStart(
IN GL_HIF_INFO_T *HifInfo
)
{
UINT32 RegVal;
/* Enable interrupt */
RegVal = HIF_DMAR_READL(HifInfo, AP_P_DMA_G_DMA_2_INT_EN);
HIF_DMAR_WRITEL(HifInfo, AP_P_DMA_G_DMA_2_INT_EN, (RegVal | ADH_CR_INTEN_FLAG_0));
/* Start DMA */
RegVal = HIF_DMAR_READL(HifInfo, AP_P_DMA_G_DMA_2_EN);
HIF_DMAR_WRITEL(HifInfo, AP_P_DMA_G_DMA_2_EN, (RegVal | ADH_CR_EN | ADH_CR_CONN_BUR_EN));
GDMA_DBG(("GDMA> HifGdmaStart...\n"));
} /* End of HifGdmaStart */
/*----------------------------------------------------------------------------*/
static VOID
HifGdmaConfig (
IN void *HifInfoSrc,
IN void *Param
)
{
GL_HIF_INFO_T *HifInfo = (GL_HIF_INFO_T *)HifInfoSrc;
MTK_WCN_HIF_DMA_CONF *Conf = (MTK_WCN_HIF_DMA_CONF *)Param;
UINT32 RegVal;
/* Assign fixed value */
Conf->Ratio = HIF_GDMA_RATIO_1;
Conf->Connect = HIF_GDMA_CONNECT_SET1;
Conf->Wsize = HIF_GDMA_WRITE_2;
Conf->Burst = HIF_GDMA_BURST_4_8;
Conf->Fix_en = TRUE;
/* AP_P_DMA_G_DMA_2_CON */
GDMA_DBG(("GDMA> Conf->Dir = %d\n", Conf->Dir));
RegVal = HIF_DMAR_READL(HifInfo, AP_P_DMA_G_DMA_2_CON);
RegVal &= ~(ADH_CR_FLAG_FINISH | ADH_CR_RSIZE | ADH_CR_WSIZE | \
ADH_CR_BURST_LEN | ADH_CR_WADDR_FIX_EN | ADH_CR_RADDR_FIX_EN);
if (Conf->Dir == HIF_DMA_DIR_TX)
{
RegVal |= (((Conf->Wsize<<ADH_CR_WSIZE_OFFSET)&ADH_CR_WSIZE) | \
((Conf->Burst<<ADH_CR_BURST_LEN_OFFSET)&ADH_CR_BURST_LEN) | \
((Conf->Fix_en<<ADH_CR_WADDR_FIX_EN_OFFSET)&ADH_CR_WADDR_FIX_EN));
}
else
{
RegVal |= (((Conf->Wsize<<ADH_CR_RSIZE_OFFSET)&ADH_CR_RSIZE) | \
((Conf->Burst<<ADH_CR_BURST_LEN_OFFSET)&ADH_CR_BURST_LEN) | \
((Conf->Fix_en<<ADH_CR_RADDR_FIX_EN_OFFSET)&ADH_CR_RADDR_FIX_EN));
}
HIF_DMAR_WRITEL(HifInfo, AP_P_DMA_G_DMA_2_CON, RegVal);
GDMA_DBG(("GDMA> AP_P_DMA_G_DMA_2_CON = 0x%08x\n", RegVal));
/* AP_P_DMA_G_DMA_2_CONNECT */
RegVal = HIF_DMAR_READL(HifInfo, AP_P_DMA_G_DMA_2_CONNECT);
RegVal &= ~(ADH_CR_RATIO | ADH_CR_DIR | ADH_CR_CONNECT);
RegVal |= (((Conf->Ratio<<ADH_CR_RATIO_OFFSET)&ADH_CR_RATIO) | \
((Conf->Dir<<ADH_CR_DIR_OFFSET)&ADH_CR_DIR) | \
(Conf->Connect&ADH_CR_CONNECT));
HIF_DMAR_WRITEL(HifInfo, AP_P_DMA_G_DMA_2_CONNECT, RegVal);
GDMA_DBG(("GDMA> AP_P_DMA_G_DMA_2_CONNECT = 0x%08x\n", RegVal));
/* AP_DMA_HIF_0_SRC_ADDR */
HIF_DMAR_WRITEL(HifInfo, AP_P_DMA_G_DMA_2_SRC_ADDR, Conf->Src);
GDMA_DBG(("GDMA> AP_P_DMA_G_DMA_2_SRC_ADDR = 0x%08x\n", Conf->Src));
/* AP_DMA_HIF_0_DST_ADDR */
HIF_DMAR_WRITEL(HifInfo, AP_P_DMA_G_DMA_2_DST_ADDR, Conf->Dst);
GDMA_DBG(("GDMA> AP_P_DMA_G_DMA_2_DST_ADDR = 0x%08x\n", Conf->Dst));
/* AP_P_DMA_G_DMA_2_LEN1 */
HIF_DMAR_WRITEL(HifInfo, AP_P_DMA_G_DMA_2_LEN1, (Conf->Count & ADH_CR_LEN));
GDMA_DBG(("GDMA> AP_P_DMA_G_DMA_2_LEN1 = %ld\n", (Conf->Count & ADH_CR_LEN)));
}/* End of HifGdmaConfig */
