static int fimc_is_ixc_video_g_ctrl(struct file *file, void *priv,
struct v4l2_control *ctrl)
{
int ret = 0;
struct fimc_is_video_ctx *vctx = file->private_data;
struct fimc_is_framemgr *framemgr;
BUG_ON(!vctx);
BUG_ON(!ctrl);
mdbgv_ixc("%s\n", vctx, __func__);
framemgr = GET_FRAMEMGR(vctx);
switch (ctrl->id) {
case V4L2_CID_IS_G_COMPLETES:
ctrl->value = framemgr->frame_com_cnt;
break;
default:
err("unsupported ioctl(%d)\n", ctrl->id);
ret = -EINVAL;
break;
}
return ret;
}
static int fimc_is_ssx_video_s_input(struct file *file, void *priv,
unsigned int input)
{
int ret = 0;
u32 scenario;
#if defined(CONFIG_CAMERA_SUPPORT_PDAF)
u32 pdaf_on;
#endif
struct fimc_is_video_ctx *vctx = file->private_data;
struct fimc_is_device_sensor *device;
struct fimc_is_framemgr *framemgr;
BUG_ON(!vctx);
mdbgv_sensor("%s(input : %08X)\n", vctx, __func__, input);
device = GET_DEVICE(vctx);
framemgr = GET_FRAMEMGR(vctx);
scenario = (input & SENSOR_SCENARIO_MASK) >> SENSOR_SCENARIO_SHIFT;
#if defined(CONFIG_CAMERA_SUPPORT_PDAF)
pdaf_on = (input & SENSOR_PDAFON_MASK) >> SENSOR_PDAFON_SHIFT;
#endif
input = (input & SENSOR_MODULE_MASK) >> SENSOR_MODULE_SHIFT;
#if defined(CONFIG_CAMERA_SUPPORT_PDAF)
device->pdaf_on = pdaf_on;
#endif
ret = fimc_is_video_s_input(file, vctx);
if (ret) {
merr("fimc_is_video_s_input is fail(%d)", vctx, ret);
goto p_err;
}
ret = fimc_is_sensor_s_input(device, input, scenario);
if (ret) {
merr("fimc_is_sensor_s_input is fail(%d)", device, ret);
goto p_err;
}
p_err:
return ret;
}
static void __fimc_is_fault_handler(struct device *dev)
{
u32 i, j, k;
struct fimc_is_core *core;
struct fimc_is_device_sensor *sensor;
struct fimc_is_device_ischain *ischain;
struct fimc_is_subdev *subdev;
struct fimc_is_framemgr *framemgr;
struct fimc_is_resourcemgr *resourcemgr;
core = dev_get_drvdata(dev);
if (core) {
resourcemgr = &core->resourcemgr;
fimc_is_hw_fault(&core->interface);
/* dump FW page table 1nd(~16KB), 2nd(16KB~32KB) */
fimc_is_hw_memdump(&core->interface,
resourcemgr->minfo.kvaddr + FIMC_IS_TTB_OFFSET, /* TTB_BASE ~ 32KB */
resourcemgr->minfo.kvaddr + FIMC_IS_TTB_OFFSET + FIMC_IS_TTB_SIZE);
fimc_is_hw_logdump(&core->interface);
/* SENSOR */
for (i = 0; i < FIMC_IS_SENSOR_COUNT; i++) {
sensor = &core->sensor[i];
framemgr = GET_FRAMEMGR(sensor->vctx);
if (test_bit(FIMC_IS_SENSOR_OPEN, &sensor->state) && framemgr) {
struct fimc_is_device_flite *flite;
struct fimc_is_device_csi *csi;
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[SS%d] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
/* vc0 */
framemgr = GET_SUBDEV_FRAMEMGR(&sensor->ssvc0);
if (test_bit(FIMC_IS_SUBDEV_START, &sensor->ssvc0.state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[SS%dVC0] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* vc1 */
framemgr = GET_SUBDEV_FRAMEMGR(&sensor->ssvc1);
if (test_bit(FIMC_IS_SUBDEV_START, &sensor->ssvc1.state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[SS%dVC1] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* vc2 */
framemgr = GET_SUBDEV_FRAMEMGR(&sensor->ssvc2);
if (test_bit(FIMC_IS_SUBDEV_START, &sensor->ssvc2.state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[SS%dVC2] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* vc3 */
framemgr = GET_SUBDEV_FRAMEMGR(&sensor->ssvc3);
if (test_bit(FIMC_IS_SUBDEV_START, &sensor->ssvc3.state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[SS%dVC3] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* csis, bns sfr dump */
flite = (struct fimc_is_device_flite *)v4l2_get_subdevdata(sensor->subdev_flite);
if (flite)
flite_hw_dump(flite->base_reg);
csi = (struct fimc_is_device_csi *)v4l2_get_subdevdata(sensor->subdev_csi);
if (csi)
csi_hw_dump(csi->base_reg);
}
}
/* ISCHAIN */
for (i = 0; i < FIMC_IS_STREAM_COUNT; i++) {
ischain = &core->ischain[i];
if (test_bit(FIMC_IS_ISCHAIN_OPEN, &ischain->state)) {
/* 3AA */
subdev = &ischain->group_3aa.leader;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][3XS] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* 3AAC */
subdev = &ischain->txc;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][3XC] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* 3AAP */
subdev = &ischain->txp;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][3XP] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* ISP */
subdev = &ischain->group_isp.leader;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][IXS] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* ISPC */
subdev = &ischain->ixc;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][IXC] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* ISPP */
subdev = &ischain->ixp;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][IXP] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* DIS */
subdev = &ischain->group_dis.leader;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][DIS] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* SCC */
subdev = &ischain->scc;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][SCC] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* SCP */
subdev = &ischain->scp;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][SCP] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* MCS */
subdev = &ischain->group_mcs.leader;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][MCS] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* M0P */
subdev = &ischain->m0p;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][M0P] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* M1P */
subdev = &ischain->m1p;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][M1P] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* M2P */
subdev = &ischain->m2p;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][M2P] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* M3P */
subdev = &ischain->m3p;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][M3P] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* M4P */
subdev = &ischain->m4p;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][M4P] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
/* VRA */
subdev = &ischain->group_vra.leader;
framemgr = GET_SUBDEV_FRAMEMGR(subdev);
if (test_bit(FIMC_IS_SUBDEV_START, &subdev->state) && framemgr) {
for (j = 0; j < framemgr->num_frames; ++j) {
for (k = 0; k < framemgr->frames[j].planes; k++) {
pr_err("[%d][VRA] BUF[%d][%d] = 0x%08X(0x%lX)\n", i, j, k,
framemgr->frames[j].dvaddr_buffer[k],
framemgr->frames[j].mem_state);
}
}
}
}
}
} else {
pr_err("failed to get core\n");
}
}
