UQI
frvbf_read_mem_UQI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
USI hsr0 = GET_HSR0 ();
FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
/* Check for access exceptions. */
address = check_data_read_address (current_cpu, address, 0);
address = check_readwrite_address (current_cpu, address, 0);
/* If we need to count cycles, then the cache operation will be
initiated from the model profiling functions.
See frvbf_model_.... */
if (model_insn)
{
CPU_LOAD_ADDRESS (current_cpu) = address;
CPU_LOAD_LENGTH (current_cpu) = 1;
CPU_LOAD_SIGNED (current_cpu) = 0;
return 0xb7; /* any random value */
}
if (GET_HSR0_DCE (hsr0))
{
int cycles;
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, UQI, 1);
}
return GETMEMUQI (current_cpu, pc, address);
}
void
frvbf_write_mem_DF (SIM_CPU *current_cpu, IADDR pc, SI address, DF value)
{
USI hsr0;
hsr0 = GET_HSR0 ();
if (GET_HSR0_DCE (hsr0))
sim_queue_fn_mem_df_write (current_cpu, frvbf_mem_set_DF, address, value);
else
sim_queue_mem_df_write (current_cpu, address, value);
frv_set_write_queue_slot (current_cpu);
}
/* Determine whether the given cache is enabled. */
int
frv_cache_enabled (FRV_CACHE *cache)
{
SIM_CPU *current_cpu = cache->cpu;
int hsr0 = GET_HSR0 ();
if (GET_HSR0_ICE (hsr0) && cache == CPU_INSN_CACHE (current_cpu))
return 1;
if (GET_HSR0_DCE (hsr0) && cache == CPU_DATA_CACHE (current_cpu))
return 1;
return 0;
}
UHI
frvbf_read_mem_UHI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
USI hsr0;
FRV_CACHE *cache;
/* Check for access exceptions. */
address = check_data_read_address (current_cpu, address, 1);
address = check_readwrite_address (current_cpu, address, 1);
/* If we need to count cycles, then the cache operation will be
initiated from the model profiling functions.
See frvbf_model_.... */
hsr0 = GET_HSR0 ();
cache = CPU_DATA_CACHE (current_cpu);
if (model_insn)
{
CPU_LOAD_ADDRESS (current_cpu) = address;
CPU_LOAD_LENGTH (current_cpu) = 2;
CPU_LOAD_SIGNED (current_cpu) = 0;
return 0xb711; /* any random value */
}
if (GET_HSR0_DCE (hsr0))
{
int cycles;
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 2))
return read_mem_unaligned_HI (current_cpu, pc, address);
}
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, UHI, 2);
}
return GETMEMUHI (current_cpu, pc, address);
}
