static void timerIRQHandler(uint32_t token) {
//dump_memory(0x3e200000, 0x100);
/* this function does not implement incrementing a counter at dword_18022B28 like Apple's */
uint32_t stat = GET_REG(TIMER + TIMER_IRQSTAT);
/* signal timer is being handled */
volatile register uint32_t discard = GET_REG(TIMER + TIMER_IRQLATCH); discard --;
if(stat & TIMER_SPECIALTIMER_BIT0) {
SET_REG(TIMER + TIMER_UNKREG0, GET_REG(TIMER + TIMER_UNKREG0) | TIMER_SPECIALTIMER_BIT0);
}
if(stat & TIMER_SPECIALTIMER_BIT1) {
SET_REG(TIMER + TIMER_UNKREG0, GET_REG(TIMER + TIMER_UNKREG0) | TIMER_SPECIALTIMER_BIT1);
}
int i;
for(i = TIMER_Separator; i < NUM_TIMERS; i++) {
callTimerHandler(i, stat >> (8 * (NUM_TIMERS - i - 1)));
}
/* signal timer has been handled */
SET_REG(TIMER + TIMER_IRQLATCH, stat);
}
void setupDisconnectPin (void) {
/* enable USB DISC Pin */
#ifdef STM32F2
#if !defined(BOARD_DiscoveryF4)
pRCC->AHB1ENR |= RCC_AHB1ENR_USB;
GPIO_TypeDef *p = (GPIO_TypeDef *)USB_DISC_BANK;
/* set to output */
p->MODER |= 1 << (2*USB_DISC);
/* Configure pins speed to 100 MHz */
//p->OSPEEDR = 0xffffc00f; // 2 bit/port medium speed = %01
/* Configure pins Output type to open drain */
p->OTYPER |= 1 << (1*USB_DISC);
/* No pull-up, pull-down for PEx pins */
//p->PUPDR = 0x00000000;
#endif
#else
pRCC->APB2ENR |= RCC_APB2ENR_USB;
/* Setup USB DISC pin as output open drain */
#ifdef USB_DISC_OD
SET_REG(USB_DISC_CR, (GET_REG(USB_DISC_CR) & USB_DISC_CR_MASK) | USB_DISC_CR_OUTPUT_OD); // ala42 just pull down external pull up
#else
SET_REG(USB_DISC_CR, (GET_REG(USB_DISC_CR) & USB_DISC_CR_MASK) | USB_DISC_CR_OUTPUT_PP); // ala42 actively pull up USBDP
#endif
#endif
}
int dma_cancel(int channel) {
//bufferPrintf("cdma: dma_cancel.\r\n");
DMAInfo* dma = &dmaInfo[channel];
uint64_t startTime = timer_get_system_microtime();
if (!dma->signalled)
return channel;
dma_channel_activate(channel, 1);
uint32_t channel_reg = DMA + (channel << 12);
if (GET_BITS(GET_REG(channel_reg), 16, 2) == 1) {
SET_REG(channel_reg, 4);
while (GET_BITS(GET_REG(channel_reg), 16, 2) == 1) {
if (has_elapsed(startTime, 10000))
system_panic("CDMA: channel %d timeout during abort\r\n", channel);
}
SET_REG(channel_reg, 2);
}
dma->signalled = 1;
dma_set_aes(channel, 0);
return dma_channel_activate(channel, 0);
}
int spi_tx(int port, const uint8_t* buffer, int len, int block, int unknown) {
if(port > (NUM_SPIPORTS - 1)) {
return -1;
}
SET_REG(SPIRegs[port].control, GET_REG(SPIRegs[port].control) | (1 << 2));
SET_REG(SPIRegs[port].control, GET_REG(SPIRegs[port].control) | (1 << 3));
spi_info[port].txBuffer = buffer;
if(len > MAX_TX_BUFFER)
spi_info[port].txCurrentLen = MAX_TX_BUFFER;
else
spi_info[port].txCurrentLen = len;
spi_info[port].txTotalLen = len;
spi_info[port].txDone = FALSE;
if(unknown == 0) {
SET_REG(SPIRegs[port].cnt, 0);
}
spi_txdata(port, buffer, 0, spi_info[port].txCurrentLen);
SET_REG(SPIRegs[port].control, 1);
if(block) {
while(!spi_info[port].txDone || GET_BITS(GET_REG(SPIRegs[port].status), 4, 4) != 0) {
// yield
}
return len;
} else {
return 0;
}
}
void setupLED(void) {
#if defined(ARCH_SI32)
// Enable Crossbar 1 to use LED
SET_REG(XBAR1_SET, 0x80000000);
SET_REG(XBAR0H_SET, 0x80000000);
// Set LED 3 as push pull output
SET_REG(GPIO_OUTMD_SET(PORT_BANK3), 0x00000001);
SET_REG(GPIO_MDSEL_SET(PORT_BANK3), 0x00000001);
#elif defined(ARC_STM32)
// todo, swap out hardcoded pin/bank with macro
u32 rwmVal; /* read-write-modify place holder var */
/* Setup APB2 (GPIOA) */
rwmVal = GET_REG(RCC_APB2ENR);
rwmVal |= 0x00000004;
SET_REG(RCC_APB2ENR, rwmVal);
/* Setup GPIOA Pin 5 as PP Out */
SET_REG(GPIO_CRL(GPIOA), 0x00100000);
rwmVal = GET_REG(GPIO_CRL(GPIOA));
rwmVal &= 0xFF0FFFFF;
rwmVal |= 0x00100000;
SET_REG(GPIO_CRL(GPIOA), rwmVal);
setPin(GPIOA, 5);
#endif // defined(ARCH_SI32)
}
int gpio_get_value(rt_uint32_t gpio)
{
rt_uint32_t tmp, base, offset;
if (!gpio_available[gpio])
{
rt_kprintf("ERROR: %s, GPIO %d is not available\n", __func__, gpio);
return -RT_EBUSY;
}
offset = gpio % 32;
base = gpio_to_base(gpio);
tmp = GET_REG(base + REG_GPIO_SWPORTA_DDR);
tmp &= BIT(offset);
if (tmp)
{
tmp = GET_REG(base + REG_GPIO_SWPORTA_DR);
}
else
{
tmp = GET_REG(base + REG_GPIO_EXT_PORTA);
}
tmp &= BIT(offset);
tmp = tmp >> offset;
return tmp;
}
void updateScreen() {
ili9340_setBackColor(0x0000);
ili9340_setFrontColor(0xFFFF);
//Draw info
itoa(GET_REG(REG_ACC), buff, 10);
ili9340_fillRect( BOX_SPLIT + 8, BOX_TOP + INFO_HEIGHT*0 + 16, 8*4, 13, 0x0000);
ili9340_drawString( BOX_SPLIT + 8, BOX_TOP + INFO_HEIGHT*0 + 16, buff);
itoa(GET_REG(REG_BAK), buff, 10);
ili9340_fillRect( BOX_SPLIT + 8, BOX_TOP + INFO_HEIGHT*1 + 16, 8*4, 13, 0x0000);
ili9340_drawString( BOX_SPLIT + 8, BOX_TOP + INFO_HEIGHT*1 + 16, buff);
//TODO: LAST: Last side used when ANY
//TODO: MODE: Current Running mode (IDLE, RUN, WRITING, READING)
//IDLE PERCENTAGE
itoa(0, buff, 10);
ili9340_fillRect( BOX_SPLIT + 8, BOX_TOP + INFO_HEIGHT*4 + 16, 8*4, 13, 0x0000);
ili9340_drawString( BOX_SPLIT + 8, BOX_TOP + INFO_HEIGHT*4 + 16, buff);
//Draw instruction
for(uint8_t i = 0; i < 15; i++) {
if(i != lastPC && i != GET_REG(REG_PC))
continue;
drawInstr(i);
}
lastPC = GET_REG(REG_PC);
}
int spi_rx(int port, uint8_t* buffer, int len, int block, int unknown) {
if(port >= (NUM_SPIPORTS - 1)) {
return -1;
}
SET_REG(SPIRegs[port].control, GET_REG(SPIRegs[port].control) | (1 << 2));
SET_REG(SPIRegs[port].control, GET_REG(SPIRegs[port].control) | (1 << 3));
spi_info[port].rxBuffer = buffer;
spi_info[port].rxDone = FALSE;
spi_info[port].rxCurrentLen = 0;
spi_info[port].rxTotalLen = len;
spi_info[port].counter = 0;
SET_REG(SPIRegs[port].unkReg2, len);
SET_REG(SPIRegs[port].control, 1);
if(unknown == 0) {
SET_REG(SPIRegs[port].setup, GET_REG(SPIRegs[port].setup) | 1);
}
if(block) {
while(!spi_info[port].rxDone) {
// yield
}
if(unknown == 0) {
SET_REG(SPIRegs[port].setup, GET_REG(SPIRegs[port].setup) & ~1);
}
return len;
} else {
return 0;
}
}
int usb_start(USBEnumerateHandler hEnumerate, USBStartHandler hStart) {
enumerateHandler = hEnumerate;
startHandler = hStart;
currentlySending = 0xFF;
if(txQueue == NULL)
txQueue = createRingBuffer(TX_QUEUE_LEN);
initializeDescriptors();
if(controlSendBuffer == NULL)
controlSendBuffer = memalign(DMA_ALIGN, CONTROL_SEND_BUFFER_LEN);
if(controlRecvBuffer == NULL)
controlRecvBuffer = memalign(DMA_ALIGN, CONTROL_RECV_BUFFER_LEN);
SET_REG(USB + GAHBCFG, GAHBCFG_DMAEN | GAHBCFG_BSTLEN_INCR8 | GAHBCFG_MASKINT);
SET_REG(USB + GUSBCFG, GUSBCFG_PHYIF16BIT | GUSBCFG_SRPENABLE | GUSBCFG_HNPENABLE | ((5 & GUSBCFG_TURNAROUND_MASK) << GUSBCFG_TURNAROUND_SHIFT));
SET_REG(USB + DCFG, DCFG_HISPEED); // some random setting. See specs
SET_REG(USB + DCFG, GET_REG(USB + DCFG) & ~(DCFG_DEVICEADDRMSK));
InEPRegs[0].control = USB_EPCON_ACTIVE;
OutEPRegs[0].control = USB_EPCON_ACTIVE;
SET_REG(USB + GRXFSIZ, RX_FIFO_DEPTH);
SET_REG(USB + GNPTXFSIZ, (TX_FIFO_DEPTH << GNPTXFSIZ_DEPTH_SHIFT) | TX_FIFO_STARTADDR);
int i;
for(i = 0; i < USB_NUM_ENDPOINTS; i++) {
InEPRegs[i].interrupt = USB_EPINT_INEPNakEff | USB_EPINT_INTknEPMis | USB_EPINT_INTknTXFEmp
| USB_EPINT_TimeOUT | USB_EPINT_AHBErr | USB_EPINT_EPDisbld | USB_EPINT_XferCompl;
OutEPRegs[i].interrupt = USB_EPINT_OUTTknEPDis
| USB_EPINT_SetUp | USB_EPINT_AHBErr | USB_EPINT_EPDisbld | USB_EPINT_XferCompl;
InEPRegs[i].control = (InEPRegs[i].control & ~(DCTL_NEXTEP_MASK << DCTL_NEXTEP_SHIFT));
}
SET_REG(USB + GINTMSK, GINTMSK_OTG | GINTMSK_SUSPEND | GINTMSK_RESET | GINTMSK_INEP | GINTMSK_OEP | GINTMSK_DISCONNECT);
SET_REG(USB + DAINTMSK, DAINTMSK_ALL);
SET_REG(USB + DOEPMSK, USB_EPINT_XferCompl | USB_EPINT_SetUp | USB_EPINT_Back2BackSetup);
SET_REG(USB + DIEPMSK, USB_EPINT_XferCompl | USB_EPINT_AHBErr | USB_EPINT_TimeOUT);
InEPRegs[0].interrupt = USB_EPINT_ALL;
OutEPRegs[0].interrupt = USB_EPINT_ALL;
SET_REG(USB + DCTL, DCTL_PROGRAMDONE + DCTL_CGOUTNAK + DCTL_CGNPINNAK);
udelay(USB_PROGRAMDONE_DELAYUS);
SET_REG(USB + GOTGCTL, GET_REG(USB + GOTGCTL) | GOTGCTL_SESSIONREQUEST);
receiveControl(controlRecvBuffer, sizeof(USBSetupPacket));
change_state(USBPowered);
interrupt_enable(USB_INTERRUPT);
return 0;
}
static void delay_cycles(unsigned long cycles)
{
unsigned long now, start;
SET_REG(P4A_TIMER2_CTRL_REG,GET_REG(P4A_TIMER2_CTRL_REG)|TIME_RESETCNT);
now = start = GET_REG(P4A_TIMER2_CNT_REG);
while ((now - start) < cycles)
now = GET_REG(P4A_TIMER2_CNT_REG);
}
void usb_phy_shutdown()
{
SET_REG(USB_PHY + OPHYPWR, OPHYPWR_FORCESUSPEND | OPHYPWR_PLLPOWERDOWN
| OPHYPWR_XOPOWERDOWN | OPHYPWR_ANALOGPOWERDOWN | OPHYPWR_UNKNOWNPOWERDOWN); // power down phy
SET_REG(USB_PHY + ORSTCON, GET_REG(USB_PHY + ORSTCON) | ORSTCON_PHYSWRESET);
udelay(USB_RESET_DELAYUS); // wait a millisecond for the changes to stick
SET_REG(USB_PHY + OPHYUNK1, GET_REG(USB_PHY + OPHYUNK1) &~ OPHYUNK1_STOP_MASK);
}
static int si3054_switch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *uvalue)
{
struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
u16 reg = PRIVATE_REG(kcontrol->private_value);
u16 mask = PRIVATE_MASK(kcontrol->private_value);
if (uvalue->value.integer.value[0])
SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) | mask);
else
SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) & ~mask);
return 0;
}
int power_ctrl(uint32_t device, OnOff on_off) {
if(on_off == ON) {
SET_REG(POWER + POWER_ONCTRL, device);
} else {
SET_REG(POWER + POWER_OFFCTRL, device);
}
/* wait for the new state to take effect */
while((GET_REG(POWER + POWER_SETSTATE) & device) != (GET_REG(POWER + POWER_STATE) & device));
return 0;
}
int gpio_set_irq_type(rt_uint32_t gpio, rt_uint32_t type)
{
rt_uint32_t int_type, int_polarity;
rt_uint32_t bit = gpio % 32;
rt_uint32_t base;
if (!gpio_available[gpio])
{
rt_kprintf("ERROR: %s, GPIO %d is not available\n", __func__, gpio);
return -RT_EBUSY;
}
base = gpio_to_base(gpio);
int_type = GET_REG(base + REG_GPIO_INTTYPE_LEVEL);
int_polarity = GET_REG(base + REG_GPIO_INT_POLARITY);
switch (type & IRQ_TYPE_TRIGGER_MASK)
{
case IRQ_TYPE_EDGE_BOTH:
int_type |= BIT(bit);
// toggle trigger
if (gpio_get_value(gpio))
int_polarity &= ~BIT(bit);
else
int_polarity |= BIT(bit);
break;
case IRQ_TYPE_EDGE_RISING:
int_type |= BIT(bit);
int_polarity |= BIT(bit);
break;
case IRQ_TYPE_EDGE_FALLING:
int_type |= BIT(bit);
int_polarity &= ~BIT(bit);
break;
case IRQ_TYPE_LEVEL_HIGH:
int_type &= ~BIT(bit);
int_polarity |= BIT(bit);
break;
case IRQ_TYPE_LEVEL_LOW:
int_type &= ~BIT(bit);
int_polarity &= ~BIT(bit);
break;
case IRQ_TYPE_NONE:
return 0;
default:
return -RT_ERROR;
}
SET_REG(base + REG_GPIO_INTTYPE_LEVEL, int_type);
SET_REG(base + REG_GPIO_INT_POLARITY, int_polarity);
return 0;
}
/*********************************************************************************************************
** 函数名称: sio16c550PollInput
** 功能描述: 串口接口查询方式输入
** 输 入 : pchan SIO CHAN
** pc 读取到的数据
** 输 出 : ERROR or OK
** 全局变量:
** 调用模块:
*********************************************************************************************************/
static INT sio16c550PollInput (SIO16C550_CHAN *psiochan, CHAR *pc)
{
UINT8 poll_status = GET_REG(psiochan, LSR);
if ((poll_status & LSR_DR) == 0x00) {
_ErrorHandle(EAGAIN);
return (PX_ERROR);
}
*pc = GET_REG(psiochan, RBR); /* got a character */
return (ERROR_NONE);
}
int interrupt_enable(int irq_no) {
if(irq_no >= VIC_MaxInterrupt) {
return -1;
}
EnterCriticalSection();
if(irq_no < VIC_InterruptSeparator) {
SET_REG(VIC0 + VICINTENABLE, GET_REG(VIC0 + VICINTENABLE) | (1 << irq_no));
#ifndef CONFIG_IPHONE_4
} else {
SET_REG(VIC1 + VICINTENABLE, GET_REG(VIC1 + VICINTENABLE) | (1 << (irq_no - VIC_InterruptSeparator)));
#else
} else if(irq_no < VIC_InterruptSeparator*2) {
static void usb_set_global_out_nak()
{
usb_global_out_nak++;
if(usb_global_out_nak > 1)
return;
//bufferPrintf("USB: SGOUTNAK\n");
SET_REG(USB + GINTSTS, GINTMSK_GOUTNAKEFF);
SET_REG(USB + DCTL, GET_REG(USB + DCTL) | DCTL_SGOUTNAK);
while ((GET_REG(USB + GINTSTS) & GINTMSK_GOUTNAKEFF) != GINTMSK_GOUTNAKEFF);
SET_REG(USB + GINTSTS, GINTMSK_GOUTNAKEFF);
}
static int wait_for_ready(int timeout) {
if((GET_REG(NAND + NAND_STATUS) & NAND_STATUS_READY) != 0) {
return 0;
}
uint64_t startTime = timer_get_system_microtime();
while((GET_REG(NAND + NAND_STATUS) & NAND_STATUS_READY) == 0) {
if(has_elapsed(startTime, timeout * 1000)) {
return ERROR_TIMEOUT;
}
}
return 0;
}
void usb_phy_init() {
// power on PHY
SET_REG(USB_PHY + OPHYPWR, OPHYPWR_POWERON);
udelay(USB_PHYPWRPOWERON_DELAYUS);
// select clock
SET_REG(USB_PHY + OPHYCLK, (GET_REG(USB_PHY + OPHYCLK) & (~OPHYCLK_CLKSEL_MASK)) | OPHYCLK_CLKSEL_48MHZ);
// reset phy
SET_REG(USB_PHY + ORSTCON, GET_REG(USB_PHY + ORSTCON) | ORSTCON_PHYSWRESET);
udelay(USB_RESET2_DELAYUS);
SET_REG(USB_PHY + ORSTCON, GET_REG(USB_PHY + ORSTCON) & (~ORSTCON_PHYSWRESET));
udelay(USB_RESET_DELAYUS);
}
int spi_tx(int port, const uint8_t* buffer, int len, int block, int unknown)
{
if(port >= SPICount || port < 0)
return -1;
SPIStruct *spi = &SPIData[port];
SET_REG(spi->registers->control, GET_REG(spi->registers->control) | (1 << 2));
SET_REG(spi->registers->control, GET_REG(spi->registers->control) | (1 << 3));
// Set len to number of words.
len = (len + ((1<<spi->wordSize)-1)) >> spi->wordSize;
spi->txBuffer = (void*)buffer;
spi->rxBuffer = NULL;
spi->txLength = len;
if(len > MAX_TX_BUFFER)
spi->txDone = MAX_TX_BUFFER;
else
spi->txDone = len;
if(unknown == 0) {
SET_REG(spi->registers->rxCount, 0);
}
else
{
spi->config |= 0x80;
}
//bufferPrintf("spi_tx(%d, %p, %d, %d, %d)\n", port, buffer, len, block, unknown);
spi_txdata(spi, buffer, 0, spi->txDone);
spi->config |= 0x200100;
SET_REG(spi->registers->txCount, len);
SET_REG(spi->registers->config, spi->config);
SET_REG(spi->registers->control, 1);
if(block)
{
while(spi->txBuffer != NULL || TX_BUFFER_LEFT(GET_REG(spi->registers->status)) > 0)
task_yield();
return len;
}
else
return 0;
}
/*********************************************************************************************************
** 函数名称: sio16c550Isr
** 功能描述: 16C550 中断服务函数
** 输 入 : psiochan SIO CHAN
** 输 出 : ERROR or OK
** 全局变量:
** 调用模块:
*********************************************************************************************************/
VOID sio16c550Isr (SIO16C550_CHAN *psiochan)
{
volatile UINT8 iir;
UINT8 msr;
UINT8 ucRd;
UINT8 ucTx;
INT i;
psiochan->int_ctx = 1;
KN_SMP_MB();
iir = (UINT8)(GET_REG(psiochan, IIR) & 0x0f);
while (GET_REG(psiochan, LSR) & RxCHAR_AVAIL) { /* receive data */
ucRd = GET_REG(psiochan, RBR);
psiochan->pcbPutRcvChar(psiochan->putRcvArg, ucRd);
}
if ((psiochan->ier & TxFIFO_BIT) &&
(GET_REG(psiochan, LSR) & LSR_THRE)) { /* transmit data */
for (i = 0; i < psiochan->fifo_len; i++) {
if (psiochan->pcbGetTxChar(psiochan->getTxArg, &ucTx) < 0) {
psiochan->ier &= (~TxFIFO_BIT);
break;
} else {
SET_REG(psiochan, THR, ucTx); /* char to Transmit Holding Reg */
}
}
}
if (iir == IIR_MSTAT) { /* modem status changed */
msr = GET_REG(psiochan, MSR);
if (msr & MSR_DCTS) {
if (msr & MSR_CTS) {
psiochan->ier |= TxFIFO_BIT; /* CTS was turned on */
} else {
psiochan->ier &= (~TxFIFO_BIT); /* CTS was turned off */
}
}
}
KN_SMP_MB();
psiochan->int_ctx = 0;
KN_SMP_MB();
SET_REG(psiochan, IER, psiochan->ier); /* update ier */
}
int interrupt_disable(int irq_no) {
if(irq_no >= VIC_MaxInterrupt) {
return -1;
}
EnterCriticalSection();
if(irq_no < VIC_InterruptSeparator) {
SET_REG(VIC0 + VICINTENABLE, GET_REG(VIC0 + VICINTENABLE) & ~(1 << irq_no));
} else {
SET_REG(VIC1 + VICINTENABLE, GET_REG(VIC1 + VICINTENABLE) & ~(1 << (irq_no - VIC_InterruptSeparator)));
}
LeaveCriticalSection();
return 0;
}
int power_setup() {
SET_REG(POWER + POWER_CONFIG0, POWER_CONFIG0_RESET);
SET_REG(POWER + POWER_CONFIG1, POWER_CONFIG1_RESET);
SET_REG(POWER + POWER_CONFIG2, POWER_CONFIG2_RESET);
/* turn off everything */
int toReset = POWER_DEFAULT_DEVICES | POWER_VROM | POWER_LCD;
SET_REG(POWER + POWER_OFFCTRL, toReset);
/* wait for the new state to take effect */
while((GET_REG(POWER + POWER_SETSTATE) & toReset) != (GET_REG(POWER + POWER_STATE) & toReset));
return 0;
}
void timer_get_rtc_ticks(uint64_t* ticks, uint64_t* sec_divisor) {
register uint32_t ticksHigh;
register uint32_t ticksLow;
register uint32_t ticksHigh2;
/* try to get a good read where the lower bits remain the same after reading the higher bits */
do {
ticksHigh = GET_REG(TIMER + TIMER_TICKSHIGH);
ticksLow = GET_REG(TIMER + TIMER_TICKSLOW);
ticksHigh2 = GET_REG(TIMER + TIMER_TICKSHIGH);
} while(ticksHigh != ticksHigh2);
*ticks = (((uint64_t)ticksHigh) << 32) | ticksLow;
*sec_divisor = TicksPerSec;
}
void clock_gate_switch(uint32_t gate, OnOff on_off) {
#if !defined(CONFIG_IPHONE_4) && !defined(CONFIG_IPAD)
uint32_t gate_register;
uint32_t gate_flag;
if(gate < CLOCK1_Separator) {
gate_register = CLOCK1 + CLOCK1_CL2_GATES;
gate_flag = gate;
} else {
gate_register = CLOCK1 + CLOCK1_CL3_GATES;
gate_flag = gate - CLOCK1_Separator;
}
uint32_t gates = GET_REG(gate_register);
if(on_off == ON) {
gates &= ~(1 << gate_flag);
} else {
gates |= 1 << gate_flag;
}
SET_REG(gate_register, gates);
#else
power_ctrl(gate, on_off);
#endif
}
/* Check for received packets */
s32 eth_rx (void)
{
s32 nLen = 0;
ETH *eth = &m_eth;
/* check if packet ready */
if ( (GET_REG( REG_BDMASTAT)) & ETH_S_BRxRDF) {
/* process all waiting packets */
while ( !eth->m_curRX_FD->m_frameDataPtr.bf.owner) {
nLen = eth->m_curRX_FD->m_status.bf.len;
/* call back u-boot -- may call eth_send() */
NetReceive ((u8 *)eth->m_curRX_FD->m_frameDataPtr.ui, nLen);
/* set owner back to CPU */
eth->m_curRX_FD->m_frameDataPtr.bf.owner = 1;
/* clear status */
eth->m_curRX_FD->m_status.ui = 0x0;
/* advance to next descriptor */
eth->m_curRX_FD = eth->m_curRX_FD->m_nextFD;
/* clear received frame bit */
PUT_REG( REG_BDMASTAT, ETH_S_BRxRDF);
}
}
return nLen;
}
static void callEndpointHandlers() {
uint32_t status = GET_REG(USB + DAINTMSK);
int endpoint;
for(endpoint = 0; endpoint < USB_NUM_ENDPOINTS; endpoint++) {
if((status & ((1 << endpoint) << DAINTMSK_OUT_SHIFT)) == ((1 << endpoint) << DAINTMSK_OUT_SHIFT)) {
if((outInterruptStatus[endpoint] & USB_EPINT_XferCompl) == USB_EPINT_XferCompl) {
if(endpoint_handlers[endpoint].out.handler != NULL) {
endpoint_handlers[endpoint].out.handler(endpoint_handlers[endpoint].out.token);
}
}
}
if((status & ((1 << endpoint) << DAINTMSK_IN_SHIFT)) == ((1 << endpoint) << DAINTMSK_IN_SHIFT)) {
if((inInterruptStatus[endpoint] & USB_EPINT_XferCompl) == USB_EPINT_XferCompl) {
if(endpoint_handlers[endpoint].in.handler != NULL) {
endpoint_handlers[endpoint].in.handler(endpoint_handlers[endpoint].in.token);
}
}
}
if(endpoint_directions[endpoint] == USBOut || endpoint_directions[endpoint] == USBBiDir) {
handleRxInterrupts(endpoint);
}
if(endpoint_directions[endpoint] == USBIn || endpoint_directions[endpoint] == USBBiDir) {
handleTxInterrupts(endpoint);
}
}
}
static int transferToFlash(void* buffer, int size) {
int controller = 0;
int channel = 0;
if((((uint32_t)buffer) & 0x3) != 0) {
// the buffer needs to be aligned for DMA, last two bits have to be clear
return ERROR_ALIGN;
}
SET_REG(NAND + FMCTRL0, GET_REG(NAND + FMCTRL0) | (1 << FMCTRL0_DMASETTINGSHIFT));
SET_REG(NAND + FMDNUM, size - 1);
SET_REG(NAND + FMCTRL1, 0x7F4);
CleanCPUDataCache();
dma_request(DMA_MEMORY, 4, 4, DMA_NAND, 4, 4, &controller, &channel, NULL);
dma_perform((uint32_t)buffer, DMA_NAND, size, 0, &controller, &channel);
if(dma_finish(controller, channel, 500) != 0) {
bufferPrintf("nand: dma timed out\r\n");
return ERROR_TIMEOUT;
}
if(wait_for_transfer_done(500) != 0) {
bufferPrintf("nand: waiting for transfer done timed out\r\n");
return ERROR_TIMEOUT;
}
SET_REG(NAND + FMCTRL1, FMCTRL1_FLUSHFIFOS);
CleanAndInvalidateCPUDataCache();
return 0;
}
void gpio_register_interrupt(uint32_t interrupt, int type, int level, int autoflip, InterruptServiceRoutine handler, uint32_t token)
{
uint8_t mode;
if(autoflip)
mode = 0xC;
else if(type)
{
if(level)
mode = 0x4;
else
mode = 0x6;
}
else
{
if(level)
mode = 0x8;
else
mode = 0xa;
}
gpio_interrupts[interrupt].token = token;
gpio_interrupts[interrupt].func = handler;
EnterCriticalSection();
reg32_t reg = GPIO + sizeof(uint32_t)*interrupt;
SET_REG(reg, (GET_REG(reg) &~ 0xE) | mode | 0x200);
LeaveCriticalSection();
}
static int transferToFlash(void* buffer, int size) {
int controller = 0;
int channel = 0;
if((((uint32_t)buffer) & 0x3) != 0) {
// the buffer needs to be aligned for DMA, last two bits have to be clear
return ERROR_ALIGN;
}
SET_REG(NAND + NAND_CONFIG, GET_REG(NAND + NAND_CONFIG) | (1 << NAND_CONFIG_DMASETTINGSHIFT));
SET_REG(NAND + NAND_TRANSFERSIZE, size - 1);
SET_REG(NAND + NAND_CON, 0x7F4);
CleanCPUDataCache();
dma_request(DMA_MEMORY, 4, 4, DMA_NAND, 4, 4, &controller, &channel, NULL);
dma_perform((uint32_t)buffer, DMA_NAND, size, 0, &controller, &channel);
if(dma_finish(controller, channel, 500) != 0) {
bufferPrintf("nand: dma timed out\r\n");
return ERROR_TIMEOUT;
}
if(wait_for_status_bit_3(500) != 0) {
bufferPrintf("nand: waiting for status bit 3 timed out\r\n");
return ERROR_TIMEOUT;
}
SET_REG(NAND + NAND_CON, NAND_CON_SETTING1);
CleanAndInvalidateCPUDataCache();
return 0;
}
