void *poll_modbus(void *ctx_p) {
int retval;
modbus_t *ctx = (modbus_t *) ctx_p;
/* Bring data into buffer */
while (1) {
/* TCP requests - may block */
GET_REGS(826, 826);
GET_REGS(352, 353);
GET_REGS(902, 902);
if (retval < 0) {
printf("modbus: Error on poll\n");
/* Attempt reconnect */
modbus_close(ctx);
if (modbus_connect(ctx) == -1) {
/* Kill the process */
exit(1);
}
}
pthread_mutex_lock(&modbus_lock);
modbus_data = priv_modbus_data;
pthread_mutex_unlock(&modbus_lock);
usleep(MODBUS_POLL_INTERVAL_US);
}
}
/**
* Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
* registers.
*/
static void ep93xx_eth_close(struct eth_device *dev)
{
struct mac_regs *mac = GET_REGS(dev);
debug("+ep93xx_eth_close");
writel(0x00000000, &mac->rxctl);
writel(0x00000000, &mac->txctl);
debug("-ep93xx_eth_close");
}
/**
* Send a block of data via ethernet.
*/
static int ep93xx_eth_send_packet(struct eth_device *dev,
volatile void * const packet, int const length)
{
struct mac_regs *mac = GET_REGS(dev);
struct ep93xx_priv *priv = GET_PRIV(dev);
int ret = -1;
debug("+ep93xx_eth_send_packet");
/* Parameter check */
BUG_ON(packet == NULL);
/*
* Initialize the TX descriptor queue with the new packet's info.
* Clear the associated status queue entry. Enqueue the packet
* to the MAC for transmission.
*/
/* set buffer address */
priv->tx_dq.current->word1 = (uint32_t)packet;
/* set buffer length and EOF bit */
priv->tx_dq.current->word2 = length | TX_DESC_EOF;
/* clear tx status */
priv->tx_sq.current->word1 = 0;
/* enqueue the TX descriptor */
writel(1, &mac->txdqenq);
/* wait for the frame to become processed */
while (!TX_STATUS_TXFP(priv->tx_sq.current))
; /* noop */
if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
error("packet tx error, status %08X",
priv->tx_sq.current->word1);
dump_tx_descriptor_queue(dev);
dump_tx_status_queue(dev);
/* TODO: Add better error handling? */
goto eth_send_out;
}
ret = 0;
/* Fall through */
eth_send_out:
debug("-ep93xx_eth_send_packet %d", ret);
return ret;
}
/**
* Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
* it's cleared.
*/
static void ep93xx_mac_reset(struct eth_device *dev)
{
struct mac_regs *mac = GET_REGS(dev);
uint32_t value;
debug("+ep93xx_mac_reset");
value = readl(&mac->selfctl);
value |= SELFCTL_RESET;
writel(value, &mac->selfctl);
while (readl(&mac->selfctl) & SELFCTL_RESET)
; /* noop */
debug("-ep93xx_mac_reset");
}
/**
* Copy a frame of data from the MAC into the protocol layer for further
* processing.
*/
static int ep93xx_eth_rcv_packet(struct eth_device *dev)
{
struct mac_regs *mac = GET_REGS(dev);
struct ep93xx_priv *priv = GET_PRIV(dev);
int len = -1;
debug("+ep93xx_eth_rcv_packet");
if (RX_STATUS_RFP(priv->rx_sq.current)) {
if (RX_STATUS_RWE(priv->rx_sq.current)) {
/*
* We have a good frame. Extract the frame's length
* from the current rx_status_queue entry, and copy
* the frame's data into NetRxPackets[] of the
* protocol stack. We track the total number of
* bytes in the frame (nbytes_frame) which will be
* used when we pass the data off to the protocol
* layer via NetReceive().
*/
len = RX_STATUS_FRAME_LEN(priv->rx_sq.current);
NetReceive((uchar *)priv->rx_dq.current->word1, len);
debug("reporting %d bytes...\n", len);
} else {
/* Do we have an erroneous packet? */
error("packet rx error, status %08X %08X",
priv->rx_sq.current->word1,
priv->rx_sq.current->word2);
dump_rx_descriptor_queue(dev);
dump_rx_status_queue(dev);
}
/*
* Clear the associated status queue entry, and
* increment our current pointers to the next RX
* descriptor and status queue entries (making sure
* we wrap properly).
*/
memset((void *)priv->rx_sq.current, 0,
sizeof(struct rx_status));
priv->rx_sq.current++;
if (priv->rx_sq.current >= priv->rx_sq.end)
priv->rx_sq.current = priv->rx_sq.base;
priv->rx_dq.current++;
if (priv->rx_dq.current >= priv->rx_dq.end)
priv->rx_dq.current = priv->rx_dq.base;
/*
* Finally, return the RX descriptor and status entries
* back to the MAC engine, and loop again, checking for
* more descriptors to process.
*/
writel(1, &mac->rxdqenq);
writel(1, &mac->rxstsqenq);
} else {
len = 0;
}
debug("-ep93xx_eth_rcv_packet %d", len);
return len;
}
/* Eth device open */
static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd)
{
struct ep93xx_priv *priv = GET_PRIV(dev);
struct mac_regs *mac = GET_REGS(dev);
uchar *mac_addr = dev->enetaddr;
int i;
debug("+ep93xx_eth_open");
/* Reset the MAC */
ep93xx_mac_reset(dev);
/* Reset the descriptor queues' current and end address values */
priv->tx_dq.current = priv->tx_dq.base;
priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
priv->tx_sq.current = priv->tx_sq.base;
priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
priv->rx_dq.current = priv->rx_dq.base;
priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
priv->rx_sq.current = priv->rx_sq.base;
priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
/*
* Set the transmit descriptor and status queues' base address,
* current address, and length registers. Set the maximum frame
* length and threshold. Enable the transmit descriptor processor.
*/
writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd);
writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd);
writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen);
writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd);
writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd);
writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen);
writel(0x00040000, &mac->txdthrshld);
writel(0x00040000, &mac->txststhrshld);
writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen);
writel(BMCTL_TXEN, &mac->bmctl);
/*
* Set the receive descriptor and status queues' base address,
* current address, and length registers. Enable the receive
* descriptor processor.
*/
writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd);
writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd);
writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen);
writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd);
writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd);
writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen);
writel(0x00040000, &mac->rxdthrshld);
writel(BMCTL_RXEN, &mac->bmctl);
writel(0x00040000, &mac->rxststhrshld);
/* Wait until the receive descriptor processor is active */
while (!(readl(&mac->bmsts) & BMSTS_RXACT))
; /* noop */
/*
* Initialize the RX descriptor queue. Clear the TX descriptor queue.
* Clear the RX and TX status queues. Enqueue the RX descriptor and
* status entries to the MAC.
*/
for (i = 0; i < NUMRXDESC; i++) {
/* set buffer address */
(priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i];
/* set buffer length, clear buffer index and NSOF */
(priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;
}
memset(priv->tx_dq.base, 0,
(sizeof(struct tx_descriptor) * NUMTXDESC));
memset(priv->rx_sq.base, 0,
(sizeof(struct rx_status) * NUMRXDESC));
memset(priv->tx_sq.base, 0,
(sizeof(struct tx_status) * NUMTXDESC));
writel(NUMRXDESC, &mac->rxdqenq);
writel(NUMRXDESC, &mac->rxstsqenq);
/* Set the primary MAC address */
writel(AFP_IAPRIMARY, &mac->afp);
writel(mac_addr[0] | (mac_addr[1] << 8) |
(mac_addr[2] << 16) | (mac_addr[3] << 24),
&mac->indad);
writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper);
/* Turn on RX and TX */
writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
RXCTL_RCRCA | RXCTL_MA, &mac->rxctl);
writel(TXCTL_STXON, &mac->txctl);
/* Dump data structures if we're debugging */
dump_dev(dev);
dump_rx_descriptor_queue(dev);
dump_rx_status_queue(dev);
dump_tx_descriptor_queue(dev);
dump_tx_status_queue(dev);
debug("-ep93xx_eth_open");
return 1;
}
