static void gic_it_set_prio(struct gic_data *gd, size_t it, uint8_t prio) { size_t idx __maybe_unused = it / NUM_INTS_PER_REG; uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG); /* Assigned to group0 */ assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); /* Set prio it to selected CPUs */ DMSG("prio: writing 0x%x to 0x%" PRIxVA, prio, gd->gicd_base + GICD_IPRIORITYR(0) + it); write8(prio, gd->gicd_base + GICD_IPRIORITYR(0) + it); }
void gic_it_set_prio(size_t it, uint8_t prio) { size_t idx = it / NUM_INTS_PER_REG; uint32_t mask = 1 << (it % NUM_INTS_PER_REG); assert(it <= gic.max_it); /* Not too large */ /* Assigned to group0 */ assert(!(read32(gic.gicd_base + GICD_IGROUPR(idx)) & mask)); /* Set prio it to selected CPUs */ DMSG("prio: writing 0x%x to 0x%" PRIxVA, prio, gic.gicd_base + GICD_IPRIORITYR(0) + it); write8(prio, gic.gicd_base + GICD_IPRIORITYR(0) + it); }
/** * \fn init_gic_distributor * * Initialise GIC Dirstributor. * * Configure all IRQs to be active low, level sensitive, target cpu0, * priority 0xa0 and disable all interrupts. */ void init_gic_distributor() { GICD[GICD_CTLR] = 0x0; // disable GIC unsigned int typer = GICD[GICD_TYPER]; unsigned int lines = 32 * ((typer & 0x1F) + 1); unsigned int i; /* set global interrupts to active low, level sensitive */ for (i = 32; i < lines; i += 16) { GICD[GICD_ICFGR(i / 16)] = 0x0; } for (i = 32; i < lines; i += 4) { GICD[GICD_ITARGETSR(i / 4)] = 0x01010101; } for (i = 32; i < lines; i += 4) { GICD[GICD_IPRIORITYR(i / 4)] = 0xa0a0a0a0; } for (i = 32; i < lines; i += 32) { GICD[GICD_ICENABLER(i / 32)] = 0xFFFFFFFF; } for (i = 32; i < lines; i += 32) { GICD[GICD_IGROUPR(i / 32)] = 0x0; } GICD[GICD_CTLR] = 0x0; }
/** * \fn init_gic_cpu * * Initialise GIC CPU interface */ void init_gic_cpu() { unsigned int i; GICD[GICD_ICENABLER(0)] = 0xFFFF0000; GICD[GICD_ISENABLER(0)] = 0x0000FFFF; for (i = 0; i < 128; i += 4) GICD[GICD_IPRIORITYR(i / 4)] = 0xa0a0a0a0; GICC[GICC_PMR] = 0xff; GICC[GICC_BPR] = 0; GICC[GICC_CTLR] = 0x201; }
/* * ディストリビュータの初期化 */ void gicd_initialize(void) { int i; /* * ディストリビュータをディスエーブル */ sil_wrw_mem(GICD_CTLR, GICD_CTLR_DISABLE); #ifdef TOPPERS_SAFEG_SECURE /* * すべての割込みをグループ1(IRQ)に設定 */ for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) { sil_wrw_mem(GICD_IGROUPR(i), 0xffffffffU); } #endif /* TOPPERS_SAFEG_SECURE */ /* * すべての割込みを禁止 */ for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) { sil_wrw_mem(GICD_ICENABLER(i), 0xffffffffU); } /* * すべての割込みペンディングをクリア */ for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) { sil_wrw_mem(GICD_ICPENDR(i), 0xffffffffU); } /* * すべての割込みを最低優先度に設定 */ for (i = 0; i < (GIC_TNUM_INTNO + 3) / 4; i++){ sil_wrw_mem(GICD_IPRIORITYR(i), 0xffffffffU); } /* * すべての共有ペリフェラル割込みのターゲットをプロセッサ0に設定 */ for (i = GIC_INTNO_SPI0 / 4; i < (GIC_TNUM_INTNO + 3) / 4; i++) { sil_wrw_mem(GICD_ITARGETSR(i), 0x01010101U); } /* * すべてのペリフェラル割込みをレベルトリガに設定 */ for (i = GIC_INTNO_PPI0 / 16; i < (GIC_TNUM_INTNO + 15) / 16; i++) { #ifdef GIC_ARM11MPCORE sil_wrw_mem(GICD_ICFGR(i), 0x55555555U); #else /* GIC_ARM11MPCORE */ sil_wrw_mem(GICD_ICFGR(i), 0x00000000U); #endif /* GIC_ARM11MPCORE */ } /* * ディストリビュータをイネーブル */ sil_wrw_mem(GICD_CTLR, GICD_CTLR_ENABLE); }
/** * \fn enable_irq(unsigned int irqn) * * Enable IRQ in GICD, setting target CPU to cpu0 and priority to 0xa0 */ void enable_irq(unsigned int irqn) { GICD[GICD_ISENABLER(irqn / 32)] = 1 << (irqn % 32); GICD[GICD_ITARGETSR(irqn / 4)] |= (0x01 << ((irqn % 4) * 8)); GICD[GICD_IPRIORITYR(irqn / 4)] |= (0xa0 << ((irqn % 4) * 8)); }