void samv71EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
{
//Set up a write operation
uint32_t value = GMAC_MAN_CLTTO | GMAC_MAN_OP(1) | GMAC_MAN_WTN(2);
//PHY address
value |= GMAC_MAN_PHYA(phyAddr);
//Register address
value |= GMAC_MAN_REGA(regAddr);
//Register value
value |= GMAC_MAN_DATA(data);
//Start a write operation
GMAC->GMAC_MAN = value;
//Wait for the write to complete
while(!(GMAC->GMAC_NSR & GMAC_NSR_IDLE));
}
uint16_t samv71EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
{
//Set up a read operation
uint32_t value = GMAC_MAN_CLTTO | GMAC_MAN_OP(2) | GMAC_MAN_WTN(2);
//PHY address
value |= GMAC_MAN_PHYA(phyAddr);
//Register address
value |= GMAC_MAN_REGA(regAddr);
//Start a read operation
GMAC->GMAC_MAN = value;
//Wait for the read to complete
while(!(GMAC->GMAC_NSR & GMAC_NSR_IDLE));
//Return PHY register contents
return GMAC->GMAC_MAN & GMAC_MAN_DATA_Msk;
}
bool gmac_phy_write(Gmac* gmac, uint8_t phy_addr, uint8_t reg_addr, uint16_t data,
uint32_t retries)
{
/* Wait until idle */
if (!_gmac_phy_wait_idle(gmac, retries))
return false;
/* Write maintenance register */
gmac->GMAC_MAN = GMAC_MAN_CLTTO |
GMAC_MAN_OP(1) |
GMAC_MAN_WTN(2) |
GMAC_MAN_PHYA(phy_addr) |
GMAC_MAN_REGA(reg_addr) |
GMAC_MAN_DATA(data);
/* Wait until idle */
return _gmac_phy_wait_idle(gmac, retries);
}
bool gmac_phy_read(Gmac* gmac, uint8_t phy_addr, uint8_t reg_addr, uint16_t* data,
uint32_t retries)
{
/* Wait until idle */
if (!_gmac_phy_wait_idle(gmac, retries))
return false;
/* Write maintenance register */
gmac->GMAC_MAN = GMAC_MAN_CLTTO |
GMAC_MAN_OP(2) |
GMAC_MAN_WTN(2) |
GMAC_MAN_PHYA(phy_addr) |
GMAC_MAN_REGA(reg_addr);
/* Wait until idle */
if (!_gmac_phy_wait_idle(gmac, retries))
return false;
*data = (gmac->GMAC_MAN & GMAC_MAN_DATA_Msk) >> GMAC_MAN_DATA_Pos;
return true;
}