void gpio_config(GPIO_ConfigTypeDef *pGPIOConfig)
{
uint32 gpio_pin_mask = pGPIOConfig->GPIO_Pin;
uint32 gpio_pin_mask_high = pGPIOConfig->GPIO_Pin_high;
uint32 io_reg;
uint8 io_num = 0;
uint32 pin_reg;
uint32 bit_valid;
if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Input) {
GPIO_AS_INPUT(gpio_pin_mask);
GPIO_AS_INPUT_HIGH(gpio_pin_mask_high);
} else if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Output) {
GPIO_AS_OUTPUT(gpio_pin_mask);
GPIO_AS_OUTPUT_HIGH(gpio_pin_mask_high);
}
do {
bit_valid = (io_num >= 32 ? (gpio_pin_mask_high & (0x1 << (io_num - 32))) : (gpio_pin_mask & (0x1 << io_num)));
if (bit_valid && (io_reg = GPIO_PIN_REG[io_num])) {
if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Input) {
SET_PERI_REG_MASK(io_reg, FUN_IE);
}
//for ESP32 function 2 of every pad is allways GPIO func
PIN_FUNC_SELECT(io_reg, 2);
if (pGPIOConfig->GPIO_Pullup) {
PIN_PULLUP_EN(io_reg);
} else {
PIN_PULLUP_DIS(io_reg);
}
if (pGPIOConfig->GPIO_Pulldown) {
PIN_PULLDWN_EN(io_reg);
} else {
PIN_PULLDWN_DIS(io_reg);
}
if (pGPIOConfig->GPIO_Mode == GPIO_Mode_Out_OD) {
portENTER_CRITICAL();
pin_reg = GPIO_REG_READ(GPIO_PIN_ADDR(io_num));
//pin_reg &= (~GPIO_GPIO_PIN0_PAD_DRIVER);
pin_reg |= GPIO_GPIO_PIN0_PAD_DRIVER;
GPIO_REG_WRITE(GPIO_PIN_ADDR(io_num), pin_reg);
portEXIT_CRITICAL();
}
gpio_pin_intr_state_set(io_num, pGPIOConfig->GPIO_IntrType);
}
io_num++;
} while (io_num < GPIO_PIN_COUNT);
}
static void pinMode(uint8_t pin, uint8_t mode)
{
if (pin < 16) // only for GPIO0 to GPIO15, GPIO16 is special
{
if (mode == OUTPUT)
{
GPIO_AS_OUTPUT(1 << pin);
}
else // INPUT
{
GPIO_AS_INPUT(1 << pin);
}
}
}
//Initialize I2S subsystem for DMA circular buffer use
void ICACHE_FLASH_ATTR i2sInit() {
int x, y;
underrunCnt=0;
//First, take care of the DMA buffers.
for (y=0; y<I2SDMABUFCNT; y++) {
//Allocate memory for this DMA sample buffer.
i2sBuf[y]=malloc(I2SDMABUFLEN*4);
//Clear sample buffer. We don't want noise.
for (x=0; x<I2SDMABUFLEN; x++) {
i2sBuf[y][x]=0;
}
}
//Reset DMA
SET_PERI_REG_MASK(SLC_CONF0, SLC_RXLINK_RST|SLC_TXLINK_RST);
CLEAR_PERI_REG_MASK(SLC_CONF0, SLC_RXLINK_RST|SLC_TXLINK_RST);
//Clear DMA int flags
SET_PERI_REG_MASK(SLC_INT_CLR, 0xffffffff);
CLEAR_PERI_REG_MASK(SLC_INT_CLR, 0xffffffff);
//Enable and configure DMA
CLEAR_PERI_REG_MASK(SLC_CONF0, (SLC_MODE<<SLC_MODE_S));
SET_PERI_REG_MASK(SLC_CONF0,(1<<SLC_MODE_S));
SET_PERI_REG_MASK(SLC_RX_DSCR_CONF,SLC_INFOR_NO_REPLACE|SLC_TOKEN_NO_REPLACE);
CLEAR_PERI_REG_MASK(SLC_RX_DSCR_CONF, SLC_RX_FILL_EN|SLC_RX_EOF_MODE | SLC_RX_FILL_MODE);
//Initialize DMA buffer descriptors in such a way that they will form a circular
//buffer.
for (x=0; x<I2SDMABUFCNT; x++) {
i2sBufDesc[x].owner=1;
i2sBufDesc[x].eof=1;
i2sBufDesc[x].sub_sof=0;
i2sBufDesc[x].datalen=I2SDMABUFLEN*4;
i2sBufDesc[x].blocksize=I2SDMABUFLEN*4;
i2sBufDesc[x].buf_ptr=(uint32_t)&i2sBuf[x][0];
i2sBufDesc[x].unused=0;
i2sBufDesc[x].next_link_ptr=(int)((x<(I2SDMABUFCNT-1))?(&i2sBufDesc[x+1]):(&i2sBufDesc[0]));
}
//Feed dma the 1st buffer desc addr
//To send data to the I2S subsystem, counter-intuitively we use the RXLINK part, not the TXLINK as you might
//expect. The TXLINK part still needs a valid DMA descriptor, even if it's unused: the DMA engine will throw
//an error at us otherwise. Just feed it any random descriptor.
CLEAR_PERI_REG_MASK(SLC_TX_LINK,SLC_TXLINK_DESCADDR_MASK);
SET_PERI_REG_MASK(SLC_TX_LINK, ((uint32)&i2sBufDesc[1]) & SLC_TXLINK_DESCADDR_MASK); //any random desc is OK, we don't use TX but it needs something valid
CLEAR_PERI_REG_MASK(SLC_RX_LINK,SLC_RXLINK_DESCADDR_MASK);
SET_PERI_REG_MASK(SLC_RX_LINK, ((uint32)&i2sBufDesc[0]) & SLC_RXLINK_DESCADDR_MASK);
//Attach the DMA interrupt
_xt_isr_attach(ETS_SLC_INUM, (_xt_isr)slc_isr, NULL);
//Enable DMA operation intr
WRITE_PERI_REG(SLC_INT_ENA, SLC_RX_EOF_INT_ENA);
//clear any interrupt flags that are set
WRITE_PERI_REG(SLC_INT_CLR, 0xffffffff);
///enable DMA intr in cpu
_xt_isr_unmask(1<<ETS_SLC_INUM);
//We use a queue to keep track of the DMA buffers that are empty. The ISR will push buffers to the back of the queue,
//the mp3 decode will pull them from the front and fill them. For ease, the queue will contain *pointers* to the DMA
//buffers, not the data itself. The queue depth is one smaller than the amount of buffers we have, because there's
//always a buffer that is being used by the DMA subsystem *right now* and we don't want to be able to write to that
//simultaneously.
dmaQueue=xQueueCreate(I2SDMABUFCNT-1, sizeof(int*));
//Start transmission
SET_PERI_REG_MASK(SLC_TX_LINK, SLC_TXLINK_START);
SET_PERI_REG_MASK(SLC_RX_LINK, SLC_RXLINK_START);
//----
//Init pins to i2s functions
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_I2SO_DATA);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_I2SO_WS);
#ifndef USE_ESP01_MODULE
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_I2SO_BCK);
#else
GPIO_AS_INPUT(1<<15);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_GPIO15);
#endif
//Enable clock to i2s subsystem
i2c_writeReg_Mask_def(i2c_bbpll, i2c_bbpll_en_audio_clock_out, 1);
//Reset I2S subsystem
CLEAR_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
SET_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
CLEAR_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
//Select 16bits per channel (FIFO_MOD=0), no DMA access (FIFO only)
CLEAR_PERI_REG_MASK(I2S_FIFO_CONF, I2S_I2S_DSCR_EN|(I2S_I2S_RX_FIFO_MOD<<I2S_I2S_RX_FIFO_MOD_S)|(I2S_I2S_TX_FIFO_MOD<<I2S_I2S_TX_FIFO_MOD_S));
//Enable DMA in i2s subsystem
SET_PERI_REG_MASK(I2S_FIFO_CONF, I2S_I2S_DSCR_EN);
//tx/rx binaureal
CLEAR_PERI_REG_MASK(I2SCONF_CHAN, (I2S_TX_CHAN_MOD<<I2S_TX_CHAN_MOD_S)|(I2S_RX_CHAN_MOD<<I2S_RX_CHAN_MOD_S));
//Clear int
SET_PERI_REG_MASK(I2SINT_CLR, I2S_I2S_TX_REMPTY_INT_CLR|I2S_I2S_TX_WFULL_INT_CLR|
I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
CLEAR_PERI_REG_MASK(I2SINT_CLR, I2S_I2S_TX_REMPTY_INT_CLR|I2S_I2S_TX_WFULL_INT_CLR|
I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
//trans master&rece slave,MSB shift,right_first,msb right
CLEAR_PERI_REG_MASK(I2SCONF, I2S_TRANS_SLAVE_MOD|
(I2S_BITS_MOD<<I2S_BITS_MOD_S)|
(I2S_BCK_DIV_NUM <<I2S_BCK_DIV_NUM_S)|
(I2S_CLKM_DIV_NUM<<I2S_CLKM_DIV_NUM_S));
SET_PERI_REG_MASK(I2SCONF, I2S_RIGHT_FIRST|I2S_MSB_RIGHT|I2S_RECE_SLAVE_MOD|
I2S_RECE_MSB_SHIFT|I2S_TRANS_MSB_SHIFT|
((16&I2S_BCK_DIV_NUM )<<I2S_BCK_DIV_NUM_S)|
((7&I2S_CLKM_DIV_NUM)<<I2S_CLKM_DIV_NUM_S));
//No idea if ints are needed...
//clear int
SET_PERI_REG_MASK(I2SINT_CLR, I2S_I2S_TX_REMPTY_INT_CLR|I2S_I2S_TX_WFULL_INT_CLR|
I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
CLEAR_PERI_REG_MASK(I2SINT_CLR, I2S_I2S_TX_REMPTY_INT_CLR|I2S_I2S_TX_WFULL_INT_CLR|
I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
//enable int
SET_PERI_REG_MASK(I2SINT_ENA, I2S_I2S_TX_REMPTY_INT_ENA|I2S_I2S_TX_WFULL_INT_ENA|
I2S_I2S_RX_REMPTY_INT_ENA|I2S_I2S_TX_PUT_DATA_INT_ENA|I2S_I2S_RX_TAKE_DATA_INT_ENA);
//Start transmission
SET_PERI_REG_MASK(I2SCONF,I2S_I2S_TX_START);
}
//-----------------------------------------------------------------------------------------
void static dht11_protocol(uint32 gpio_status,int cause)
{
static int actual_bit;
switch(cause) // 0 = gpio interrupt, 1=timer
{
case 0: // gpio edge
{
// disable interrupt for GPIO
gpio_pin_intr_state_set(GPIO_ID_PIN(dht11_gpio), GPIO_PIN_INTR_DISABLE);
// clear interrupt status for GPIO
GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, gpio_status & GPIO_Pin(dht11_gpio));
// Reactivate interrupts for GPIO0
gpio_pin_intr_state_set(GPIO_ID_PIN(dht11_gpio), GPIO_PIN_INTR_ANYEGDE);
switch(sStatus)
{
case dht11_connecting:
if(GPIO_INPUT_GET(dht11_gpio))
{
// Rising edge ?? Error.
dht11_set_read_nok();
dht11_set_standby();
}
else
{
sStatus = dht11_mark_connecting;
}
break;
case dht11_mark_connecting:
if(!GPIO_INPUT_GET(dht11_gpio))
{
// Falling edge ?? Error.
dht11_set_read_nok();
dht11_set_standby();
}
else
{
sStatus = dht11_waiting_bit;
}
break;
case dht11_waiting_bit:
if(GPIO_INPUT_GET(dht11_gpio))
{
// Rising edge ?? Error.
dht11_set_read_nok();
dht11_set_standby();
}
else
{
sStatus = dht11_mark_bit;
actual_bit=0;
}
break;
case dht11_mark_bit:
if(! GPIO_INPUT_GET(dht11_gpio))
{
// Falling edge ?? Error.
dht11_set_read_nok();
dht11_set_standby();
}
else
{
if(actual_bit >= 40)
{
dht11_set_standby(); // finish OK
}
else
{
last_timer = system_get_time();
sStatus = dht11_read_bit;
}
}
break;
case dht11_read_bit:
if(GPIO_INPUT_GET(dht11_gpio))
{
// Rising edge ?? Error.
dht11_set_read_nok();
dht11_set_standby();
}
else
{
// 26-28 uS means 0. 70 uS means 1
int bit_data = ((system_get_time()-last_timer) > 40) ? 1:0;
int actual_byte = actual_bit / 8;
sRead[actual_byte] <<= 1;
sRead[actual_byte] |= bit_data;
actual_bit++;
sStatus = dht11_mark_bit;
}
break;
case dht11_standby:
case dht11_mark:
default:
dht11_set_standby();
break;
}
}
break;
case 1: //timer
switch(sStatus)
{
case dht11_mark: // end of mark
sStatus = dht11_connecting;
// GPIO as Output to high level by default.
GPIO_OUTPUT_SET(dht11_gpio,1);
GPIO_AS_INPUT(dht11_gpio);
ETS_GPIO_INTR_DISABLE();
gpio_register_set(GPIO_PIN_ADDR(dht11_gpio),
GPIO_PIN_INT_TYPE_SET(GPIO_PIN_INTR_DISABLE) |
GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_DISABLE) |
GPIO_PIN_SOURCE_SET(GPIO_AS_PIN_SOURCE));
GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(dht11_gpio));
gpio_pin_intr_state_set(GPIO_ID_PIN(dht11_gpio), GPIO_PIN_INTR_ANYEGDE);
ETS_GPIO_INTR_ENABLE();
os_timer_disarm(&dht11_timer);
os_timer_arm(&dht11_timer,6,0); // maximun frame time 4.8 ms
break;
case dht11_connecting:
case dht11_mark_connecting:
case dht11_waiting_bit:
case dht11_mark_bit:
case dht11_read_bit:
default:
dht11_set_read_nok();
dht11_set_standby();
break;
}
default:
break;
}
}
