/*!
* @brief 初始化gpio
* @param PTxn 端口
* @param cfg 引脚方向,0=输入,1=输出
* @param data 输出初始状态,0=低电平,1=高电平 （对输入无效）
* @since v5.0
* Sample usage: gpio_init (PTA8, GPI,0); //初始化 PTA8 管脚为输入
*/
void gpio_init (PTXn_e ptxn, GPIO_CFG cfg, uint8 data)
{
//复用管脚为GPIO功能
port_init( ptxn, ALT1);
//端口方向控制输入还是输出
if( cfg == GPI )
{
//设置端口方向为输入
GPIO_PDDR_REG(GPIOX_BASE(ptxn)) &= ~(1 << PTn(ptxn)); // GPIO PDDR 管脚号 清0，即对应管脚配置为端口方向输入
}
else
{
//设置端口方向为输出
GPIO_PDDR_REG(GPIOX_BASE(ptxn)) |= (1 << PTn(ptxn)); // GPIO PDDR 管脚号 置1，即对应管脚配置为端口方向输出
//端口输出数据
if(data == 0)
{
GPIO_PDOR_REG(GPIOX_BASE(ptxn)) &= ~(1 << PTn(ptxn)); // GPIO PDOR 管脚号 清0，即对应管脚配置为端口输出低电平
}
else
{
GPIO_PDOR_REG(GPIOX_BASE(ptxn)) |= (1 << PTn(ptxn)); // GPIO PDOR 管脚号 置1，即对应管脚配置为端口输出高电平
}
}
}
/*!
* @brief 设置引脚状态
* @param PTxn 端口
* @param data 输出初始状态,0=低电平,1=高电平 （对输入无效）
* @since v5.0
* @warning 务必保证数据方向为输出（DEBUG模式下，有断言进行检测）
* Sample usage: gpio_set (PTA8, 1); // PTA8 管脚 输出 1
*/
void gpio_set (PTXn_e ptxn, uint8 data)
{
ASSERT( BIT_GET( GPIO_PDDR_REG(GPIOX_BASE(ptxn)) , PTn(ptxn)) == GPO ); // 断言，检测 输出方向是否为输出
// 获取 GPIO PDDR 管脚号 ，比较是否为输出
//端口输出数据
if(data == 0)
{
GPIO_PDOR_REG(GPIOX_BASE(ptxn)) &= ~(1 << PTn(ptxn)); // GPIO PDOR 管脚号 清0，即对应管脚配置为端口输出低电平
}
else
{
GPIO_PDOR_REG(GPIOX_BASE(ptxn)) |= (1 << PTn(ptxn)); // GPIO PDOR 管脚号 置1，即对应管脚配置为端口输出高电平
}
}
//Beep引脚初始化
//PTB2初始输出高电平
//
void BeepInit(void)
{
//指定该引脚功能为GPIO功能（即令引脚控制寄存器的MUX=0b001）
PORT_PCR_REG(PORTB_BASE_PTR, 2)= 0 ;
PORT_PCR_REG(PORTB_BASE_PTR, 2)= PORT_PCR_MUX(1);
GPIO_PDDR_REG(PTB_BASE_PTR) |= (1 << 2); //设置端口方向为输出
GPIO_PDOR_REG(PTB_BASE_PTR) |= (1 << 2); //设置输出为高电平
}
_mqx_int _bsp_usb_io_init
(
void
)
{
#if PE_LDD_VERSION
/* USB clock is configured using CPU component */
/* Check if peripheral is not used by Processor Expert USB_LDD component */
if (PE_PeripheralUsed((uint32_t)USB0_BASE_PTR) == TRUE) {
/* IO Device used by PE Component*/
return IO_ERROR;
}
/**
* Workaround for Processor Expert as USB clock divider settings has been removed
* from __pe_initialize_hardware() and Cpu_SetClockConfiguration() functions
* Needs to be replaced by dynamic calculation of dividers.
* SIM_CLKDIV2: USBDIV=1,USBFRAC=0
*/
SIM_CLKDIV2 = (uint32_t)((SIM_CLKDIV2 & (uint32_t)~0x0DUL) | (uint32_t)0x02UL); /* Update USB clock prescalers */
#endif
#if BSPCFG_USB_USE_IRC48M
/*
* Configure SIM_CLKDIV2: USBDIV = 0, USBFRAC = 0
*/
SIM_CLKDIV2 = (uint32_t)0x0UL; /* Update USB clock prescalers */
/* Configure USB to be clocked from IRC 48MHz */
SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(3);
/* Enable USB-OTG IP clocking */
SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK;
/* Enable IRC 48MHz for USB module */
USB0_CLK_RECOVER_IRC_EN = 0x03;
#else
/* Configure USB to be clocked from PLL */
SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(1);
/* Enable USB-OTG IP clocking */
SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK;
/* USB D+ and USB D- are standalone not multiplexed one-purpose pins */
/* VREFIN for device is standalone not multiplexed one-purpose pin */
#endif
#if BSP_USB_TWR_SER2
/* TWR-SER2 board has 2 connectors: on channel A, there is Micro-USB connector,
** which is not routed to TWRK64 board. On channel B, there is standard
** A-type host connector routed to the USB0 peripheral on TWRK64. To enable
** power to this connector, GPIO PB8 must be set as GPIO output
*/
PORT_PCR_REG(PORTB_BASE_PTR, 8) = PORT_PCR_MUX(0x01);
GPIO_PDDR_REG(PTB_BASE_PTR) |= 1 << 8; // PB8 as output
GPIO_PDOR_REG(PTB_BASE_PTR) |= 1 << 8; // PB8 in high level
#endif
return MQX_OK;
}
_mqx_int _bsp_usb_io_init
(
void
)
{
#if PE_LDD_VERSION
/* USB clock is configured using CPU component */
/* Check if peripheral is not used by Processor Expert USB_LDD component */
if (PE_PeripheralUsed((uint32_t)USB0_BASE_PTR) == TRUE) {
/* IO Device used by PE Component*/
return IO_ERROR;
}
/**
* Workaround for Processor Expert as USB clock divider settings has been removed
* from __pe_initialize_hardware() and Cpu_SetClockConfiguration() functions
* Needs to be replaced by dynamic calculation of dividers.
* SIM_CLKDIV2: USBDIV=1,USBFRAC=0
*/
SIM_CLKDIV2 = (uint32_t)((SIM_CLKDIV2 & (uint32_t)~0x0DUL) | (uint32_t)0x02UL); /* Update USB clock prescalers */
#endif
/* Configure USB to be clocked from PLL */
SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK;
/* Enable USB-OTG IP clocking */
SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK;
/* USB D+ and USB D- are standalone not multiplexed one-purpose pins */
/* VREFIN for device is standalone not multiplexed one-purpose pin */
/** If we need the USB working as a host we have to provide
** power to the USB connector. To do this PTC9 has to be set
** as a GPIO output in high level.
** If USB should work as a device, the J26 jumper should be removed.
*/
PORT_PCR_REG(PORTC_BASE_PTR, 9) = PORT_PCR_MUX(0x01) | PORT_PCR_PE_MASK;
GPIO_PDDR_REG(PTC_BASE_PTR) |= 0x00000200; // PTC9 as output
GPIO_PDOR_REG(PTC_BASE_PTR) |= 0x00000200; // PTC9 in high level
return MQX_OK;
}
_mqx_int _bsp_usb_host_io_init
(
struct usb_host_if_struct *dev_if
)
{
if (dev_if->HOST_INIT_PARAM == &_khci0_host_init_param)
{
_bsp_usb_io_init();
/* Set pin to enable power supply to on board usb conector */
PORT_PCR_REG(PORTC_BASE_PTR, 9) = PORT_PCR_MUX(0x01) | PORT_PCR_PE_MASK;
GPIO_PDDR_REG(PTC_BASE_PTR) |= 0x00000200; // PC9 as output
GPIO_PDOR_REG(PTC_BASE_PTR) |= 0x00000200; // PC9 in high level
}
else
{
return IO_ERROR; //unknown controller
}
return MQX_OK;
}
_mqx_int _bsp_usb_io_init
(
void
)
{
#if PE_LDD_VERSION
/* USB clock is configured using CPU component */
/* Check if peripheral is not used by Processor Expert USB_LDD component */
if (PE_PeripheralUsed((uint_32)USB0_BASE_PTR) == TRUE) {
/* IO Device used by PE Component*/
return IO_ERROR;
}
#endif
/* Configure USB to be clocked from PLL */
SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK;
/* Enable USB-OTG IP clocking */
SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK;
/* USB D+ and USB D- are standalone not multiplexed one-purpose pins */
/* VREFIN for device is standalone not multiplexed one-purpose pin */
#if BSP_USB_TWR_SER2
/* TWR-SER2 board has 2 connectors: on channel A, there is Micro-USB connector,
** which is not routed to TWRK60 board. On channel B, there is standard
** A-type host connector routed to the USB0 peripheral on TWRK60. To enable
** power to this connector, GPIO PB8 must be set as GPIO output
*/
PORT_PCR_REG(PORTB_BASE_PTR, 8) = PORT_PCR_MUX(0x01) | PORT_PCR_PE_MASK;
GPIO_PDDR_REG(PTB_BASE_PTR) |= 0x00000100; // PB8 as output
GPIO_PDOR_REG(PTB_BASE_PTR) |= 0x00000100; // PB8 in high level
#endif
return MQX_OK;
}
static _mqx_int _bsp_usb_io_init
(
_mqx_uint i
)
{
if (i == 0) {
#if PE_LDD_VERSION
/* USB clock is configured using CPU component */
/* Check if peripheral is not used by Processor Expert USB_LDD component */
if (PE_PeripheralUsed((uint_32)USB0_BASE_PTR) == TRUE) {
/* IO Device used by PE Component*/
return IO_ERROR;
}
#endif
/* Configure USB to be clocked from PLL0 */
SIM_SOPT2_REG(SIM_BASE_PTR) &= ~(SIM_SOPT2_USBFSRC_MASK);
SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBFSRC(1);
/* Configure USB to be clocked from clock divider */
SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBF_CLKSEL_MASK;
/* Configure USB divider to be 120MHz * 2 / 5 = 48 MHz */
SIM_CLKDIV2_REG(SIM_BASE_PTR) &= ~(SIM_CLKDIV2_USBFSDIV_MASK | SIM_CLKDIV2_USBFSFRAC_MASK);
SIM_CLKDIV2_REG(SIM_BASE_PTR) |= SIM_CLKDIV2_USBFSDIV(4) | SIM_CLKDIV2_USBFSFRAC_MASK;
/* Enable USB-OTG IP clocking */
SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBFS_MASK;
/* USB D+ and USB D- are standalone not multiplexed one-purpose pins */
/* VREFIN for device is standalone not multiplexed one-purpose pin */
#if BSP_USB_TWR_SER2
/* TWR-SER2 board has 2 connectors: on channel A, there is Micro-USB connector,
** which is not routed to TWRK60 board. On channel B, there is standard
** A-type host connector routed to the USB0 peripheral on TWRK60. To enable
** power to this connector, GPIO PB8 must be set as GPIO output
*/
PORT_PCR_REG(PORTB_BASE_PTR, 8) = PORT_PCR_MUX(0x01);
GPIO_PDDR_REG(PTB_BASE_PTR) |= 0x00000100; // PB8 as output
GPIO_PDOR_REG(PTB_BASE_PTR) |= 0x00000100; // PB8 in high level
#endif
}
else if (i == 1) {
//Disable MPU so the module can access RAM
MPU_CESR &= ~MPU_CESR_VLD_MASK;
//Enable clock to the module
SIM_SCGC6 |= SIM_SCGC6_USBHS_MASK;
// SIM_MCR &= (uint32_t)~0x40000000UL; /* Disconnect internal generated ULPI clock from pin */
// SIM_CLKDIV2 |= SIM_CLKDIV2_USBHSFRAC_MASK | SIM_CLKDIV2_USBHSDIV_MASK; // Divide reference clock to obtain 60MHz
// SIM_SOPT2 |= SIM_SOPT2_USBHSRC(1); // MCGPLLCLK for the USB 60MHz CLKC source
//Select external clock for USBH controller
SIM_SOPT2 |= SIM_SOPT2_USBH_CLKSEL_MASK;
PORTA_PCR7 = PORT_PCR_MUX(2); //ULPI DIR
PORTA_PCR8 = PORT_PCR_MUX(2); //ULPI NXT
PORTA_PCR10 = PORT_PCR_MUX(2); //ULPI DATA0
PORTA_PCR11 = PORT_PCR_MUX(2); //ULPI DATA1
PORTA_PCR24 = PORT_PCR_MUX(2); //ULPI DATA2
PORTA_PCR25 = PORT_PCR_MUX(2); //ULPI DATA3
PORTA_PCR26 = PORT_PCR_MUX(2); //ULPI DATA4
PORTA_PCR27 = PORT_PCR_MUX(2); //ULPI DATA5
PORTA_PCR28 = PORT_PCR_MUX(2); //ULPI DATA6
PORTA_PCR29 = PORT_PCR_MUX(2); //ULPI DATA7
PORTA_PCR6 = PORT_PCR_MUX(2); //ULPI CLK
PORTA_PCR9 = PORT_PCR_MUX(2); //ULPI STP
}
else {
return IO_ERROR; //unknow controller
}
return MQX_OK;
}
void Gpio::setValPort (uint32_t value)
{
GPIO_PDOR_REG(portAdr[prt]) = value;
}
/*************************************************************************
* 蓝宙电子工作室
*
* 函数名称：OLED_Init
* 功能说明：初始化函数
* 参数说明：无
* 函数返回：无
* 修改时间：2014-9-13
* 备 注：
*************************************************************************/
void OLED_Init(void)
{
PORT_PCR_REG(PORTE_BASE_PTR, 1)= 0 ;
PORT_PCR_REG(PORTE_BASE_PTR, 1)= PORT_PCR_MUX(1);
GPIO_PDDR_REG(PTE_BASE_PTR) |= (1 << 1);
GPIO_PDOR_REG(PTE_BASE_PTR) |= (1<<(1));
PORT_PCR_REG(PORTE_BASE_PTR, 2)= 0 ;
PORT_PCR_REG(PORTE_BASE_PTR, 2)= PORT_PCR_MUX(1);
GPIO_PDDR_REG(PTE_BASE_PTR) |= (1 << 2);
GPIO_PDOR_REG(PTE_BASE_PTR) |= (1<<(2));
PORT_PCR_REG(PORTE_BASE_PTR, 3)= 0 ;
PORT_PCR_REG(PORTE_BASE_PTR, 3)= PORT_PCR_MUX(1);
GPIO_PDDR_REG(PTE_BASE_PTR) |= (1 << 3);
GPIO_PDOR_REG(PTE_BASE_PTR) |= (1<<(3));
PORT_PCR_REG(PORTE_BASE_PTR, 4)= 0 ;
PORT_PCR_REG(PORTE_BASE_PTR, 4)= PORT_PCR_MUX(1);
GPIO_PDDR_REG(PTE_BASE_PTR) |= (1 << 4);
GPIO_PDOR_REG(PTE_BASE_PTR) |= (1<<(4));
PORT_PCR_REG(PORTE_BASE_PTR, 5)= 0 ;
PORT_PCR_REG(PORTE_BASE_PTR, 5)= PORT_PCR_MUX(1);
GPIO_PDDR_REG(PTE_BASE_PTR) |= (1 << 5);
GPIO_PDOR_REG(PTE_BASE_PTR) |= (1<<(5));
/* gpio_init (PTE1, GPO,HIGH);
gpio_init (PTE2, GPO,HIGH);
gpio_init (PTE3, GPO,HIGH);
gpio_init (PTE4, GPO,HIGH);
gpio_init (PTE5, GPO,LOW);*/
OLED_SCL=1;
OLED_CS = 0 ; ///使能信号端，拉低时正常使用
OLED_RST=0;
OLED_DLY_ms(100);
OLED_RST=1;
OLED_WrCmd(0xae);//--turn off oled panel
OLED_WrCmd(0x00);//---set low column address
OLED_WrCmd(0x10);//---set high column address
OLED_WrCmd(0x40);//--set start line address Set Mapping RAM Display Start Line (0x00~0x3F)
OLED_WrCmd(0x81);//--set contrast control register
OLED_WrCmd(0xcf); // Set SEG Output Current Brightness
OLED_WrCmd(0xa1);//--Set SEG/Column Mapping 0xa0左右反置 0xa1正常
OLED_WrCmd(0xc8);//Set COM/Row Scan Direction 0xc0上下反置 0xc8正常
OLED_WrCmd(0xa6);//--set normal display
OLED_WrCmd(0xa8);//--set multiplex ratio(1 to 64)
OLED_WrCmd(0x3f);//--1/64 duty
OLED_WrCmd(0xd3);//-set display offset Shift Mapping RAM Counter (0x00~0x3F)
OLED_WrCmd(0x00);//-not offset
OLED_WrCmd(0xd5);//--set display clock divide ratio/oscillator frequency
OLED_WrCmd(0x80);//--set divide ratio, Set Clock as 100 Frames/Sec
OLED_WrCmd(0xd9);//--set pre-charge period
OLED_WrCmd(0xf1);//Set Pre-Charge as 15 Clocks & Discharge as 1 Clock
OLED_WrCmd(0xda);//--set com pins hardware configuration
OLED_WrCmd(0x12);
OLED_WrCmd(0xdb);//--set vcomh
OLED_WrCmd(0x40);//Set VCOM Deselect Level
OLED_WrCmd(0x20);//-Set Page Addressing Mode (0x00/0x01/0x02)
OLED_WrCmd(0x02);//
OLED_WrCmd(0x8d);//--set Charge Pump enable/disable
OLED_WrCmd(0x14);//--set(0x10) disable
OLED_WrCmd(0xa4);// Disable Entire Display On (0xa4/0xa5)
OLED_WrCmd(0xa6);// Disable Inverse Display On (0xa6/a7)
OLED_WrCmd(0xaf);//--turn on oled panel
OLED_Fill(0x00); //初始清屏
//OLED_Set_Pos(0,0);
//OLED_Fill(0x00);//黑屏
//OLED_DLY_ms(100);
}
