static int __INIT__ smsc91x_device_init(struct platform_device *pdev) { __u32 val; val = readl(VA(GPMC_CONFIG1(1))); val &= ~(0x3 << 10); val &= ~(0x1 << 9); val |= 0x1; writel(VA(GPMC_CONFIG1(1)), val); val = 0x8 << 8 | 0x1 << 6 | 0x8; writel(VA(GPMC_CONFIG7(1)), val); return 0; }
static int __init smsc91x_device_init(struct platform_device *pdev) { __u32 val; val = readl(VA(GPMC_CONFIG1(1))); val &= ~(0x3 << 10); val &= ~(0x1 << 9); val |= 0x1; writel(VA(GPMC_CONFIG1(1)), val); #if 0 val = 0xF << 8 | 0x1 << 6; // | 0x8; writel(VA(GPMC_CONFIG7(1)), val); #endif return 0; }
int setupGPMCNonMuxed(void){ unsigned int temp = 0; unsigned short int csNum = 1 ; volatile unsigned int * gpmc_reg_pointer ; printk("Configuring GPMC for non muxed access \n"); if (check_mem_region(SOC_GPMC_0_REGS, 720)) { printk("%s: memory already in use\n", gDrvrName); return -EBUSY; } request_mem_region(SOC_GPMC_0_REGS, 720, gDrvrName); gpmc_reg_pointer = ioremap_nocache(SOC_GPMC_0_REGS, 720); printk("GPMC_REVISION value :%x \n", ioread32(gpmc_reg_pointer + GPMC_REVISION/4)); orShortRegister(GPMC_SYSCONFIG_SOFTRESET, gpmc_reg_pointer + GPMC_SYSCONFIG/4 ) ; printk("Trying to reset GPMC \n"); printk("GPMC_SYSSTATUS value :%x \n", ioread32(gpmc_reg_pointer + GPMC_SYSSTATUS/4)); while((ioread32(gpmc_reg_pointer + GPMC_SYSSTATUS/4) & GPMC_SYSSTATUS_RESETDONE) == GPMC_SYSSTATUS_RESETDONE_RSTONGOING){ printk("GPMC_SYSSTATUS value :%x \n", ioread32(gpmc_reg_pointer + GPMC_SYSSTATUS/4)); } printk("GPMC reset \n"); temp = ioread32(gpmc_reg_pointer + GPMC_SYSCONFIG/4); temp &= ~GPMC_SYSCONFIG_IDLEMODE; temp |= GPMC_SYSCONFIG_IDLEMODE_NOIDLE << GPMC_SYSCONFIG_IDLEMODE_SHIFT; iowrite32(temp, gpmc_reg_pointer + GPMC_SYSCONFIG/4); iowrite32(0x00, gpmc_reg_pointer + GPMC_IRQENABLE/4) ; iowrite32(0x00, gpmc_reg_pointer + GPMC_TIMEOUT_CONTROL/4); iowrite32((0x0 | (GPMC_CONFIG1_0_DEVICESIZE_SIXTEENBITS << GPMC_CONFIG1_0_DEVICESIZE_SHIFT ) | (GPMC_CONFIG1_0_ATTACHEDDEVICEPAGELENGTH_FOUR << GPMC_CONFIG1_0_ATTACHEDDEVICEPAGELENGTH_SHIFT ) | (GPMC_CONFIG1_0_MUXADDDATA_NONMUX << GPMC_CONFIG1_0_MUXADDDATA_SHIFT )), gpmc_reg_pointer + GPMC_CONFIG1(csNum)/4) ; //Address/Data not multiplexed iowrite32( (0x0 | (0) | // CS_ON_TIME (6 << GPMC_CONFIG2_0_CSRDOFFTIME_SHIFT) | // CS_DEASSERT_RD (6 << GPMC_CONFIG2_0_CSWROFFTIME_SHIFT)), //CS_DEASSERT_WR gpmc_reg_pointer + GPMC_CONFIG2(csNum)/4) ; iowrite32((0x0 | (0 << GPMC_CONFIG3_0_ADVONTIME_SHIFT) | //ADV_ASSERT (0 << GPMC_CONFIG3_0_ADVRDOFFTIME_SHIFT) | //ADV_DEASSERT_RD (0 << GPMC_CONFIG3_0_ADVWROFFTIME_SHIFT)), //ADV_DEASSERT_WR gpmc_reg_pointer + GPMC_CONFIG3(csNum)/4) ; iowrite32((0x0 | (1 << GPMC_CONFIG4_0_OEONTIME_SHIFT) | //OE_ASSERT (6 << GPMC_CONFIG4_0_OEOFFTIME_SHIFT) | //OE_DEASSERT (1 << GPMC_CONFIG4_0_WEONTIME_SHIFT)| //WE_ASSERT (6 << GPMC_CONFIG4_0_WEOFFTIME_SHIFT)), //WE_DEASSERT gpmc_reg_pointer + GPMC_CONFIG4(csNum)/4) ; iowrite32((0x0 | (7 << GPMC_CONFIG5_0_RDCYCLETIME_SHIFT)| //CFG_5_RD_CYCLE_TIM (7 << GPMC_CONFIG5_0_WRCYCLETIME_SHIFT)| //CFG_5_WR_CYCLE_TIM (6 << GPMC_CONFIG5_0_RDACCESSTIME_SHIFT)), // CFG_5_RD_ACCESS_TIM gpmc_reg_pointer + GPMC_CONFIG5(csNum)/4) ; iowrite32( (0x0 | (0 << //GPMC_CONFIG6_0_CYCLE2CYCLESAMECSEN_C2CDELAY GPMC_CONFIG6_0_CYCLE2CYCLESAMECSEN_SHIFT) | (0 << GPMC_CONFIG6_0_CYCLE2CYCLEDELAY_SHIFT) | //CYC2CYC_DELAY (0 << GPMC_CONFIG6_0_WRDATAONADMUXBUS_SHIFT)| //WR_DATA_ON_ADMUX (0 << GPMC_CONFIG6_0_WRACCESSTIME_SHIFT)), //CFG_6_WR_ACCESS_TIM gpmc_reg_pointer + GPMC_CONFIG6(csNum)/4) ; iowrite32((0x09 << GPMC_CONFIG7_0_BASEADDRESS_SHIFT) | //CFG_7_BASE_ADDR (0x1 << GPMC_CONFIG7_0_CSVALID_SHIFT) | (0x0f << GPMC_CONFIG7_0_MASKADDRESS_SHIFT), //CFG_7_MASK gpmc_reg_pointer + GPMC_CONFIG7(csNum)/4); iounmap(gpmc_reg_pointer); release_mem_region(SOC_GPMC_0_REGS, 720); return 1; }
void setupGPMCMuxed(void){ unsigned int i ; unsigned int temp = 0; unsigned short int csNum = 1 ; printf("Configuring GPMC for mux access \n"); int fd = open("/dev/mem", O_RDWR | O_SYNC); printf("fd is%d \n", fd); //sleep(1); volatile unsigned int * gpmc_reg_pointer = (volatile unsigned int *) mmap(0, getpagesize(), PROT_READ | PROT_WRITE, MAP_SHARED ,fd, SOC_GPMC_0_REGS); //sleep(1); printf("mmap passed %x \n",gpmc_reg_pointer); if(gpmc_reg_pointer == -1){ printf( "%s\n", strerror( errno ) ); printf("cannot allocate pointer gpmc_reg_pointer at %x \n", SOC_GPMC_0_REGS); exit(EXIT_FAILURE); } printf("gpmc regs pointer allocated with address %x \n", gpmc_reg_pointer); //sleep(1); //reset the GPMC module printf("GPMC_REVISION value :%x \n", HWREG(gpmc_reg_pointer + GPMC_REVISION/4)); //sleep(1); HWREG(gpmc_reg_pointer + GPMC_SYSCONFIG/4 ) |= GPMC_SYSCONFIG_SOFTRESET; printf("Trying to reset GPMC \n"); printf("GPMC_SYSSTATUS value :%x \n", HWREG(gpmc_reg_pointer + GPMC_SYSSTATUS/4)); //sleep(1); while((HWREG(gpmc_reg_pointer + GPMC_SYSSTATUS/4) & GPMC_SYSSTATUS_RESETDONE) == GPMC_SYSSTATUS_RESETDONE_RSTONGOING){ //sleep(1); printf("GPMC_SYSSTATUS value :%x \n", HWREG(gpmc_reg_pointer + GPMC_SYSSTATUS/4)); } printf("GPMC reset \n"); //sleep(1); //Configure to no idle temp = HWREG(gpmc_reg_pointer + GPMC_SYSCONFIG/4); temp &= ~GPMC_SYSCONFIG_IDLEMODE; temp |= GPMC_SYSCONFIG_IDLEMODE_NOIDLE << GPMC_SYSCONFIG_IDLEMODE_SHIFT; printf("GPCM_SYSCONFIG value : %x \n", HWREG(gpmc_reg_pointer + GPMC_SYSCONFIG/4)); HWREG(gpmc_reg_pointer + GPMC_SYSCONFIG/4) = temp; printf("sysconfig configured with value %x \n", temp); //sleep(1); HWREG(gpmc_reg_pointer + GPMC_IRQENABLE/4) = 0x0; HWREG(gpmc_reg_pointer + GPMC_TIMEOUT_CONTROL/4) = 0x0; printf("IRQ and TIMEOUT configured \n"); //sleep(1); //configure for NOR and granularity x2 HWREG(gpmc_reg_pointer + GPMC_CONFIG1(csNum)/4) = (0x0 | (GPMC_CONFIG1_0_DEVICESIZE_SIXTEENBITS << GPMC_CONFIG1_0_DEVICESIZE_SHIFT ) | (GPMC_CONFIG1_0_ATTACHEDDEVICEPAGELENGTH_FOUR << GPMC_CONFIG1_0_ATTACHEDDEVICEPAGELENGTH_SHIFT ) | (0x2 << 8 )); //Address/Data Multiplex enable HWREG(gpmc_reg_pointer + GPMC_CONFIG2(csNum)/4) = (0x0 | (CS_ON) | // CS_ON_TIME (CS_OFF << GPMC_CONFIG2_0_CSRDOFFTIME_SHIFT) | // CS_DEASSERT_RD (CS_OFF << GPMC_CONFIG2_0_CSWROFFTIME_SHIFT)); //CS_DEASSERT_WR HWREG(gpmc_reg_pointer + GPMC_CONFIG3(csNum)/4) = (0x0 | (ADV_ON << GPMC_CONFIG3_0_ADVONTIME_SHIFT) | //ADV_ASSERT (ADV_OFF << GPMC_CONFIG3_0_ADVRDOFFTIME_SHIFT) | //ADV_DEASSERT_RD (ADV_OFF << GPMC_CONFIG3_0_ADVWROFFTIME_SHIFT)); //ADV_DEASSERT_WR HWREG(gpmc_reg_pointer + GPMC_CONFIG4(csNum)/4) = (0x0 | (OE_ON << GPMC_CONFIG4_0_OEONTIME_SHIFT) | //OE_ASSERT (OE_OFF << GPMC_CONFIG4_0_OEOFFTIME_SHIFT) | //OE_DEASSERT (WR_ON << GPMC_CONFIG4_0_WEONTIME_SHIFT)| //WE_ASSERT (WR_OFF << GPMC_CONFIG4_0_WEOFFTIME_SHIFT)); //WE_DEASSERT printf("config 1 to 4 configured \n"); //sleep(1); HWREG(gpmc_reg_pointer + GPMC_CONFIG5(csNum)/4) = (0x0 | (RD_CYC << GPMC_CONFIG5_0_RDCYCLETIME_SHIFT)| //CFG_5_RD_CYCLE_TIM (WR_CYC << GPMC_CONFIG5_0_WRCYCLETIME_SHIFT)| //CFG_5_WR_CYCLE_TIM (RD_ACC_TIME << GPMC_CONFIG5_0_RDACCESSTIME_SHIFT)); // CFG_5_RD_ACCESS_TIM HWREG(gpmc_reg_pointer + GPMC_CONFIG6(csNum)/4) = (0x0 | (0 << //GPMC_CONFIG6_0_CYCLE2CYCLESAMECSEN_C2CDELAY GPMC_CONFIG6_0_CYCLE2CYCLESAMECSEN_SHIFT) | (0 << GPMC_CONFIG6_0_CYCLE2CYCLEDELAY_SHIFT) | //CYC2CYC_DELAY (WRDATAONADMUX << GPMC_CONFIG6_0_WRDATAONADMUXBUS_SHIFT)| //WR_DATA_ON_ADMUX (0 << GPMC_CONFIG6_0_WRACCESSTIME_SHIFT)); //CFG_6_WR_ACCESS_TIM printf("config 5 & 6 configured \n"); //sleep(1); HWREG(gpmc_reg_pointer + GPMC_CONFIG7(csNum)/4) = ( 0x09 << GPMC_CONFIG7_0_BASEADDRESS_SHIFT) | //CFG_7_BASE_ADDR (0x1 << GPMC_CONFIG7_0_CSVALID_SHIFT) | (0x0f << GPMC_CONFIG7_0_MASKADDRESS_SHIFT); //CFG_7_MASK munmap((void *) gpmc_reg_pointer, getpagesize()); close(fd); }