/**
* Execute/clean up reconfiguration
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyExecuteReconfigV4 (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062;
PCIe_SILICON_CONFIG *Silicon;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Enter\n");
PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie);
D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
Silicon = PcieConfigGetParentSilicon (Wrapper);
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0xB8_ADDRESS,
D0F0xBC_x1F630_ADDRESS,
AccessWidth32,
(UINT32) ~D0F0xBC_x1F630_RECONF_WRAPPER_MASK,
Wrapper->WrapId << D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET,
GnbLibGetHeader (Pcie)
);
GnbSmuServiceRequestV4 (
Silicon->Address,
SMC_MSG_RECONFIGURE,
0,
GnbLibGetHeader (Pcie)
);
D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Exit\n");
}
}
VOID
GnbSmuServiceRequestV4S3Script (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT16 ContextLength,
IN VOID *Context
)
{
SMU_MSG_CONTEXT *SmuMsgContext;
SmuMsgContext = (SMU_MSG_CONTEXT *) Context;
GnbSmuServiceRequestV4 (SmuMsgContext->GnbPciAddress, SmuMsgContext->RequestId, 0, StdHeader);
}
/**
* RX offset cancellation enablement
*
*
*
* @param[in] Wrapper Pointer to Wrapper configuration data area
* @param[in] Pcie Pointer to PCIe configuration data area
*/
VOID
PcieOffsetCancelCalibration (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 LaneBitmap;
D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C;
LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper);
if ((Wrapper->WrapId != GFX_WRAP_ID) && (Wrapper->WrapId != GPP_WRAP_ID)) {
return;
}
if (LaneBitmap != 0) {
D0F0xBC_x1F39C.Value = 0;
D0F0xBC_x1F39C.Field.Tx = 1;
D0F0xBC_x1F39C.Field.Rx = 1;
D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane;
D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane;
GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
GnbSmuServiceRequestV4 (
PcieConfigGetParentSilicon (Wrapper)->Address,
SMC_MSG_PHY_LN_OFF,
GNB_REG_ACC_FLAG_S3SAVE,
GnbLibGetHeader (Pcie)
);
GnbSmuServiceRequestV4 (
PcieConfigGetParentSilicon (Wrapper)->Address,
SMC_MSG_PHY_LN_ON,
GNB_REG_ACC_FLAG_S3SAVE,
GnbLibGetHeader (Pcie)
);
}
PcieTopologyLaneControl (
EnableLanes,
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, 0, Wrapper),
Wrapper,
Pcie
);
}
STATIC AGESA_STATUS
GnbLclkDpmInitTN (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
PP_FUSE_ARRAY *PpFuseArray;
PCI_ADDR GnbPciAddress;
UINT32 Index;
UINT8 LclkDpmMode;
D0F0xBC_x1F200_STRUCT D0F0xBC_x1F200[NUM_DPM_STATES];
D0F0xBC_x1F208_STRUCT D0F0xBC_x1F208[NUM_DPM_STATES];
D0F0xBC_x1F210_STRUCT D0F0xBC_x1F210[NUM_DPM_STATES];
D0F0xBC_x1F300_STRUCT D0F0xBC_x1F300;
ex1003_STRUCT ex1003 [NUM_DPM_STATES];
DOUBLE PcieCacLut;
ex1072_STRUCT ex1072 ;
D0F0xBC_x1FE00_STRUCT D0F0xBC_x1FE00;
D0F0xBC_x1F30C_STRUCT D0F0xBC_x1F30C;
D18F3x64_STRUCT D18F3x64;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Enter\n");
Status = AGESA_SUCCESS;
LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled;
IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader);
if (LclkDpmMode == LclkDpmRcActivity) {
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
if (PpFuseArray != NULL) {
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
if (Status == AGESA_SUCCESS) {
GnbPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
//Clear DPM_EN bit in LCLK_DPM_CNTL register
//Call BIOS service SMC_MSG_CONFIG_LCLK_DPM to disable LCLK DPM
GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader);
D0F0xBC_x1F300.Field.LclkDpmEn = 0x0;
GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
GnbSmuServiceRequestV4 (
GnbPciAddress,
SMC_MSG_CONFIG_LCLK_DPM,
GNB_REG_ACC_FLAG_S3SAVE,
StdHeader
);
//Initialize LCLK states
LibAmdMemFill (D0F0xBC_x1F200, 0x00, sizeof (D0F0xBC_x1F200), StdHeader);
LibAmdMemFill (D0F0xBC_x1F208, 0x00, sizeof (D0F0xBC_x1F208), StdHeader);
LibAmdMemFill (ex1003, 0x00, sizeof (D0F0xBC_x1F208), StdHeader);
D0F0xBC_x1F200[0].Field.LclkDivider = PpFuseArray->LclkDpmDid[0];
D0F0xBC_x1F200[0].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[0]];
D0F0xBC_x1F200[0].Field.LowVoltageReqThreshold = 0xa;
D0F0xBC_x1F210[0].Field.ActivityThreshold = 0xf;
D0F0xBC_x1F200[5].Field.LclkDivider = PpFuseArray->LclkDpmDid[1];
D0F0xBC_x1F200[5].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[1]];
D0F0xBC_x1F200[5].Field.LowVoltageReqThreshold = 0xa;
D0F0xBC_x1F210[5].Field.ActivityThreshold = 0x32;
D0F0xBC_x1F200[5].Field.StateValid = 0x1;
D0F0xBC_x1F200[6].Field.LclkDivider = PpFuseArray->LclkDpmDid[2];
D0F0xBC_x1F200[6].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[2]];
D0F0xBC_x1F200[6].Field.LowVoltageReqThreshold = 0xa;
D0F0xBC_x1F210[6].Field.ActivityThreshold = 0x32;
D0F0xBC_x1F200[6].Field.StateValid = 0x1;
GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072.Value, 0, StdHeader);
PcieCacLut = 0.0000057028 * (1 << ex1072.Field.ex1072_0 );
IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM1 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader));
D0F0xBC_x1FE00.Field.Data = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader));
GnbRegisterWriteTN (D0F0xBC_x1FE00_TYPE, D0F0xBC_x1FE00_ADDRESS, &D0F0xBC_x1FE00.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
PcieCacLut = 0.00000540239329 * (1 << ex1072.Field.ex1072_0 );
ex1003[6].Field.ex1003_0 = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader));
IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM2 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader));
for (Index = 0; Index < NUM_DPM_STATES; ++Index) {
GnbRegisterWriteTN (
D0F0xBC_x1F200_TYPE,
D0F0xBC_x1F200_ADDRESS + Index * 0x20,
&D0F0xBC_x1F200[Index].Value,
GNB_REG_ACC_FLAG_S3SAVE,
StdHeader
);
GnbRegisterWriteTN (
D0F0xBC_x1F208_TYPE,
D0F0xBC_x1F208_ADDRESS + Index * 0x20,
&D0F0xBC_x1F208[Index].Value,
GNB_REG_ACC_FLAG_S3SAVE,
StdHeader
);
GnbRegisterWriteTN (
D0F0xBC_x1F210_TYPE,
D0F0xBC_x1F210_ADDRESS + Index * 0x20,
&D0F0xBC_x1F210[Index].Value,
GNB_REG_ACC_FLAG_S3SAVE,
StdHeader
);
GnbRegisterWriteTN (
TYPE_D0F0xBC ,
0x1f940 + Index * 4,
&ex1003[Index].Value,
GNB_REG_ACC_FLAG_S3SAVE,
StdHeader
);
}
//Enable LCLK DPM Voltage Scaling
GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader);
D0F0xBC_x1F300.Field.VoltageChgEn = 0x1;
D0F0xBC_x1F300.Field.LclkDpmEn = 0x1;
D0F0xBC_x1F300.Field.LclkDpmBootState = 0x5;
GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
//Programming Lclk Thermal Throttling Threshold
GnbRegisterReadTN (D18F3x64_TYPE, D18F3x64_ADDRESS, &D18F3x64.Value, 0, StdHeader);
GnbRegisterReadTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, 0, StdHeader);
D0F0xBC_x1F30C.Field.LowThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) - 1 + 49) * 8);
D0F0xBC_x1F30C.Field.HighThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) + 49) * 8);
GnbRegisterWriteTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
GnbSmuServiceRequestV4 (
GnbPciAddress,
SMC_MSG_CONFIG_LCLK_DPM,
GNB_REG_ACC_FLAG_S3SAVE,
StdHeader
);
}
} else {
Status = AGESA_ERROR;
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Exit [0x%x]\n", Status);
return Status;
}
