/*
* Control Adaptive Noise Immunity Parameters
*/
HAL_BOOL
ar9300_ani_control(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state = ahp->ah_curani;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
int32_t value, value2;
u_int level = param;
u_int is_on;
if (chan == NULL && cmd != HAL_ANI_MODE) {
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
"%s: ignoring cmd 0x%02x - no channel\n", __func__, cmd);
return AH_FALSE;
}
switch (cmd & ahp->ah_ani_function) {
case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION:
{
int m1_thresh_low, m2_thresh_low;
int m1_thresh, m2_thresh;
int m2_count_thr, m2_count_thr_low;
int m1_thresh_low_ext, m2_thresh_low_ext;
int m1_thresh_ext, m2_thresh_ext;
/*
* is_on == 1 means ofdm weak signal detection is ON
* (default, less noise imm)
* is_on == 0 means ofdm weak signal detection is OFF
* (more noise imm)
*/
is_on = param ? 1 : 0;
if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah))
goto skip_ws_det;
/*
* make register setting for default (weak sig detect ON)
* come from INI file
*/
m1_thresh_low = is_on ?
ani_state->ini_def.m1_thresh_low : m1_thresh_low_off;
m2_thresh_low = is_on ?
ani_state->ini_def.m2_thresh_low : m2_thresh_low_off;
m1_thresh = is_on ?
ani_state->ini_def.m1_thresh : m1_thresh_off;
m2_thresh = is_on ?
ani_state->ini_def.m2_thresh : m2_thresh_off;
m2_count_thr = is_on ?
ani_state->ini_def.m2_count_thr : m2_count_thr_off;
m2_count_thr_low = is_on ?
ani_state->ini_def.m2_count_thr_low : m2_count_thr_low_off;
m1_thresh_low_ext = is_on ?
ani_state->ini_def.m1_thresh_low_ext : m1_thresh_low_ext_off;
m2_thresh_low_ext = is_on ?
ani_state->ini_def.m2_thresh_low_ext : m2_thresh_low_ext_off;
m1_thresh_ext = is_on ?
ani_state->ini_def.m1_thresh_ext : m1_thresh_ext_off;
m2_thresh_ext = is_on ?
ani_state->ini_def.m2_thresh_ext : m2_thresh_ext_off;
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M1_THRESH,
m1_thresh);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2_THRESH,
m2_thresh);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2COUNT_THR,
m2_count_thr);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low_ext);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low_ext);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH,
m1_thresh_ext);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M2_THRESH,
m2_thresh_ext);
skip_ws_det:
if (is_on) {
OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
} else {
OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
}
if (!(is_on != ani_state->ofdm_weak_sig_detect_off)) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: ofdm weak signal: %s=>%s\n",
__func__, chan->ic_freq,
!ani_state->ofdm_weak_sig_detect_off ? "on" : "off",
is_on ? "on" : "off");
if (is_on) {
ahp->ah_stats.ast_ani_ofdmon++;
} else {
ahp->ah_stats.ast_ani_ofdmoff++;
}
ani_state->ofdm_weak_sig_detect_off = !is_on;
}
break;
}
case HAL_ANI_FIRSTEP_LEVEL:
if (level >= ARRAY_LENGTH(firstep_table)) {
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
"%s: HAL_ANI_FIRSTEP_LEVEL level out of range (%u > %u)\n",
__func__, level, (unsigned) ARRAY_LENGTH(firstep_table));
return AH_FALSE;
}
/*
* make register setting relative to default
* from INI file & cap value
*/
value =
firstep_table[level] -
firstep_table[HAL_ANI_DEF_FIRSTEP_LVL] +
ani_state->ini_def.firstep;
if (value < HAL_SIG_FIRSTEP_SETTING_MIN) {
value = HAL_SIG_FIRSTEP_SETTING_MIN;
}
if (value > HAL_SIG_FIRSTEP_SETTING_MAX) {
value = HAL_SIG_FIRSTEP_SETTING_MAX;
}
OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, value);
/*
* we need to set first step low register too
* make register setting relative to default from INI file & cap value
*/
value2 =
firstep_table[level] -
firstep_table[HAL_ANI_DEF_FIRSTEP_LVL] +
ani_state->ini_def.firstep_low;
if (value2 < HAL_SIG_FIRSTEP_SETTING_MIN) {
value2 = HAL_SIG_FIRSTEP_SETTING_MIN;
}
if (value2 > HAL_SIG_FIRSTEP_SETTING_MAX) {
value2 = HAL_SIG_FIRSTEP_SETTING_MAX;
}
OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
if (level != ani_state->firstep_level) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
__func__, chan->ic_freq, ani_state->firstep_level, level,
HAL_ANI_DEF_FIRSTEP_LVL, value, ani_state->ini_def.firstep);
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: level %d=>%d[def:%d] "
"firstep_low[level]=%d ini=%d\n",
__func__, chan->ic_freq, ani_state->firstep_level, level,
HAL_ANI_DEF_FIRSTEP_LVL, value2,
ani_state->ini_def.firstep_low);
if (level > ani_state->firstep_level) {
ahp->ah_stats.ast_ani_stepup++;
} else if (level < ani_state->firstep_level) {
ahp->ah_stats.ast_ani_stepdown++;
}
ani_state->firstep_level = level;
}
break;
case HAL_ANI_SPUR_IMMUNITY_LEVEL:
if (level >= ARRAY_LENGTH(cycpwr_thr1_table)) {
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
"%s: HAL_ANI_SPUR_IMMUNITY_LEVEL level "
"out of range (%u > %u)\n",
__func__, level, (unsigned) ARRAY_LENGTH(cycpwr_thr1_table));
return AH_FALSE;
}
/*
* make register setting relative to default from INI file & cap value
*/
value =
cycpwr_thr1_table[level] -
cycpwr_thr1_table[HAL_ANI_DEF_SPUR_IMMUNE_LVL] +
ani_state->ini_def.cycpwr_thr1;
if (value < HAL_SIG_SPUR_IMM_SETTING_MIN) {
value = HAL_SIG_SPUR_IMM_SETTING_MIN;
}
if (value > HAL_SIG_SPUR_IMM_SETTING_MAX) {
value = HAL_SIG_SPUR_IMM_SETTING_MAX;
}
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, value);
/*
* set AR_PHY_EXT_CCA for extension channel
* make register setting relative to default from INI file & cap value
*/
value2 =
cycpwr_thr1_table[level] -
cycpwr_thr1_table[HAL_ANI_DEF_SPUR_IMMUNE_LVL] +
ani_state->ini_def.cycpwr_thr1_ext;
if (value2 < HAL_SIG_SPUR_IMM_SETTING_MIN) {
value2 = HAL_SIG_SPUR_IMM_SETTING_MIN;
}
if (value2 > HAL_SIG_SPUR_IMM_SETTING_MAX) {
value2 = HAL_SIG_SPUR_IMM_SETTING_MAX;
}
OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CYCPWR_THR1, value2);
if (level != ani_state->spur_immunity_level) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: level %d=>%d[def:%d] "
"cycpwr_thr1[level]=%d ini=%d\n",
__func__, chan->ic_freq, ani_state->spur_immunity_level, level,
HAL_ANI_DEF_SPUR_IMMUNE_LVL, value,
ani_state->ini_def.cycpwr_thr1);
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: level %d=>%d[def:%d] "
"cycpwr_thr1_ext[level]=%d ini=%d\n",
__func__, chan->ic_freq, ani_state->spur_immunity_level, level,
HAL_ANI_DEF_SPUR_IMMUNE_LVL, value2,
ani_state->ini_def.cycpwr_thr1_ext);
if (level > ani_state->spur_immunity_level) {
ahp->ah_stats.ast_ani_spurup++;
} else if (level < ani_state->spur_immunity_level) {
ahp->ah_stats.ast_ani_spurdown++;
}
ani_state->spur_immunity_level = level;
}
break;
case HAL_ANI_MRC_CCK:
/*
* is_on == 1 means MRC CCK ON (default, less noise imm)
* is_on == 0 means MRC CCK is OFF (more noise imm)
*/
is_on = param ? 1 : 0;
if (!AR_SREV_POSEIDON(ah)) {
OS_REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
AR_PHY_MRC_CCK_ENABLE, is_on);
OS_REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
AR_PHY_MRC_CCK_MUX_REG, is_on);
}
if (!(is_on != ani_state->mrc_cck_off)) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: MRC CCK: %s=>%s\n", __func__, chan->ic_freq,
!ani_state->mrc_cck_off ? "on" : "off", is_on ? "on" : "off");
if (is_on) {
ahp->ah_stats.ast_ani_ccklow++;
} else {
ahp->ah_stats.ast_ani_cckhigh++;
}
ani_state->mrc_cck_off = !is_on;
}
break;
case HAL_ANI_PRESENT:
break;
#ifdef AH_PRIVATE_DIAG
case HAL_ANI_MODE:
if (param == 0) {
ahp->ah_proc_phy_err &= ~HAL_PROCESS_ANI;
/* Turn off HW counters if we have them */
ar9300_ani_detach(ah);
if (AH_PRIVATE(ah)->ah_curchan == NULL) {
return AH_TRUE;
}
/* if we're turning off ANI, reset regs back to INI settings */
if (ah->ah_config.ath_hal_enable_ani) {
HAL_ANI_CMD savefunc = ahp->ah_ani_function;
/* temporarly allow all functions so we can reset */
ahp->ah_ani_function = HAL_ANI_ALL;
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: disable all ANI functions\n", __func__);
ar9300_ani_set_odfm_noise_immunity_level(
ah, HAL_ANI_OFDM_DEF_LEVEL);
ar9300_ani_set_cck_noise_immunity_level(
ah, HAL_ANI_CCK_DEF_LEVEL);
ahp->ah_ani_function = savefunc;
}
} else { /* normal/auto mode */
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: enabled\n", __func__);
ahp->ah_proc_phy_err |= HAL_PROCESS_ANI;
if (AH_PRIVATE(ah)->ah_curchan == NULL) {
return AH_TRUE;
}
ar9300_enable_mib_counters(ah);
ar9300_ani_reset(ah, AH_FALSE);
ani_state = ahp->ah_curani;
}
HALDEBUG(ah, HAL_DEBUG_ANI, "5 ANC: ahp->ah_proc_phy_err %x \n",
ahp->ah_proc_phy_err);
break;
case HAL_ANI_PHYERR_RESET:
ahp->ah_stats.ast_ani_ofdmerrs = 0;
ahp->ah_stats.ast_ani_cckerrs = 0;
break;
#endif /* AH_PRIVATE_DIAG */
default:
#if HAL_ANI_DEBUG
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: invalid cmd 0x%02x (allowed=0x%02x)\n",
__func__, cmd, ahp->ah_ani_function);
#endif
return AH_FALSE;
}
#if HAL_ANI_DEBUG
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ANI parameters: SI=%d, ofdm_ws=%s FS=%d MRCcck=%s listen_time=%d "
"CC=%d listen=%d ofdm_errs=%d cck_errs=%d\n",
__func__, ani_state->spur_immunity_level,
!ani_state->ofdm_weak_sig_detect_off ? "on" : "off",
ani_state->firstep_level, !ani_state->mrc_cck_off ? "on" : "off",
ani_state->listen_time, ani_state->cycle_count,
ani_state->listen_time, ani_state->ofdm_phy_err_count,
ani_state->cck_phy_err_count);
#endif
#ifndef REMOVE_PKT_LOG
/* do pktlog */
{
struct log_ani log_data;
/* Populate the ani log record */
log_data.phy_stats_disable = DO_ANI(ah);
log_data.noise_immun_lvl = ani_state->ofdm_noise_immunity_level;
log_data.spur_immun_lvl = ani_state->spur_immunity_level;
log_data.ofdm_weak_det = ani_state->ofdm_weak_sig_detect_off;
log_data.cck_weak_thr = ani_state->cck_noise_immunity_level;
log_data.fir_lvl = ani_state->firstep_level;
log_data.listen_time = ani_state->listen_time;
log_data.cycle_count = ani_state->cycle_count;
/* express ofdm_phy_err_count as errors/second */
log_data.ofdm_phy_err_count = ani_state->listen_time ?
ani_state->ofdm_phy_err_count * 1000 / ani_state->listen_time : 0;
/* express cck_phy_err_count as errors/second */
log_data.cck_phy_err_count = ani_state->listen_time ?
ani_state->cck_phy_err_count * 1000 / ani_state->listen_time : 0;
log_data.rssi = ani_state->rssi;
/* clear interrupt context flag */
ath_hal_log_ani(AH_PRIVATE(ah)->ah_sc, &log_data, 0);
}
#endif
return AH_TRUE;
}
/*
* Reads EEPROM header info from device structure and programs
* all rf registers
*
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
ar2316SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
{
#define RF_BANK_SETUP(_priv, _ix, _col) do { \
int i; \
for (i = 0; i < N(ar5212Bank##_ix##_2316); i++) \
(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2316[i][_col];\
} while (0)
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
uint16_t ob2GHz = 0, db2GHz = 0;
struct ar2316State *priv = AR2316(ah);
int regWrites = 0;
HALDEBUG(ah, HAL_DEBUG_RFPARAM,
"%s: chan 0x%x flag 0x%x modesIndex 0x%x\n",
__func__, chan->channel, chan->channelFlags, modesIndex);
HALASSERT(priv != AH_NULL);
/* Setup rf parameters */
switch (chan->channelFlags & CHANNEL_ALL) {
case CHANNEL_B:
ob2GHz = ee->ee_obFor24;
db2GHz = ee->ee_dbFor24;
break;
case CHANNEL_G:
case CHANNEL_108G:
ob2GHz = ee->ee_obFor24g;
db2GHz = ee->ee_dbFor24g;
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
__func__, chan->channelFlags);
return AH_FALSE;
}
/* Bank 1 Write */
RF_BANK_SETUP(priv, 1, 1);
/* Bank 2 Write */
RF_BANK_SETUP(priv, 2, modesIndex);
/* Bank 3 Write */
RF_BANK_SETUP(priv, 3, modesIndex);
/* Bank 6 Write */
RF_BANK_SETUP(priv, 6, modesIndex);
ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 178, 0);
ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 175, 0);
/* Bank 7 Setup */
RF_BANK_SETUP(priv, 7, modesIndex);
/* Write Analog registers */
HAL_INI_WRITE_BANK(ah, ar5212Bank1_2316, priv->Bank1Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank2_2316, priv->Bank2Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank3_2316, priv->Bank3Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank6_2316, priv->Bank6Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank7_2316, priv->Bank7Data, regWrites);
/* Now that we have reprogrammed rfgain value, clear the flag. */
ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
return AH_TRUE;
#undef RF_BANK_SETUP
}
static HAL_BOOL
ar2316SetPowerTable(struct ath_hal *ah,
int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan,
uint16_t *rfXpdGain)
{
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
const RAW_DATA_STRUCT_2316 *pRawDataset = AH_NULL;
uint16_t pdGainOverlap_t2;
int16_t minCalPower2316_t2;
uint16_t *pdadcValues = ahp->ah_pcdacTable;
uint16_t gainBoundaries[4];
uint32_t reg32, regoffset;
int i, numPdGainsUsed;
#ifndef AH_USE_INIPDGAIN
uint32_t tpcrg1;
#endif
HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
__func__, chan->channel,chan->channelFlags);
if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
else if (IS_CHAN_B(chan))
pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__);
return AH_FALSE;
}
pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
numPdGainsUsed = ar2316getGainBoundariesAndPdadcsForPowers(ah,
chan->channel, pRawDataset, pdGainOverlap_t2,
&minCalPower2316_t2,gainBoundaries, rfXpdGain, pdadcValues);
HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);
#ifdef AH_USE_INIPDGAIN
/*
* Use pd_gains curve from eeprom; Atheros always uses
* the default curve from the ini file but some vendors
* (e.g. Zcomax) want to override this curve and not
* honoring their settings results in tx power 5dBm low.
*/
OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
(pRawDataset->pDataPerChannel[0].numPdGains - 1));
#else
tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);
tpcrg1 = (tpcrg1 &~ AR_PHY_TPCRG1_NUM_PD_GAIN)
| SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);
switch (numPdGainsUsed) {
case 3:
tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING3;
tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);
/* fall thru... */
case 2:
tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING2;
tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);
/* fall thru... */
case 1:
tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING1;
tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);
break;
}
#ifdef AH_DEBUG
if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))
HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "
"pd_gains (default 0x%x, calculated 0x%x)\n",
__func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);
#endif
OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);
#endif
/*
* Note the pdadc table may not start at 0 dBm power, could be
* negative or greater than 0. Need to offset the power
* values by the amount of minPower for griffin
*/
if (minCalPower2316_t2 != 0)
ahp->ah_txPowerIndexOffset = (int16_t)(0 - minCalPower2316_t2);
else
ahp->ah_txPowerIndexOffset = 0;
/* Finally, write the power values into the baseband power table */
regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
for (i = 0; i < 32; i++) {
reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0) |
((pdadcValues[4*i + 1] & 0xFF) << 8) |
((pdadcValues[4*i + 2] & 0xFF) << 16) |
((pdadcValues[4*i + 3] & 0xFF) << 24) ;
OS_REG_WRITE(ah, regoffset, reg32);
regoffset += 4;
}
OS_REG_WRITE(ah, AR_PHY_TPCRG5,
SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
return AH_TRUE;
}
/*
* Cleanup any ANI state setup.
*/
void
ar5416AniDetach(struct ath_hal *ah)
{
HALDEBUG(ah, HAL_DEBUG_ANI, "Detaching Ani\n");
disableAniMIBCounters(ah);
}
/*
* Restore/reset the ANI parameters and reset the statistics.
* This routine must be called for every channel change.
*
* NOTE: This is where ah_curani is set; other ani code assumes
* it is setup to reflect the current channel.
*/
void
ar5416AniReset(struct ath_hal *ah, const struct ieee80211_channel *chan,
HAL_OPMODE opmode, int restore)
{
struct ath_hal_5212 *ahp = AH5212(ah);
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
/* XXX bounds check ic_devdata */
struct ar5212AniState *aniState = &ahp->ah_ani[chan->ic_devdata];
uint32_t rxfilter;
if ((ichan->privFlags & CHANNEL_ANI_INIT) == 0) {
OS_MEMZERO(aniState, sizeof(*aniState));
if (IEEE80211_IS_CHAN_2GHZ(chan))
aniState->params = &ahp->ah_aniParams24;
else
aniState->params = &ahp->ah_aniParams5;
ichan->privFlags |= CHANNEL_ANI_INIT;
HALASSERT((ichan->privFlags & CHANNEL_ANI_SETUP) == 0);
}
ahp->ah_curani = aniState;
#if 0
ath_hal_printf(ah,"%s: chan %u/0x%x restore %d opmode %u%s\n",
__func__, chan->ic_freq, chan->ic_flags, restore, opmode,
ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");
#else
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: chan %u/0x%x restore %d opmode %u%s\n",
__func__, chan->ic_freq, chan->ic_flags, restore, opmode,
ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");
#endif
OS_MARK(ah, AH_MARK_ANI_RESET, opmode);
/*
* Turn off PHY error frame delivery while we futz with settings.
*/
rxfilter = ar5212GetRxFilter(ah);
ar5212SetRxFilter(ah, rxfilter &~ HAL_RX_FILTER_PHYERR);
/*
* Automatic processing is done only in station mode right now.
*/
if (opmode == HAL_M_STA)
ahp->ah_procPhyErr |= HAL_RSSI_ANI_ENA;
else
ahp->ah_procPhyErr &= ~HAL_RSSI_ANI_ENA;
/*
* Set all ani parameters. We either set them to initial
* values or restore the previous ones for the channel.
* XXX if ANI follows hardware, we don't care what mode we're
* XXX in, we should keep the ani parameters
*/
if (restore && (ichan->privFlags & CHANNEL_ANI_SETUP)) {
ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
aniState->noiseImmunityLevel);
ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
aniState->spurImmunityLevel);
ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
!aniState->ofdmWeakSigDetectOff);
ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
aniState->cckWeakSigThreshold);
ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel);
} else {
ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
AH_TRUE);
ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);
ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
ichan->privFlags |= CHANNEL_ANI_SETUP;
}
ar5416AniRestart(ah, aniState);
/* restore RX filter mask */
ar5212SetRxFilter(ah, rxfilter);
}
static void
ar5212AniOfdmErrTrigger(struct ath_hal *ah)
{
struct ath_hal_5212 *ahp = AH5212(ah);
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
struct ar5212AniState *aniState;
const struct ar5212AniParams *params;
HALASSERT(chan != AH_NULL);
if (!ANI_ENA(ah))
return;
aniState = ahp->ah_curani;
params = aniState->params;
/* First, raise noise immunity level, up to max */
if (aniState->noiseImmunityLevel+1 <= params->maxNoiseImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise NI to %u\n", __func__,
aniState->noiseImmunityLevel + 1);
ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
aniState->noiseImmunityLevel + 1);
return;
}
/* then, raise spur immunity level, up to max */
if (aniState->spurImmunityLevel+1 <= params->maxSpurImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise SI to %u\n", __func__,
aniState->spurImmunityLevel + 1);
ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
aniState->spurImmunityLevel + 1);
return;
}
if (ANI_ENA_RSSI(ah)) {
int32_t rssi = BEACON_RSSI(ahp);
if (rssi > params->rssiThrHigh) {
/*
* Beacon rssi is high, can turn off ofdm
* weak sig detect.
*/
if (!aniState->ofdmWeakSigDetectOff) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d OWSD off\n", __func__, rssi);
ar5212AniControl(ah,
HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
AH_FALSE);
ar5212AniControl(ah,
HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
return;
}
/*
* If weak sig detect is already off, as last resort,
* raise firstep level
*/
if (aniState->firstepLevel+1 <= params->maxFirstepLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d raise ST %u\n", __func__, rssi,
aniState->firstepLevel+1);
ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel + 1);
return;
}
} else if (rssi > params->rssiThrLow) {
/*
* Beacon rssi in mid range, need ofdm weak signal
* detect, but we can raise firststepLevel.
*/
if (aniState->ofdmWeakSigDetectOff) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d OWSD on\n", __func__, rssi);
ar5212AniControl(ah,
HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
AH_TRUE);
}
if (aniState->firstepLevel+1 <= params->maxFirstepLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d raise ST %u\n", __func__, rssi,
aniState->firstepLevel+1);
ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel + 1);
}
return;
} else {
/*
* Beacon rssi is low, if in 11b/g mode, turn off ofdm
* weak signal detection and zero firstepLevel to
* maximize CCK sensitivity
*/
if (IEEE80211_IS_CHAN_CCK(chan)) {
if (!aniState->ofdmWeakSigDetectOff) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d OWSD off\n",
__func__, rssi);
ar5212AniControl(ah,
HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
AH_FALSE);
}
if (aniState->firstepLevel > 0) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d zero ST (was %u)\n",
__func__, rssi,
aniState->firstepLevel);
ar5212AniControl(ah,
HAL_ANI_FIRSTEP_LEVEL, 0);
}
return;
}
}
}
}
/*
* Attach for an AR9160 part.
*/
static struct ath_hal *
ar9160Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
HAL_STATUS *status)
{
struct ath_hal_5416 *ahp5416;
struct ath_hal_5212 *ahp;
struct ath_hal *ah;
uint32_t val;
HAL_STATUS ecode;
HAL_BOOL rfStatus;
HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
__func__, sc, (void*) st, (void*) sh);
/* NB: memory is returned zero'd */
ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416));
if (ahp5416 == AH_NULL) {
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
"%s: cannot allocate memory for state block\n", __func__);
*status = HAL_ENOMEM;
return AH_NULL;
}
ar5416InitState(ahp5416, devid, sc, st, sh, status);
ahp = &ahp5416->ah_5212;
ah = &ahp->ah_priv.h;
/* XXX override with 9160 specific state */
/* override 5416 methods for our needs */
AH5416(ah)->ah_initPLL = ar9160InitPLL;
AH5416(ah)->ah_cal.iqCalData.calData = &ar9160_iq_cal;
AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9160_adc_gain_cal;
AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9160_adc_dc_cal;
AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9160_adc_init_dc_cal;
AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
/* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
__func__);
ecode = HAL_EIO;
goto bad;
}
if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
__func__);
ecode = HAL_EIO;
goto bad;
}
/* Read Revisions from Chips before taking out of reset */
val = OS_REG_READ(ah, AR_SREV);
HALDEBUG(ah, HAL_DEBUG_ATTACH,
"%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
__func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
/* NB: include chip type to differentiate from pre-Sowl versions */
AH_PRIVATE(ah)->ah_macVersion =
(val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
/* setup common ini data; rf backends handle remainder */
HAL_INI_INIT(&ahp->ah_ini_modes, ar9160Modes, 6);
HAL_INI_INIT(&ahp->ah_ini_common, ar9160Common, 2);
HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar9160BB_RfGain, 3);
HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar9160Bank0, 2);
HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar9160Bank1, 2);
HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar9160Bank2, 2);
HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar9160Bank3, 3);
HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar9160Bank6TPC, 3);
HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar9160Bank7, 2);
if (AR_SREV_SOWL_11(ah))
HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar9160Addac_1_1, 2);
else
HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar9160Addac, 2);
ecode = ath_hal_v14EepromAttach(ah);
if (ecode != HAL_OK)
goto bad;
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar9160PciePhy, 2);
ar5416AttachPCIE(ah);
if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
ecode = HAL_EIO;
goto bad;
}
AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
if (!ar5212ChipTest(ah)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
__func__);
ecode = HAL_ESELFTEST;
goto bad;
}
/*
* Set correct Baseband to analog shift
* setting to access analog chips.
*/
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
/* Read Radio Chip Rev Extract */
AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
break;
default:
if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
AH_PRIVATE(ah)->ah_analog5GhzRev =
AR_RAD5133_SREV_MAJOR;
break;
}
#ifdef AH_DEBUG
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: 5G Radio Chip Rev 0x%02X is not supported by "
"this driver\n", __func__,
AH_PRIVATE(ah)->ah_analog5GhzRev);
ecode = HAL_ENOTSUPP;
goto bad;
#endif
}
rfStatus = ar2133RfAttach(ah, &ecode);
if (!rfStatus) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
__func__, ecode);
goto bad;
}
/*
* Got everything we need now to setup the capabilities.
*/
if (!ar9160FillCapabilityInfo(ah)) {
ecode = HAL_EEREAD;
goto bad;
}
ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
if (ecode != HAL_OK) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error getting mac address from EEPROM\n", __func__);
goto bad;
}
/* XXX How about the serial number ? */
/* Read Reg Domain */
AH_PRIVATE(ah)->ah_currentRD =
ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
AH_PRIVATE(ah)->ah_currentRDext =
ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL);
/*
* ah_miscMode is populated by ar5416FillCapabilityInfo()
* starting from griffin. Set here to make sure that
* AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
* placed into hardware.
*/
if (ahp->ah_miscMode != 0)
OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
ar9160AniSetup(ah); /* Anti Noise Immunity */
/* This just uses the AR5416 NF values */
AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
return ah;
bad:
if (ahp)
ar5416Detach((struct ath_hal *) ahp);
if (status)
*status = ecode;
return AH_NULL;
}
/*
* Attach for an AR9280 part.
*/
static struct ath_hal *
ar9280Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
{
struct ath_hal_9280 *ahp9280;
struct ath_hal_5212 *ahp;
struct ath_hal *ah;
uint32_t val;
HAL_STATUS ecode;
HAL_BOOL rfStatus;
HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
__func__, sc, (void*) st, (void*) sh);
/* NB: memory is returned zero'd */
ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280));
if (ahp9280 == AH_NULL) {
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
"%s: cannot allocate memory for state block\n", __func__);
*status = HAL_ENOMEM;
return AH_NULL;
}
ahp = AH5212(ahp9280);
ah = &ahp->ah_priv.h;
ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
/* XXX override with 9280 specific state */
/* override 5416 methods for our needs */
ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch;
ah->ah_configPCIE = ar9280ConfigPCIE;
AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
AH5416(ah)->ah_writeIni = ar9280WriteIni;
AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK;
AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK;
if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
/* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
__func__);
ecode = HAL_EIO;
goto bad;
}
if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
__func__);
ecode = HAL_EIO;
goto bad;
}
/* Read Revisions from Chips before taking out of reset */
val = OS_REG_READ(ah, AR_SREV);
HALDEBUG(ah, HAL_DEBUG_ATTACH,
"%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
__func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
/* NB: include chip type to differentiate from pre-Sowl versions */
AH_PRIVATE(ah)->ah_macVersion =
(val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
/* setup common ini data; rf backends handle remainder */
if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6);
HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2);
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
ar9280PciePhy_clkreq_always_on_L1_v2, 2);
HAL_INI_INIT(&ahp9280->ah_ini_xmodes,
ar9280Modes_fast_clock_v2, 3);
} else {
HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6);
HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2);
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
ar9280PciePhy_v1, 2);
}
ar5416AttachPCIE(ah);
ecode = ath_hal_v14EepromAttach(ah);
if (ecode != HAL_OK)
goto bad;
if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
ecode = HAL_EIO;
goto bad;
}
AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
if (!ar5212ChipTest(ah)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
__func__);
ecode = HAL_ESELFTEST;
goto bad;
}
/*
* Set correct Baseband to analog shift
* setting to access analog chips.
*/
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
/* Read Radio Chip Rev Extract */
AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
break;
default:
if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
AH_PRIVATE(ah)->ah_analog5GhzRev =
AR_RAD5133_SREV_MAJOR;
break;
}
#ifdef AH_DEBUG
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: 5G Radio Chip Rev 0x%02X is not supported by "
"this driver\n", __func__,
AH_PRIVATE(ah)->ah_analog5GhzRev);
ecode = HAL_ENOTSUPP;
goto bad;
#endif
}
rfStatus = ar9280RfAttach(ah, &ecode);
if (!rfStatus) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
__func__, ecode);
goto bad;
}
if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
/* setup rxgain table */
switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) {
case AR5416_EEP_RXGAIN_13dB_BACKOFF:
HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
ar9280Modes_backoff_13db_rxgain_v2, 6);
break;
case AR5416_EEP_RXGAIN_23dB_BACKOFF:
HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
ar9280Modes_backoff_23db_rxgain_v2, 6);
break;
case AR5416_EEP_RXGAIN_ORIG:
HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
ar9280Modes_original_rxgain_v2, 6);
break;
default:
HALASSERT(AH_FALSE);
goto bad; /* XXX ? try to continue */
}
}
if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
/* setp txgain table */
switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
case AR5416_EEP_TXGAIN_HIGH_POWER:
HAL_INI_INIT(&ahp9280->ah_ini_txgain,
ar9280Modes_high_power_tx_gain_v2, 6);
break;
case AR5416_EEP_TXGAIN_ORIG:
HAL_INI_INIT(&ahp9280->ah_ini_txgain,
ar9280Modes_original_tx_gain_v2, 6);
break;
default:
HALASSERT(AH_FALSE);
goto bad; /* XXX ? try to continue */
}
}
/*
* Got everything we need now to setup the capabilities.
*/
if (!ar9280FillCapabilityInfo(ah)) {
ecode = HAL_EEREAD;
goto bad;
}
ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
if (ecode != HAL_OK) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error getting mac address from EEPROM\n", __func__);
goto bad;
}
/* XXX How about the serial number ? */
/* Read Reg Domain */
AH_PRIVATE(ah)->ah_currentRD =
ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
/*
* ah_miscMode is populated by ar5416FillCapabilityInfo()
* starting from griffin. Set here to make sure that
* AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
* placed into hardware.
*/
if (ahp->ah_miscMode != 0)
OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
ar9280AniSetup(ah); /* Anti Noise Immunity */
ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
return ah;
bad:
if (ah != AH_NULL)
ah->ah_detach(ah);
if (status)
*status = ecode;
return AH_NULL;
}
static void
ar5312AniSetup(struct ath_hal *ah)
{
static const struct ar5212AniParams aniparams = {
.maxNoiseImmunityLevel = 4, /* levels 0..4 */
.totalSizeDesired = { -41, -41, -48, -48, -48 },
.coarseHigh = { -18, -18, -16, -14, -12 },
.coarseLow = { -56, -56, -60, -60, -60 },
.firpwr = { -72, -72, -75, -78, -80 },
.maxSpurImmunityLevel = 2,
.cycPwrThr1 = { 2, 4, 6 },
.maxFirstepLevel = 2, /* levels 0..2 */
.firstep = { 0, 4, 8 },
.ofdmTrigHigh = 500,
.ofdmTrigLow = 200,
.cckTrigHigh = 200,
.cckTrigLow = 100,
.rssiThrHigh = 40,
.rssiThrLow = 7,
.period = 100,
};
ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
}
/*
* Attach for an AR5312 part.
*/
static struct ath_hal *
ar5312Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
HAL_OPS_CONFIG *ah_config, HAL_STATUS *status)
{
struct ath_hal_5212 *ahp = AH_NULL;
struct ath_hal *ah;
struct ath_hal_rf *rf;
uint32_t val;
uint16_t eeval;
HAL_STATUS ecode;
HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
__func__, sc, st, (void*) sh);
/* NB: memory is returned zero'd */
ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));
if (ahp == AH_NULL) {
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
"%s: cannot allocate memory for state block\n", __func__);
*status = HAL_ENOMEM;
return AH_NULL;
}
ar5212InitState(ahp, devid, sc, st, sh, status);
ah = &ahp->ah_priv.h;
/* override 5212 methods for our needs */
ah->ah_reset = ar5312Reset;
ah->ah_phyDisable = ar5312PhyDisable;
ah->ah_setLedState = ar5312SetLedState;
ah->ah_detectCardPresent = ar5312DetectCardPresent;
ah->ah_setPowerMode = ar5312SetPowerMode;
ah->ah_getPowerMode = ar5312GetPowerMode;
ah->ah_isInterruptPending = ar5312IsInterruptPending;
ahp->ah_priv.ah_eepromRead = ar5312EepromRead;
#ifdef AH_SUPPORT_WRITE_EEPROM
ahp->ah_priv.ah_eepromWrite = ar5312EepromWrite;
#endif
#if ( AH_SUPPORT_2316 || AH_SUPPORT_2317)
if (IS_5315(ah)) {
ahp->ah_priv.ah_gpioCfgOutput = ar5315GpioCfgOutput;
ahp->ah_priv.ah_gpioCfgInput = ar5315GpioCfgInput;
ahp->ah_priv.ah_gpioGet = ar5315GpioGet;
ahp->ah_priv.ah_gpioSet = ar5315GpioSet;
ahp->ah_priv.ah_gpioSetIntr = ar5315GpioSetIntr;
} else
#endif
{
ahp->ah_priv.ah_gpioCfgOutput = ar5312GpioCfgOutput;
ahp->ah_priv.ah_gpioCfgInput = ar5312GpioCfgInput;
ahp->ah_priv.ah_gpioGet = ar5312GpioGet;
ahp->ah_priv.ah_gpioSet = ar5312GpioSet;
ahp->ah_priv.ah_gpioSetIntr = ar5312GpioSetIntr;
}
ah->ah_gpioCfgInput = ahp->ah_priv.ah_gpioCfgInput;
ah->ah_gpioCfgOutput = ahp->ah_priv.ah_gpioCfgOutput;
ah->ah_gpioGet = ahp->ah_priv.ah_gpioGet;
ah->ah_gpioSet = ahp->ah_priv.ah_gpioSet;
ah->ah_gpioSetIntr = ahp->ah_priv.ah_gpioSetIntr;
/* setup common ini data; rf backends handle remainder */
HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);
HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);
if (!ar5312ChipReset(ah, AH_NULL)) { /* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
ecode = HAL_EIO;
goto bad;
}
#if ( AH_SUPPORT_2316 || AH_SUPPORT_2317)
if ((devid == AR5212_AR2315_REV6) ||
(devid == AR5212_AR2315_REV7) ||
(devid == AR5212_AR2317_REV1) ||
(devid == AR5212_AR2317_REV2) ) {
val = ((OS_REG_READ(ah, (AR5315_RSTIMER_BASE -((uint32_t) sh)) + AR5315_WREV)) >> AR5315_WREV_S)
& AR5315_WREV_ID;
AH_PRIVATE(ah)->ah_macVersion = val >> AR5315_WREV_ID_S;
AH_PRIVATE(ah)->ah_macRev = val & AR5315_WREV_REVISION;
HALDEBUG(ah, HAL_DEBUG_ATTACH,
"%s: Mac Chip Rev 0x%02x.%x\n" , __func__,
AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev);
} else
#endif
{
HAL_BOOL
ar5416ProcessRadarEvent(struct ath_hal *ah, struct ath_rx_status *rxs,
uint64_t fulltsf, const char *buf, HAL_DFS_EVENT *event)
{
HAL_BOOL doDfsExtCh;
HAL_BOOL doDfsEnhanced;
HAL_BOOL doDfsCombinedRssi;
uint8_t rssi = 0, ext_rssi = 0;
uint8_t pulse_bw_info = 0, pulse_length_ext = 0, pulse_length_pri = 0;
uint32_t dur = 0;
int pri_found = 1, ext_found = 0;
int early_ext = 0;
int is_dc = 0;
uint16_t datalen; /* length from the RX status field */
/* Check whether the given phy error is a radar event */
if ((rxs->rs_phyerr != HAL_PHYERR_RADAR) &&
(rxs->rs_phyerr != HAL_PHYERR_FALSE_RADAR_EXT)) {
return AH_FALSE;
}
/* Grab copies of the capabilities; just to make the code clearer */
doDfsExtCh = AH_PRIVATE(ah)->ah_caps.halExtChanDfsSupport;
doDfsEnhanced = AH_PRIVATE(ah)->ah_caps.halEnhancedDfsSupport;
doDfsCombinedRssi = AH_PRIVATE(ah)->ah_caps.halUseCombinedRadarRssi;
datalen = rxs->rs_datalen;
/* If hardware supports it, use combined RSSI, else use chain 0 RSSI */
if (doDfsCombinedRssi)
rssi = (uint8_t) rxs->rs_rssi;
else
rssi = (uint8_t) rxs->rs_rssi_ctl[0];
/* Set this; but only use it if doDfsExtCh is set */
ext_rssi = (uint8_t) rxs->rs_rssi_ext[0];
/* Cap it at 0 if the RSSI is a negative number */
if (rssi & 0x80)
rssi = 0;
if (ext_rssi & 0x80)
ext_rssi = 0;
/*
* Fetch the relevant data from the frame
*/
if (doDfsExtCh) {
if (datalen < 3)
return AH_FALSE;
/* Last three bytes of the frame are of interest */
pulse_length_pri = *(buf + datalen - 3);
pulse_length_ext = *(buf + datalen - 2);
pulse_bw_info = *(buf + datalen - 1);
HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, ext_rssi=%d, pulse_length_pri=%d,"
" pulse_length_ext=%d, pulse_bw_info=%x\n",
__func__, rssi, ext_rssi, pulse_length_pri, pulse_length_ext,
pulse_bw_info);
} else {
/* The pulse width is byte 0 of the data */
if (datalen >= 1)
dur = ((uint8_t) buf[0]) & 0xff;
else
dur = 0;
if (dur == 0 && rssi == 0) {
HALDEBUG(ah, HAL_DEBUG_DFS, "%s: dur and rssi are 0\n", __func__);
return AH_FALSE;
}
HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, dur=%d\n", __func__, rssi, dur);
/* Single-channel only */
pri_found = 1;
ext_found = 0;
}
/*
* If doing extended channel data, pulse_bw_info must
* have one of the flags set.
*/
if (doDfsExtCh && pulse_bw_info == 0x0)
return AH_FALSE;
/*
* If the extended channel data is available, calculate
* which to pay attention to.
*/
if (doDfsExtCh) {
/* If pulse is on DC, take the larger duration of the two */
if ((pulse_bw_info & EXT_CH_RADAR_FOUND) &&
(pulse_bw_info & PRI_CH_RADAR_FOUND)) {
is_dc = 1;
if (pulse_length_ext > pulse_length_pri) {
dur = pulse_length_ext;
pri_found = 0;
ext_found = 1;
} else {
dur = pulse_length_pri;
pri_found = 1;
ext_found = 0;
}
} else if (pulse_bw_info & EXT_CH_RADAR_EARLY_FOUND) {
dur = pulse_length_ext;
pri_found = 0;
ext_found = 1;
early_ext = 1;
} else if (pulse_bw_info & PRI_CH_RADAR_FOUND) {
dur = pulse_length_pri;
pri_found = 1;
ext_found = 0;
} else if (pulse_bw_info & EXT_CH_RADAR_FOUND) {
dur = pulse_length_ext;
pri_found = 0;
ext_found = 1;
}
}
/*
* For enhanced DFS (Merlin and later), pulse_bw_info has
* implications for selecting the correct RSSI value.
*/
if (doDfsEnhanced) {
switch (pulse_bw_info & 0x03) {
case 0:
/* No radar? */
rssi = 0;
break;
case PRI_CH_RADAR_FOUND:
/* Radar in primary channel */
/* Cannot use ctrl channel RSSI if ext channel is stronger */
if (ext_rssi >= (rssi + 3)) {
rssi = 0;
}
break;
case EXT_CH_RADAR_FOUND:
/* Radar in extended channel */
/* Cannot use ext channel RSSI if ctrl channel is stronger */
if (rssi >= (ext_rssi + 12)) {
rssi = 0;
} else {
rssi = ext_rssi;
}
break;
case (PRI_CH_RADAR_FOUND | EXT_CH_RADAR_FOUND):
/* When both are present, use stronger one */
if (rssi < ext_rssi)
rssi = ext_rssi;
break;
}
}
/*
* If not doing enhanced DFS, choose the ext channel if
* it is stronger than the main channel
*/
if (doDfsExtCh && !doDfsEnhanced) {
if ((ext_rssi > rssi) && (ext_rssi < 128))
rssi = ext_rssi;
}
/*
* XXX what happens if the above code decides the RSSI
* XXX wasn't valid, an sets it to 0?
*/
/*
* Fill out dfs_event structure.
*/
event->re_full_ts = fulltsf;
event->re_ts = rxs->rs_tstamp;
event->re_rssi = rssi;
event->re_dur = dur;
event->re_flags = 0;
if (pri_found)
event->re_flags |= HAL_DFS_EVENT_PRICH;
if (ext_found)
event->re_flags |= HAL_DFS_EVENT_EXTCH;
if (early_ext)
event->re_flags |= HAL_DFS_EVENT_EXTEARLY;
if (is_dc)
event->re_flags |= HAL_DFS_EVENT_ISDC;
return AH_TRUE;
}
static void
ar9285AniSetup(struct ath_hal *ah)
{
/*
* These are the parameters from the AR5416 ANI code;
* they likely need quite a bit of adjustment for the
* AR9285.
*/
static const struct ar5212AniParams aniparams = {
.maxNoiseImmunityLevel = 4, /* levels 0..4 */
.totalSizeDesired = { -55, -55, -55, -55, -62 },
.coarseHigh = { -14, -14, -14, -14, -12 },
.coarseLow = { -64, -64, -64, -64, -70 },
.firpwr = { -78, -78, -78, -78, -80 },
.maxSpurImmunityLevel = 2,
.cycPwrThr1 = { 2, 4, 6 },
.maxFirstepLevel = 2, /* levels 0..2 */
.firstep = { 0, 4, 8 },
.ofdmTrigHigh = 500,
.ofdmTrigLow = 200,
.cckTrigHigh = 200,
.cckTrigLow = 100,
.rssiThrHigh = 40,
.rssiThrLow = 7,
.period = 100,
};
/* NB: disable ANI noise immmunity for reliable RIFS rx */
AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
}
/*
* Attach for an AR9285 part.
*/
static struct ath_hal *
ar9285Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
HAL_STATUS *status)
{
struct ath_hal_9285 *ahp9285;
struct ath_hal_5212 *ahp;
struct ath_hal *ah;
uint32_t val;
HAL_STATUS ecode;
HAL_BOOL rfStatus;
HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
__func__, sc, (void*) st, (void*) sh);
/* NB: memory is returned zero'd */
ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285));
if (ahp9285 == AH_NULL) {
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
"%s: cannot allocate memory for state block\n", __func__);
*status = HAL_ENOMEM;
return AH_NULL;
}
ahp = AH5212(ahp9285);
ah = &ahp->ah_priv.h;
ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
/*
* Use the "local" EEPROM data given to us by the higher layers.
* This is a private copy out of system flash. The Linux ath9k
* commit for the initial AR9130 support mentions MMIO flash
* access is "unreliable." -adrian
*/
if (eepromdata != AH_NULL) {
AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;
AH_PRIVATE(ah)->ah_eepromWrite = NULL;
ah->ah_eepromdata = eepromdata;
}
/* XXX override with 9285 specific state */
/* override 5416 methods for our needs */
AH5416(ah)->ah_initPLL = ar9280InitPLL;
ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
ah->ah_configPCIE = ar9285ConfigPCIE;
ah->ah_disablePCIE = ar9285DisablePCIE;
ah->ah_setTxPower = ar9285SetTransmitPower;
ah->ah_setBoardValues = ar9285SetBoardValues;
AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
AH5416(ah)->ah_writeIni = ar9285WriteIni;
AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1;
if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
/* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
__func__);
ecode = HAL_EIO;
goto bad;
}
if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
__func__);
ecode = HAL_EIO;
goto bad;
}
/* Read Revisions from Chips before taking out of reset */
val = OS_REG_READ(ah, AR_SREV);
HALDEBUG(ah, HAL_DEBUG_ATTACH,
"%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
__func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
/* NB: include chip type to differentiate from pre-Sowl versions */
AH_PRIVATE(ah)->ah_macVersion =
(val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
/* setup common ini data; rf backends handle remainder */
if (AR_SREV_KITE_12_OR_LATER(ah)) {
HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
ar9285PciePhy_clkreq_always_on_L1_v2, 2);
} else {
HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
ar9285PciePhy_clkreq_always_on_L1, 2);
}
ar5416AttachPCIE(ah);
/* Attach methods that require MAC version/revision info */
if (AR_SREV_KITE_12_OR_LATER(ah))
AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware;
if (AR_SREV_KITE_11_OR_LATER(ah))
AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal;
ecode = ath_hal_v4kEepromAttach(ah);
if (ecode != HAL_OK)
goto bad;
if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
__func__);
ecode = HAL_EIO;
goto bad;
}
AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
if (!ar5212ChipTest(ah)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
__func__);
ecode = HAL_ESELFTEST;
goto bad;
}
/*
* Set correct Baseband to analog shift
* setting to access analog chips.
*/
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
/* Read Radio Chip Rev Extract */
AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
break;
default:
if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
AH_PRIVATE(ah)->ah_analog5GhzRev =
AR_RAD5133_SREV_MAJOR;
break;
}
#ifdef AH_DEBUG
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: 5G Radio Chip Rev 0x%02X is not supported by "
"this driver\n", __func__,
AH_PRIVATE(ah)->ah_analog5GhzRev);
ecode = HAL_ENOTSUPP;
goto bad;
#endif
}
rfStatus = ar9285RfAttach(ah, &ecode);
if (!rfStatus) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
__func__, ecode);
goto bad;
}
HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2,
6);
if (AR_SREV_9285E_20(ah))
ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n");
/* setup txgain table */
switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
case AR5416_EEP_TXGAIN_HIGH_POWER:
if (AR_SREV_9285E_20(ah))
HAL_INI_INIT(&ahp9285->ah_ini_txgain,
ar9285Modes_XE2_0_high_power, 6);
else
HAL_INI_INIT(&ahp9285->ah_ini_txgain,
ar9285Modes_high_power_tx_gain_v2, 6);
break;
case AR5416_EEP_TXGAIN_ORIG:
if (AR_SREV_9285E_20(ah))
HAL_INI_INIT(&ahp9285->ah_ini_txgain,
ar9285Modes_XE2_0_normal_power, 6);
else
HAL_INI_INIT(&ahp9285->ah_ini_txgain,
ar9285Modes_original_tx_gain_v2, 6);
break;
default:
HALASSERT(AH_FALSE);
goto bad; /* XXX ? try to continue */
}
/*
* Got everything we need now to setup the capabilities.
*/
if (!ar9285FillCapabilityInfo(ah)) {
ecode = HAL_EEREAD;
goto bad;
}
/* Print out whether the EEPROM settings enable AR9285 diversity */
if (ar9285_check_div_comb(ah)) {
ath_hal_printf(ah, "[ath] Enabling diversity for Kite\n");
ah->ah_rxAntCombDiversity = ar9285_ant_comb_scan;
}
/* Disable 11n for the AR2427 */
if (devid == AR2427_DEVID_PCIE)
AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE;
ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
if (ecode != HAL_OK) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error getting mac address from EEPROM\n", __func__);
goto bad;
}
/* XXX How about the serial number ? */
/* Read Reg Domain */
AH_PRIVATE(ah)->ah_currentRD =
ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
/*
* For Kite and later chipsets, the following bits are not
* programmed in EEPROM and so are set as enabled always.
*/
AH_PRIVATE(ah)->ah_currentRDext = AR9285_RDEXT_DEFAULT;
/*
* ah_miscMode is populated by ar5416FillCapabilityInfo()
* starting from griffin. Set here to make sure that
* AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
* placed into hardware.
*/
if (ahp->ah_miscMode != 0)
OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
ar9285AniSetup(ah); /* Anti Noise Immunity */
/* Setup noise floor min/max/nominal values */
AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
/* XXX no 5ghz values? */
ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
return ah;
bad:
if (ah != AH_NULL)
ah->ah_detach(ah);
if (status)
*status = ecode;
return AH_NULL;
}
static void
ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
{
uint32_t val;
/*
* This workaround needs some integration work with the HAL
* config parameters and the if_ath_pci.c glue.
* Specifically, read the value of the PCI register 0x70c
* (4 byte PCI config space register) and store it in ath_hal_war70c.
* Then if it's non-zero, the below WAR would override register
* 0x570c upon suspend/resume.
*/
#if 0
if (AR_SREV_9285E_20(ah)) {
val = AH_PRIVATE(ah)->ah_config.ath_hal_war70c;
if (val) {
val &= 0xffff00ff;
val |= 0x6f00;
OS_REG_WRITE(ah, 0x570c, val);
}
}
#endif
if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
OS_DELAY(1000);
}
/*
* Set PCIe workaround bits
*
* NOTE:
*
* In Merlin and Kite, bit 14 in WA register (disable L1) should only
* be set when device enters D3 and be cleared when device comes back
* to D0.
*/
if (power_off) { /* Power-off */
OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
val = OS_REG_READ(ah, AR_WA);
/*
* Disable bit 6 and 7 before entering D3 to prevent
* system hang.
*/
val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
/*
* See above: set AR_WA_D3_L1_DISABLE when entering D3 state.
*
* XXX The reference HAL does it this way - it only sets
* AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT,
* which it (currently) isn't. So the following statement
* is currently a NOP.
*/
if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)
val |= AR_WA_D3_L1_DISABLE;
if (AR_SREV_9285E_20(ah))
val |= AR_WA_BIT23;
OS_REG_WRITE(ah, AR_WA, val);
} else { /* Power-on */
val = AR9285_WA_DEFAULT;
/*
* See note above: make sure L1_DISABLE is not set.
*/
val &= (~AR_WA_D3_L1_DISABLE);
/* Software workaroud for ASPM system hang. */
val |= (AR_WA_BIT6 | AR_WA_BIT7);
if (AR_SREV_9285E_20(ah))
val |= AR_WA_BIT23;
OS_REG_WRITE(ah, AR_WA, val);
/* set bit 19 to allow forcing of pcie core into L1 state */
OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
}
}
/*
* Places the device in and out of reset and then places sane
* values in the registers based on EEPROM config, initialization
* vectors (as determined by the mode), and station configuration
*
* bChannelChange is used to preserve DMA/PCU registers across
* a HW Reset during channel change.
*/
HAL_BOOL
ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
struct ieee80211_channel *chan,
HAL_BOOL bChannelChange,
HAL_RESET_TYPE resetType,
HAL_STATUS *status)
{
#define N(a) (sizeof (a) / sizeof (a[0]))
#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
struct ath_hal_5212 *ahp = AH5212(ah);
HAL_CHANNEL_INTERNAL *ichan;
const HAL_EEPROM *ee;
uint32_t saveFrameSeqCount, saveDefAntenna;
uint32_t macStaId1, synthDelay, txFrm2TxDStart;
uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL];
int16_t cckOfdmPwrDelta = 0;
u_int modesIndex, freqIndex;
HAL_STATUS ecode;
int i, regWrites = 0;
uint32_t testReg;
uint32_t saveLedState = 0;
HALASSERT(ah->ah_magic == AR5212_MAGIC);
ee = AH_PRIVATE(ah)->ah_eeprom;
OS_MARK(ah, AH_MARK_RESET, bChannelChange);
/*
* Map public channel to private.
*/
ichan = ath_hal_checkchannel(ah, chan);
if (ichan == AH_NULL) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u/0x%x; no mapping\n",
__func__, chan->ic_freq, chan->ic_flags);
FAIL(HAL_EINVAL);
}
switch (opmode) {
case HAL_M_STA:
case HAL_M_IBSS:
case HAL_M_HOSTAP:
case HAL_M_MONITOR:
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
__func__, opmode);
FAIL(HAL_EINVAL);
break;
}
HALASSERT(ahp->ah_eeversion >= AR_EEPROM_VER3);
/* Preserve certain DMA hardware registers on a channel change */
if (bChannelChange) {
/*
* On Venice, the TSF is almost preserved across a reset;
* it requires the doubling writes to the RESET_TSF
* bit in the AR_BEACON register; it also has the quirk
* of the TSF going back in time on the station (station
* latches onto the last beacon's tsf during a reset 50%
* of the times); the latter is not a problem for adhoc
* stations since as long as the TSF is behind, it will
* get resynchronized on receiving the next beacon; the
* TSF going backwards in time could be a problem for the
* sleep operation (supported on infrastructure stations
* only) - the best and most general fix for this situation
* is to resynchronize the various sleep/beacon timers on
* the receipt of the next beacon i.e. when the TSF itself
* gets resynchronized to the AP's TSF - power save is
* needed to be temporarily disabled until that time
*
* Need to save the sequence number to restore it after
* the reset!
*/
saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM);
} else
saveFrameSeqCount = 0; /* NB: silence compiler */
/* If the channel change is across the same mode - perform a fast channel change */
if ((IS_2413(ah) || IS_5413(ah))) {
/*
* Channel change can only be used when:
* -channel change requested - so it's not the initial reset.
* -it's not a change to the current channel - often called when switching modes
* on a channel
* -the modes of the previous and requested channel are the same - some ugly code for XR
*/
if (bChannelChange &&
AH_PRIVATE(ah)->ah_curchan != AH_NULL &&
(chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) &&
((chan->ic_flags & IEEE80211_CHAN_ALLTURBO) ==
(AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) {
if (ar5212ChannelChange(ah, chan))
/* If ChannelChange completed - skip the rest of reset */
return AH_TRUE;
}
}
/*
* Preserve the antenna on a channel change
*/
saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
if (saveDefAntenna == 0) /* XXX magic constants */
saveDefAntenna = 1;
/* Save hardware flag before chip reset clears the register */
macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &
(AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT);
/* Save led state from pci config register */
if (!IS_5315(ah))
saveLedState = OS_REG_READ(ah, AR5312_PCICFG) &
(AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK |
AR_PCICFG_LEDSLOW);
ar5312RestoreClock(ah, opmode); /* move to refclk operation */
/*
* Adjust gain parameters before reset if
* there's an outstanding gain updated.
*/
(void) ar5212GetRfgain(ah);
if (!ar5312ChipReset(ah, chan)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
FAIL(HAL_EIO);
}
/* Setup the indices for the next set of register array writes */
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
freqIndex = 2;
modesIndex = IEEE80211_IS_CHAN_108G(chan) ? 5 :
IEEE80211_IS_CHAN_G(chan) ? 4 : 3;
} else {
freqIndex = 1;
modesIndex = IEEE80211_IS_CHAN_ST(chan) ? 2 : 1;
}
OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
/* Set correct Baseband to analog shift setting to access analog chips. */
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0);
regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange,
regWrites);
ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))
ar5212SetIFSTiming(ah, chan);
/* Overwrite INI values for revised chipsets */
if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {
/* ADC_CTL */
OS_REG_WRITE(ah, AR_PHY_ADC_CTL,
SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) |
SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) |
AR_PHY_ADC_CTL_OFF_PWDDAC |
AR_PHY_ADC_CTL_OFF_PWDADC);
/* TX_PWR_ADJ */
if (chan->channel == 2484) {
cckOfdmPwrDelta = SCALE_OC_DELTA(ee->ee_cckOfdmPwrDelta - ee->ee_scaledCh14FilterCckDelta);
} else {
cckOfdmPwrDelta = SCALE_OC_DELTA(ee->ee_cckOfdmPwrDelta);
}
if (IEEE80211_IS_CHAN_G(chan)) {
OS_REG_WRITE(ah, AR_PHY_TXPWRADJ,
SM((ee->ee_cckOfdmPwrDelta*-1), AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) |
SM((cckOfdmPwrDelta*-1), AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX));
} else {
OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0);
}
/* Add barker RSSI thresh enable as disabled */
OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK,
AR_PHY_DAG_CTRLCCK_EN_RSSI_THR);
OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK,
AR_PHY_DAG_CTRLCCK_RSSI_THR, 2);
/* Set the mute mask to the correct default */
OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);
}
if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) {
/* Clear reg to alllow RX_CLEAR line debug */
OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0);
}
if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) {
#ifdef notyet
/* Enable burst prefetch for the data queues */
OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
/* Enable double-buffering */
OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS);
#endif
}
if (IS_5312_2_X(ah)) {
/* ADC_CTRL */
OS_REG_WRITE(ah, AR_PHY_SIGMA_DELTA,
SM(2, AR_PHY_SIGMA_DELTA_ADC_SEL) |
SM(4, AR_PHY_SIGMA_DELTA_FILT2) |
SM(0x16, AR_PHY_SIGMA_DELTA_FILT1) |
SM(0, AR_PHY_SIGMA_DELTA_ADC_CLIP));
if (IEEE80211_IS_CHAN_2GHZ(chan))
OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, AR_PHY_RXGAIN_TXRX_RF_MAX, 0x0F);
/* CCK Short parameter adjustment in 11B mode */
if (IEEE80211_IS_CHAN_B(chan))
OS_REG_RMW_FIELD(ah, AR_PHY_CCK_RXCTRL4, AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT, 12);
/* Set ADC/DAC select values */
OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);
/* Increase 11A AGC Settling */
if (IEEE80211_IS_CHAN_A(chan))
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_AGC, 32);
} else {
/* Set ADC/DAC select values */
OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
}
/* Setup the transmit power values. */
if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error init'ing transmit power\n", __func__);
FAIL(HAL_EIO);
}
/* Write the analog registers */
if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n",
__func__);
FAIL(HAL_EIO);
}
/* Write delta slope for OFDM enabled modes (A, G, Turbo) */
if (IEEE80211_IS_CHAN_OFDM(chan)) {
if (IS_5413(ah) ||
AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)
ar5212SetSpurMitigation(ah, chan);
ar5212SetDeltaSlope(ah, chan);
}
/* Setup board specific options for EEPROM version 3 */
if (!ar5212SetBoardValues(ah, chan)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error setting board options\n", __func__);
FAIL(HAL_EIO);
}
/* Restore certain DMA hardware registers on a channel change */
if (bChannelChange)
OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount);
OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
| macStaId1
| AR_STA_ID1_RTS_USE_DEF
| ahp->ah_staId1Defaults
);
ar5212SetOperatingMode(ah, opmode);
/* Set Venice BSSID mask according to current state */
OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
/* Restore previous led state */
if (!IS_5315(ah))
OS_REG_WRITE(ah, AR5312_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState);
/* Restore previous antenna */
OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
/* then our BSSID */
OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
/* Restore bmiss rssi & count thresholds */
OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */
if (!ar5212SetChannel(ah, chan))
FAIL(HAL_EIO);
OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);
ar5212SetRateDurationTable(ah, chan);
/* Set Tx frame start to tx data start delay */
if (IS_RAD5112_ANY(ah) &&
(IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))) {
txFrm2TxDStart =
IEEE80211_IS_CHAN_HALF(chan) ?
TX_FRAME_D_START_HALF_RATE:
TX_FRAME_D_START_QUARTER_RATE;
OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL,
AR_PHY_TX_FRAME_TO_TX_DATA_START, txFrm2TxDStart);
}
/*
* Setup fast diversity.
* Fast diversity can be enabled or disabled via regadd.txt.
* Default is enabled.
* For reference,
* Disable: reg val
* 0x00009860 0x00009d18 (if 11a / 11g, else no change)
* 0x00009970 0x192bb514
* 0x0000a208 0xd03e4648
*
* Enable: 0x00009860 0x00009d10 (if 11a / 11g, else no change)
* 0x00009970 0x192fb514
* 0x0000a208 0xd03e6788
*/
/* XXX Setup pre PHY ENABLE EAR additions */
/* flush SCAL reg */
if (IS_5312_2_X(ah)) {
(void) OS_REG_READ(ah, AR_PHY_SLEEP_SCAL);
}
/*
* Wait for the frequency synth to settle (synth goes on
* via AR_PHY_ACTIVE_EN). Read the phy active delay register.
* Value is in 100ns increments.
*/
synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
if (IEEE80211_IS_CHAN_B(chan)) {
synthDelay = (4 * synthDelay) / 22;
} else {
synthDelay /= 10;
}
/* Activate the PHY (includes baseband activate and synthesizer on) */
OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
/*
* There is an issue if the AP starts the calibration before
* the base band timeout completes. This could result in the
* rx_clear false triggering. As a workaround we add delay an
* extra BASE_ACTIVATE_DELAY usecs to ensure this condition
* does not happen.
*/
if (IEEE80211_IS_CHAN_HALF(chan)) {
OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY);
} else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY);
} else {
OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
}
/*
* The udelay method is not reliable with notebooks.
* Need to check to see if the baseband is ready
*/
testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL);
/* Selects the Tx hold */
OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD);
i = 0;
while ((i++ < 20) &&
(OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */ OS_DELAY(200);
OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg);
/* Calibrate the AGC and start a NF calculation */
OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
OS_REG_READ(ah, AR_PHY_AGC_CONTROL)
| AR_PHY_AGC_CONTROL_CAL
| AR_PHY_AGC_CONTROL_NF);
if (!IEEE80211_IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) {
/* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
INIT_IQCAL_LOG_COUNT_MAX);
OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
AR_PHY_TIMING_CTRL4_DO_IQCAL);
ahp->ah_bIQCalibration = IQ_CAL_RUNNING;
} else
ahp->ah_bIQCalibration = IQ_CAL_INACTIVE;
/* Setup compression registers */
ar5212SetCompRegs(ah);
/* Set 1:1 QCU to DCU mapping for all queues */
for (i = 0; i < AR_NUM_DCU; i++)
OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
ahp->ah_intrTxqs = 0;
for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++)
ar5212ResetTxQueue(ah, i);
/*
* Setup interrupt handling. Note that ar5212ResetTxQueue
* manipulates the secondary IMR's as queues are enabled
* and disabled. This is done with RMW ops to insure the
* settings we make here are preserved.
*/
ahp->ah_maskReg = AR_IMR_TXOK | AR_IMR_TXERR | AR_IMR_TXURN
| AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXORN
| AR_IMR_HIUERR
;
if (opmode == HAL_M_HOSTAP)
ahp->ah_maskReg |= AR_IMR_MIB;
OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
/* Enable bus errors that are OR'd to set the HIUERR bit */
OS_REG_WRITE(ah, AR_IMR_S2,
OS_REG_READ(ah, AR_IMR_S2)
| AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR);
if (AH_PRIVATE(ah)->ah_rfkillEnabled)
ar5212EnableRfKill(ah);
if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: offset calibration failed to complete in 1ms;"
" noisy environment?\n", __func__);
}
/*
* Set clocks back to 32kHz if they had been using refClk, then
* use an external 32kHz crystal when sleeping, if one exists.
*/
ar5312SetupClock(ah, opmode);
/*
* Writing to AR_BEACON will start timers. Hence it should
* be the last register to be written. Do not reset tsf, do
* not enable beacons at this point, but preserve other values
* like beaconInterval.
*/
OS_REG_WRITE(ah, AR_BEACON,
(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
/* XXX Setup post reset EAR additions */
/* QoS support */
if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE ||
(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) {
OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */
OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */
}
/* Turn on NOACK Support for QoS packets */
OS_REG_WRITE(ah, AR_NOACK,
SM(2, AR_NOACK_2BIT_VALUE) |
SM(5, AR_NOACK_BIT_OFFSET) |
SM(0, AR_NOACK_BYTE_OFFSET));
/* Restore user-specified settings */
if (ahp->ah_miscMode != 0)
OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
if (ahp->ah_slottime != (u_int) -1)
ar5212SetSlotTime(ah, ahp->ah_slottime);
if (ahp->ah_acktimeout != (u_int) -1)
ar5212SetAckTimeout(ah, ahp->ah_acktimeout);
if (ahp->ah_ctstimeout != (u_int) -1)
ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout);
if (ahp->ah_sifstime != (u_int) -1)
ar5212SetSifsTime(ah, ahp->ah_sifstime);
if (AH_PRIVATE(ah)->ah_diagreg != 0)
OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
OS_MARK(ah, AH_MARK_RESET_DONE, 0);
return AH_TRUE;
bad:
OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
if (status != AH_NULL)
*status = ecode;
return AH_FALSE;
#undef FAIL
#undef N
}
/*
* Places the hardware into reset and then pulls it out of reset
*
* TODO: Only write the PLL if we're changing to or from CCK mode
*
* WARNING: The order of the PLL and mode registers must be correct.
*/
HAL_BOOL
ar5312ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);
/*
* Reset the HW
*/
if (!ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n",
__func__);
return AH_FALSE;
}
/* Bring out of sleep mode (AGAIN) */
if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetPowerMode failed\n",
__func__);
return AH_FALSE;
}
/* Clear warm reset register */
if (!ar5312SetResetReg(ah, 0)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n",
__func__);
return AH_FALSE;
}
/*
* Perform warm reset before the mode/PLL/turbo registers
* are changed in order to deactivate the radio. Mode changes
* with an active radio can result in corrupted shifts to the
* radio device.
*/
/*
* Set CCK and Turbo modes correctly.
*/
if (chan != AH_NULL) { /* NB: can be null during attach */
uint32_t rfMode, phyPLL = 0, curPhyPLL, turbo;
if (IS_RAD5112_ANY(ah)) {
rfMode = AR_PHY_MODE_AR5112;
if (!IS_5315(ah)) {
if (IEEE80211_IS_CHAN_CCK(chan)) {
phyPLL = AR_PHY_PLL_CTL_44_5312;
} else {
if (IEEE80211_IS_CHAN_HALF(chan)) {
phyPLL = AR_PHY_PLL_CTL_40_5312_HALF;
} else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
phyPLL = AR_PHY_PLL_CTL_40_5312_QUARTER;
} else {
phyPLL = AR_PHY_PLL_CTL_40_5312;
}
}
} else {
if (IEEE80211_IS_CHAN_CCK(chan))
phyPLL = AR_PHY_PLL_CTL_44_5112;
else
phyPLL = AR_PHY_PLL_CTL_40_5112;
if (IEEE80211_IS_CHAN_HALF(chan))
phyPLL |= AR_PHY_PLL_CTL_HALF;
else if (IEEE80211_IS_CHAN_QUARTER(chan))
phyPLL |= AR_PHY_PLL_CTL_QUARTER;
}
} else {
rfMode = AR_PHY_MODE_AR5111;
if (IEEE80211_IS_CHAN_CCK(chan))
phyPLL = AR_PHY_PLL_CTL_44;
else
phyPLL = AR_PHY_PLL_CTL_40;
if (IEEE80211_IS_CHAN_HALF(chan))
phyPLL = AR_PHY_PLL_CTL_HALF;
else if (IEEE80211_IS_CHAN_QUARTER(chan))
phyPLL = AR_PHY_PLL_CTL_QUARTER;
}
if (IEEE80211_IS_CHAN_G(chan))
rfMode |= AR_PHY_MODE_DYNAMIC;
else if (IEEE80211_IS_CHAN_OFDM(chan))
rfMode |= AR_PHY_MODE_OFDM;
else
rfMode |= AR_PHY_MODE_CCK;
if (IEEE80211_IS_CHAN_5GHZ(chan))
rfMode |= AR_PHY_MODE_RF5GHZ;
else
rfMode |= AR_PHY_MODE_RF2GHZ;
turbo = IEEE80211_IS_CHAN_TURBO(chan) ?
(AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0;
curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL);
/*
* PLL, Mode, and Turbo values must be written in the correct
* order to ensure:
* - The PLL cannot be set to 44 unless the CCK or DYNAMIC
* mode bit is set
* - Turbo cannot be set at the same time as CCK or DYNAMIC
*/
if (IEEE80211_IS_CHAN_CCK(chan)) {
OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
if (curPhyPLL != phyPLL) {
OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL);
/* Wait for the PLL to settle */
OS_DELAY(PLL_SETTLE_DELAY);
}
} else {
if (curPhyPLL != phyPLL) {
OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL);
/* Wait for the PLL to settle */
OS_DELAY(PLL_SETTLE_DELAY);
}
OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
}
}
return AH_TRUE;
}
/*
* Restore the ANI parameters in the HAL and reset the statistics.
* This routine should be called for every hardware reset and for
* every channel change.
*/
void
ar9300_ani_reset(struct ath_hal *ah, HAL_BOOL is_scanning)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
int index;
HALASSERT(chan != AH_NULL);
if (!DO_ANI(ah)) {
return;
}
/*
* we need to re-point to the correct ANI state since the channel
* may have changed due to a fast channel change
*/
index = ar9300_get_ani_channel_index(ah, chan);
ani_state = &ahp->ah_ani[index];
HALASSERT(ani_state != AH_NULL);
ahp->ah_curani = ani_state;
ahp->ah_stats.ast_ani_reset++;
ani_state->phy_noise_spur = 0;
/* only allow a subset of functions in AP mode */
if (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP) {
if (IS_CHAN_2GHZ(ichan)) {
ahp->ah_ani_function = (HAL_ANI_SPUR_IMMUNITY_LEVEL |
HAL_ANI_FIRSTEP_LEVEL |
HAL_ANI_MRC_CCK);
} else {
ahp->ah_ani_function = 0;
}
}
/* always allow mode (on/off) to be controlled */
ahp->ah_ani_function |= HAL_ANI_MODE;
if (is_scanning ||
(AH_PRIVATE(ah)->ah_opmode != HAL_M_STA &&
AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS))
{
/*
* If we're scanning or in AP mode, the defaults (ini) should be
* in place.
* For an AP we assume the historical levels for this channel are
* probably outdated so start from defaults instead.
*/
if (ani_state->ofdm_noise_immunity_level != HAL_ANI_OFDM_DEF_LEVEL ||
ani_state->cck_noise_immunity_level != HAL_ANI_CCK_DEF_LEVEL)
{
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: Restore defaults: opmode %u chan %d Mhz/0x%x "
"is_scanning=%d restore=%d ofdm:%d cck:%d\n",
__func__, AH_PRIVATE(ah)->ah_opmode, chan->ic_freq,
chan->ic_flags, is_scanning, ani_state->must_restore,
ani_state->ofdm_noise_immunity_level,
ani_state->cck_noise_immunity_level);
/*
* for STA/IBSS, we want to restore the historical values later
* (when we're not scanning)
*/
if (AH_PRIVATE(ah)->ah_opmode == HAL_M_STA ||
AH_PRIVATE(ah)->ah_opmode == HAL_M_IBSS)
{
ar9300_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
HAL_ANI_DEF_SPUR_IMMUNE_LVL);
ar9300_ani_control(
ah, HAL_ANI_FIRSTEP_LEVEL, HAL_ANI_DEF_FIRSTEP_LVL);
ar9300_ani_control(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
HAL_ANI_USE_OFDM_WEAK_SIG);
ar9300_ani_control(ah, HAL_ANI_MRC_CCK, HAL_ANI_ENABLE_MRC_CCK);
ani_state->must_restore = AH_TRUE;
} else {
ar9300_ani_set_odfm_noise_immunity_level(
ah, HAL_ANI_OFDM_DEF_LEVEL);
ar9300_ani_set_cck_noise_immunity_level(
ah, HAL_ANI_CCK_DEF_LEVEL);
}
}
} else {
/*
* restore historical levels for this channel
*/
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d "
"restore=%d ofdm:%d cck:%d\n",
__func__, AH_PRIVATE(ah)->ah_opmode, chan->ic_freq,
chan->ic_flags, is_scanning, ani_state->must_restore,
ani_state->ofdm_noise_immunity_level,
ani_state->cck_noise_immunity_level);
ar9300_ani_set_odfm_noise_immunity_level(
ah, ani_state->ofdm_noise_immunity_level);
ar9300_ani_set_cck_noise_immunity_level(
ah, ani_state->cck_noise_immunity_level);
ani_state->must_restore = AH_FALSE;
}
/* enable phy counters */
ar9300_ani_restart(ah);
OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
}
/*
* Internal interface to schedule periodic calibration work.
*/
HAL_BOOL
ar5416PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,
u_int rxchainmask, HAL_BOOL longcal, HAL_BOOL *isCalDone)
{
struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
HAL_CAL_LIST *currCal = cal->cal_curr;
HAL_CHANNEL_INTERNAL *ichan;
int r;
OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq);
*isCalDone = AH_TRUE;
/*
* Since ath_hal calls the PerCal method with rxchainmask=0x1;
* override it with the current chainmask. The upper levels currently
* doesn't know about the chainmask.
*/
rxchainmask = AH5416(ah)->ah_rx_chainmask;
/* Invalid channel check */
ichan = ath_hal_checkchannel(ah, chan);
if (ichan == AH_NULL) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u/0x%x; no mapping\n",
__func__, chan->ic_freq, chan->ic_flags);
return AH_FALSE;
}
/*
* For given calibration:
* 1. Call generic cal routine
* 2. When this cal is done (isCalDone) if we have more cals waiting
* (eg after reset), mask this to upper layers by not propagating
* isCalDone if it is set to TRUE.
* Instead, change isCalDone to FALSE and setup the waiting cal(s)
* to be run.
*/
if (currCal != AH_NULL &&
(currCal->calState == CAL_RUNNING ||
currCal->calState == CAL_WAITING)) {
ar5416DoCalibration(ah, ichan, rxchainmask, currCal, isCalDone);
if (*isCalDone == AH_TRUE) {
cal->cal_curr = currCal = currCal->calNext;
if (currCal->calState == CAL_WAITING) {
*isCalDone = AH_FALSE;
ar5416ResetMeasurement(ah, currCal);
}
}
}
/* Do NF cal only at longer intervals */
if (longcal) {
/* Do PA calibration if the chipset supports */
if (AH5416(ah)->ah_cal_pacal)
AH5416(ah)->ah_cal_pacal(ah, AH_FALSE);
/* Do open-loop temperature compensation if the chipset needs it */
if (ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))
AH5416(ah)->ah_olcTempCompensation(ah);
/*
* Get the value from the previous NF cal
* and update the history buffer.
*/
r = ar5416GetNf(ah, chan);
if (r == 0 || r == -1) {
/* NF calibration result isn't valid */
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: NF calibration"
" didn't finish; delaying CCA\n", __func__);
} else {
int ret;
/*
* NF calibration result is valid.
*
* Load the NF from history buffer of the current channel.
* NF is slow time-variant, so it is OK to use a
* historical value.
*/
ret = ar5416LoadNF(ah, AH_PRIVATE(ah)->ah_curchan);
/* start NF calibration, without updating BB NF register*/
ar5416StartNFCal(ah);
/*
* If we failed calibration then tell the driver
* we failed and it should do a full chip reset
*/
if (! ret)
return AH_FALSE;
}
}
return AH_TRUE;
}
/*
* Use HW data to do IQ Mismatch Calibration
*/
void
ar5416IQCalibration(struct ath_hal *ah, uint8_t numChains)
{
struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
int i;
for (i = 0; i < numChains; i++) {
uint32_t powerMeasI = cal->totalPowerMeasI(i);
uint32_t powerMeasQ = cal->totalPowerMeasQ(i);
uint32_t iqCorrMeas = cal->totalIqCorrMeas(i);
uint32_t qCoffDenom, iCoffDenom;
int iqCorrNeg;
HALDEBUG(ah, HAL_DEBUG_PERCAL,
"Start IQ Cal and Correction for Chain %d\n", i);
HALDEBUG(ah, HAL_DEBUG_PERCAL,
"Orignal: iq_corr_meas = 0x%08x\n", iqCorrMeas);
iqCorrNeg = 0;
/* iqCorrMeas is always negative. */
if (iqCorrMeas > 0x80000000) {
iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
iqCorrNeg = 1;
}
HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_i = 0x%08x\n",
powerMeasI);
HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_q = 0x%08x\n",
powerMeasQ);
HALDEBUG(ah, HAL_DEBUG_PERCAL, " iqCorrNeg is 0x%08x\n",
iqCorrNeg);
iCoffDenom = (powerMeasI/2 + powerMeasQ/2)/ 128;
qCoffDenom = powerMeasQ / 64;
/* Protect against divide-by-0 */
if (powerMeasQ != 0) {
/* IQ corr_meas is already negated if iqcorr_neg == 1 */
int32_t iCoff = iqCorrMeas/iCoffDenom;
int32_t qCoff = powerMeasI/qCoffDenom - 64;
HALDEBUG(ah, HAL_DEBUG_PERCAL, " iCoff = 0x%08x\n",
iCoff);
HALDEBUG(ah, HAL_DEBUG_PERCAL, " qCoff = 0x%08x\n",
qCoff);
/* Negate iCoff if iqCorrNeg == 0 */
iCoff = iCoff & 0x3f;
HALDEBUG(ah, HAL_DEBUG_PERCAL,
"New: iCoff = 0x%08x\n", iCoff);
if (iqCorrNeg == 0x0)
iCoff = 0x40 - iCoff;
if (qCoff > 15)
qCoff = 15;
else if (qCoff <= -16)
qCoff = -16;
HALDEBUG(ah, HAL_DEBUG_PERCAL,
" : iCoff = 0x%x qCoff = 0x%x\n", iCoff, qCoff);
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4_CHAIN(i),
AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff);
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4_CHAIN(i),
AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff);
HALDEBUG(ah, HAL_DEBUG_PERCAL,
"IQ Cal and Correction done for Chain %d\n", i);
}
}
OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
}
static HAL_BOOL
ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
static const uint32_t ar5416_cca_regs[] = {
AR_PHY_CCA,
AR_PHY_CH1_CCA,
AR_PHY_CH2_CCA,
AR_PHY_EXT_CCA,
AR_PHY_CH1_EXT_CCA,
AR_PHY_CH2_EXT_CCA
};
struct ar5212NfCalHist *h;
int i;
int32_t val;
uint8_t chainmask;
int16_t default_nf = ar5416GetDefaultNF(ah, chan);
/*
* Force NF calibration for all chains.
*/
if (AR_SREV_KITE(ah)) {
/* Kite has only one chain */
chainmask = 0x9;
} else if (AR_SREV_MERLIN(ah) || AR_SREV_KIWI(ah)) {
/* Merlin/Kiwi has only two chains */
chainmask = 0x1B;
} else {
chainmask = 0x3F;
}
/*
* Write filtered NF values into maxCCApwr register parameter
* so we can load below.
*/
h = AH5416(ah)->ah_cal.nfCalHist;
HALDEBUG(ah, HAL_DEBUG_NFCAL, "CCA: ");
for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
/* Don't write to EXT radio CCA registers unless in HT/40 mode */
/* XXX this check should really be cleaner! */
if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan))
continue;
if (chainmask & (1 << i)) {
int16_t nf_val;
if (h)
nf_val = h[i].privNF;
else
nf_val = default_nf;
val = OS_REG_READ(ah, ar5416_cca_regs[i]);
val &= 0xFFFFFE00;
val |= (((uint32_t) nf_val << 1) & 0x1ff);
HALDEBUG(ah, HAL_DEBUG_NFCAL, "[%d: %d]", i, nf_val);
OS_REG_WRITE(ah, ar5416_cca_regs[i], val);
}
}
HALDEBUG(ah, HAL_DEBUG_NFCAL, "\n");
/* Load software filtered NF value into baseband internal minCCApwr variable. */
OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
/* Wait for load to complete, should be fast, a few 10s of us. */
if (! ar5212WaitNFCalComplete(ah, 1000)) {
/*
* We timed out waiting for the noisefloor to load, probably due to an
* in-progress rx. Simply return here and allow the load plenty of time
* to complete before the next calibration interval. We need to avoid
* trying to load -50 (which happens below) while the previous load is
* still in progress as this can cause rx deafness. Instead by returning
* here, the baseband nf cal will just be capped by our present
* noisefloor until the next calibration timer.
*/
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "Timeout while waiting for "
"nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
return AH_FALSE;
}
/*
* Restore maxCCAPower register parameter again so that we're not capped
* by the median we just loaded. This will be initial (and max) value
* of next noise floor calibration the baseband does.
*/
for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
/* Don't write to EXT radio CCA registers unless in HT/40 mode */
/* XXX this check should really be cleaner! */
if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan))
continue;
if (chainmask & (1 << i)) {
val = OS_REG_READ(ah, ar5416_cca_regs[i]);
val &= 0xFFFFFE00;
val |= (((uint32_t)(-50) << 1) & 0x1ff);
OS_REG_WRITE(ah, ar5416_cca_regs[i], val);
}
}
return AH_TRUE;
}
static void
ar9287AniSetup(struct ath_hal *ah)
{
/*
* These are the parameters from the AR5416 ANI code;
* they likely need quite a bit of adjustment for the
* AR9287.
*/
static const struct ar5212AniParams aniparams = {
.maxNoiseImmunityLevel = 4, /* levels 0..4 */
.totalSizeDesired = { -55, -55, -55, -55, -62 },
.coarseHigh = { -14, -14, -14, -14, -12 },
.coarseLow = { -64, -64, -64, -64, -70 },
.firpwr = { -78, -78, -78, -78, -80 },
.maxSpurImmunityLevel = 7,
.cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 },
.maxFirstepLevel = 2, /* levels 0..2 */
.firstep = { 0, 4, 8 },
.ofdmTrigHigh = 500,
.ofdmTrigLow = 200,
.cckTrigHigh = 200,
.cckTrigLow = 100,
.rssiThrHigh = 40,
.rssiThrLow = 7,
.period = 100,
};
/* NB: disable ANI noise immmunity for reliable RIFS rx */
AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL;
/* NB: ANI is not enabled yet */
ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
}
/*
* Attach for an AR9287 part.
*/
static struct ath_hal *
ar9287Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
HAL_STATUS *status)
{
struct ath_hal_9287 *ahp9287;
struct ath_hal_5212 *ahp;
struct ath_hal *ah;
uint32_t val;
HAL_STATUS ecode;
HAL_BOOL rfStatus;
int8_t pwr_table_offset;
HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
__func__, sc, (void*) st, (void*) sh);
/* NB: memory is returned zero'd */
ahp9287 = ath_hal_malloc(sizeof (struct ath_hal_9287));
if (ahp9287 == AH_NULL) {
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
"%s: cannot allocate memory for state block\n", __func__);
*status = HAL_ENOMEM;
return AH_NULL;
}
ahp = AH5212(ahp9287);
ah = &ahp->ah_priv.h;
ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
if (eepromdata != AH_NULL) {
AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;
AH_PRIVATE(ah)->ah_eepromWrite = NULL;
ah->ah_eepromdata = eepromdata;
}
/* XXX override with 9280 specific state */
/* override 5416 methods for our needs */
AH5416(ah)->ah_initPLL = ar9280InitPLL;
ah->ah_setAntennaSwitch = ar9287SetAntennaSwitch;
ah->ah_configPCIE = ar9287ConfigPCIE;
ah->ah_disablePCIE = ar9287DisablePCIE;
AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal;
AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal;
AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal;
AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal;
/* Better performance without ADC Gain Calibration */
AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL;
AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
AH5416(ah)->ah_writeIni = ar9287WriteIni;
ah->ah_setTxPower = ar9287SetTransmitPower;
ah->ah_setBoardValues = ar9287SetBoardValues;
AH5416(ah)->ah_olcInit = ar9287olcInit;
AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation;
//AH5416(ah)->ah_setPowerCalTable = ar9287SetPowerCalTable;
AH5416(ah)->ah_cal_initcal = ar9287InitCalHardware;
AH5416(ah)->ah_cal_pacal = ar9287PACal;
/* XXX NF calibration */
/* XXX Ini override? (IFS vars - since the kiwi mac clock is faster?) */
/* XXX what else is kiwi-specific in the radio/calibration pathway? */
AH5416(ah)->ah_rx_chainmask = AR9287_DEFAULT_RXCHAINMASK;
AH5416(ah)->ah_tx_chainmask = AR9287_DEFAULT_TXCHAINMASK;
if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
/* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
__func__);
ecode = HAL_EIO;
goto bad;
}
if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
__func__);
ecode = HAL_EIO;
goto bad;
}
/* Read Revisions from Chips before taking out of reset */
val = OS_REG_READ(ah, AR_SREV);
HALDEBUG(ah, HAL_DEBUG_ATTACH,
"%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
__func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
/* NB: include chip type to differentiate from pre-Sowl versions */
AH_PRIVATE(ah)->ah_macVersion =
(val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
/* Don't support Kiwi < 1.2; those are pre-release chips */
if (! AR_SREV_KIWI_12_OR_LATER(ah)) {
ath_hal_printf(ah, "[ath]: Kiwi < 1.2 is not supported\n");
ecode = HAL_EIO;
goto bad;
}
/* setup common ini data; rf backends handle remainder */
HAL_INI_INIT(&ahp->ah_ini_modes, ar9287Modes_9287_1_1, 6);
HAL_INI_INIT(&ahp->ah_ini_common, ar9287Common_9287_1_1, 2);
/* If pcie_clock_req */
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 2);
/* XXX WoW ini values */
/* Else */
#if 0
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
ar9287PciePhy_clkreq_off_L1_9287_1_1, 2);
#endif
/* Initialise Japan arrays */
HAL_INI_INIT(&ahp9287->ah_ini_cckFirNormal,
ar9287Common_normal_cck_fir_coeff_9287_1_1, 2);
HAL_INI_INIT(&ahp9287->ah_ini_cckFirJapan2484,
ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 2);
ar5416AttachPCIE(ah);
ecode = ath_hal_9287EepromAttach(ah);
if (ecode != HAL_OK)
goto bad;
if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
ecode = HAL_EIO;
goto bad;
}
AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
if (!ar5212ChipTest(ah)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
__func__);
ecode = HAL_ESELFTEST;
goto bad;
}
/*
* Set correct Baseband to analog shift
* setting to access analog chips.
*/
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
/* Read Radio Chip Rev Extract */
AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
break;
default:
if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
AH_PRIVATE(ah)->ah_analog5GhzRev =
AR_RAD5133_SREV_MAJOR;
break;
}
#ifdef AH_DEBUG
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: 5G Radio Chip Rev 0x%02X is not supported by "
"this driver\n", __func__,
AH_PRIVATE(ah)->ah_analog5GhzRev);
ecode = HAL_ENOTSUPP;
goto bad;
#endif
}
rfStatus = ar9287RfAttach(ah, &ecode);
if (!rfStatus) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
__func__, ecode);
goto bad;
}
/*
* We only implement open-loop TX power control
* for the AR9287 in this codebase.
*/
if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
ath_hal_printf(ah, "[ath] AR9287 w/ closed-loop TX power control"
" isn't supported.\n");
ecode = HAL_ENOTSUPP;
goto bad;
}
/*
* Check whether the power table offset isn't the default.
* This can occur with eeprom minor V21 or greater on Merlin.
*/
(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset);
if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB)
ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n",
AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset);
/* setup rxgain table */
HAL_INI_INIT(&ahp9287->ah_ini_rxgain, ar9287Modes_rx_gain_9287_1_1, 6);
/* setup txgain table */
HAL_INI_INIT(&ahp9287->ah_ini_txgain, ar9287Modes_tx_gain_9287_1_1, 6);
/*
* Got everything we need now to setup the capabilities.
*/
if (!ar9287FillCapabilityInfo(ah)) {
ecode = HAL_EEREAD;
goto bad;
}
ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
if (ecode != HAL_OK) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error getting mac address from EEPROM\n", __func__);
goto bad;
}
/* XXX How about the serial number ? */
/* Read Reg Domain */
AH_PRIVATE(ah)->ah_currentRD =
ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
AH_PRIVATE(ah)->ah_currentRDext = AR9287_RDEXT_DEFAULT;
/*
* ah_miscMode is populated by ar5416FillCapabilityInfo()
* starting from griffin. Set here to make sure that
* AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
* placed into hardware.
*/
if (ahp->ah_miscMode != 0)
OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
ar9287AniSetup(ah); /* Anti Noise Immunity */
/* Setup noise floor min/max/nominal values */
AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_5GHZ;
AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_5GHZ;
AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9287_5GHZ;
ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
return ah;
bad:
if (ah != AH_NULL)
ah->ah_detach(ah);
if (status)
*status = ecode;
return AH_NULL;
}
static void
ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
{
if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
OS_DELAY(1000);
OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
/* Yes, Kiwi uses the Kite PCIe PHY WA */
OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
}
}
static void
ar9287DisablePCIE(struct ath_hal *ah)
{
/* XXX TODO */
}
static void
ar9287WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
u_int modesIndex, freqIndex;
int regWrites = 0;
/* Setup the indices for the next set of register array writes */
/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
freqIndex = 2;
if (IEEE80211_IS_CHAN_HT40(chan))
modesIndex = 3;
else if (IEEE80211_IS_CHAN_108G(chan))
modesIndex = 5;
else
modesIndex = 4;
} else {
freqIndex = 1;
if (IEEE80211_IS_CHAN_HT40(chan) ||
IEEE80211_IS_CHAN_TURBO(chan))
modesIndex = 2;
else
modesIndex = 1;
}
/* Set correct Baseband to analog shift setting to access analog chips. */
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, modesIndex, regWrites);
regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_rxgain, modesIndex, regWrites);
regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_txgain, modesIndex, regWrites);
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 1, regWrites);
}
static void
ar5212AniLowerImmunity(struct ath_hal *ah)
{
struct ath_hal_5212 *ahp = AH5212(ah);
struct ar5212AniState *aniState;
const struct ar5212AniParams *params;
HALASSERT(ANI_ENA(ah));
aniState = ahp->ah_curani;
params = aniState->params;
if (ANI_ENA_RSSI(ah)) {
int32_t rssi = BEACON_RSSI(ahp);
if (rssi > params->rssiThrHigh) {
/*
* Beacon signal is high, leave ofdm weak signal
* detection off or it may oscillate. Let it fall
* through.
*/
} else if (rssi > params->rssiThrLow) {
/*
* Beacon rssi in mid range, turn on ofdm weak signal
* detection or lower firstep level.
*/
if (aniState->ofdmWeakSigDetectOff) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d OWSD on\n", __func__, rssi);
ar5212AniControl(ah,
HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
AH_TRUE);
return;
}
if (aniState->firstepLevel > 0) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d lower ST %u\n", __func__, rssi,
aniState->firstepLevel-1);
ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel - 1);
return;
}
} else {
/*
* Beacon rssi is low, reduce firstep level.
*/
if (aniState->firstepLevel > 0) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d lower ST %u\n", __func__, rssi,
aniState->firstepLevel-1);
ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
aniState->firstepLevel - 1);
return;
}
}
}
/* then lower spur immunity level, down to zero */
if (aniState->spurImmunityLevel > 0) {
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: lower SI %u\n",
__func__, aniState->spurImmunityLevel-1);
ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
aniState->spurImmunityLevel - 1);
return;
}
/*
* if all else fails, lower noise immunity level down to a min value
* zero for now
*/
if (aniState->noiseImmunityLevel > 0) {
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: lower NI %u\n",
__func__, aniState->noiseImmunityLevel-1);
ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
aniState->noiseImmunityLevel - 1);
return;
}
}
/*
* Reads EEPROM header info from device structure and programs
* all rf registers
*
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
ar2413SetRfRegs(struct ath_hal *ah,
const struct ieee80211_channel *chan,
uint16_t modesIndex, uint16_t *rfXpdGain)
{
#define RF_BANK_SETUP(_priv, _ix, _col) do { \
int i; \
for (i = 0; i < N(ar5212Bank##_ix##_2413); i++) \
(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2413[i][_col];\
} while (0)
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
uint16_t ob2GHz = 0, db2GHz = 0;
struct ar2413State *priv = AR2413(ah);
int regWrites = 0;
HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
__func__, chan->ic_freq, chan->ic_flags, modesIndex);
HALASSERT(priv);
/* Setup rf parameters */
if (IEEE80211_IS_CHAN_B(chan)) {
ob2GHz = ee->ee_obFor24;
db2GHz = ee->ee_dbFor24;
} else {
ob2GHz = ee->ee_obFor24g;
db2GHz = ee->ee_dbFor24g;
}
/* Bank 1 Write */
RF_BANK_SETUP(priv, 1, 1);
/* Bank 2 Write */
RF_BANK_SETUP(priv, 2, modesIndex);
/* Bank 3 Write */
RF_BANK_SETUP(priv, 3, modesIndex);
/* Bank 6 Write */
RF_BANK_SETUP(priv, 6, modesIndex);
ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 168, 0);
ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 165, 0);
/* Bank 7 Setup */
RF_BANK_SETUP(priv, 7, modesIndex);
/* Write Analog registers */
HAL_INI_WRITE_BANK(ah, ar5212Bank1_2413, priv->Bank1Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank2_2413, priv->Bank2Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank3_2413, priv->Bank3Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank6_2413, priv->Bank6Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank7_2413, priv->Bank7Data, regWrites);
/* Now that we have reprogrammed rfgain value, clear the flag. */
ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
return AH_TRUE;
#undef RF_BANK_SETUP
}
/*
* Set all the beacon related bits on the h/w for stations
* i.e. initializes the corresponding h/w timers;
* also tells the h/w whether to anticipate PCF beacons
*/
void
ar5211SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
{
struct ath_hal_5211 *ahp = AH5211(ah);
HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__);
HALASSERT(bs->bs_intval != 0);
/* if the AP will do PCF */
if (bs->bs_cfpmaxduration != 0) {
/* tell the h/w that the associated AP is PCF capable */
OS_REG_WRITE(ah, AR_STA_ID1,
OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
/* set CFP_PERIOD(1.024ms) register */
OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
/* set CFP_DUR(1.024ms) register to max cfp duration */
OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
/* set TIMER2(128us) to anticipated time of next CFP */
OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
} else {
/* tell the h/w that the associated AP is not PCF capable */
OS_REG_WRITE(ah, AR_STA_ID1,
OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
}
/*
* Set TIMER0(1.024ms) to the anticipated time of the next beacon.
*/
OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
/*
* Start the beacon timers by setting the BEACON register
* to the beacon interval; also write the tim offset which
* we should know by now. The code, in ar5211WriteAssocid,
* also sets the tim offset once the AID is known which can
* be left as such for now.
*/
OS_REG_WRITE(ah, AR_BEACON,
(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
| SM(bs->bs_intval, AR_BEACON_PERIOD)
| SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
);
/*
* Configure the BMISS interrupt. Note that we
* assume the caller blocks interrupts while enabling
* the threshold.
*/
HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR));
ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
| SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);
OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
/*
* Set the sleep duration in 1/8 TU's.
*/
#define SLEEP_SLOP 3
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLDUR,
(bs->bs_sleepduration - SLEEP_SLOP) << 3);
#undef SLEEP_SLOP
}
/*
* Take the MHz channel value and set the Channel value
*
* ASSUMES: Writes enabled to analog bus
*/
static HAL_BOOL
ar2413SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
uint16_t freq = ath_hal_gethwchannel(ah, chan);
uint32_t channelSel = 0;
uint32_t bModeSynth = 0;
uint32_t aModeRefSel = 0;
uint32_t reg32 = 0;
OS_MARK(ah, AH_MARK_SETCHANNEL, freq);
if (freq < 4800) {
uint32_t txctl;
if (((freq - 2192) % 5) == 0) {
channelSel = ((freq - 672) * 2 - 3040)/10;
bModeSynth = 0;
} else if (((freq - 2224) % 5) == 0) {
channelSel = ((freq - 704) * 2 - 3040) / 10;
bModeSynth = 1;
} else {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u MHz\n",
__func__, freq);
return AH_FALSE;
}
channelSel = (channelSel << 2) & 0xff;
channelSel = ath_hal_reverseBits(channelSel, 8);
txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
if (freq == 2484) {
/* Enable channel spreading for channel 14 */
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
} else {
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
}
} else if (((freq % 5) == 2) && (freq <= 5435)) {
freq = freq - 2; /* Align to even 5MHz raster */
channelSel = ath_hal_reverseBits(
(uint32_t)(((freq - 4800)*10)/25 + 1), 8);
aModeRefSel = ath_hal_reverseBits(0, 2);
} else if ((freq % 20) == 0 && freq >= 5120) {
channelSel = ath_hal_reverseBits(
((freq - 4800) / 20 << 2), 8);
aModeRefSel = ath_hal_reverseBits(3, 2);
} else if ((freq % 10) == 0) {
channelSel = ath_hal_reverseBits(
((freq - 4800) / 10 << 1), 8);
aModeRefSel = ath_hal_reverseBits(2, 2);
} else if ((freq % 5) == 0) {
channelSel = ath_hal_reverseBits(
(freq - 4800) / 5, 8);
aModeRefSel = ath_hal_reverseBits(1, 2);
} else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
__func__, freq);
return AH_FALSE;
}
reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
(1 << 12) | 0x1;
OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
reg32 >>= 8;
OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);
AH_PRIVATE(ah)->ah_curchan = chan;
return AH_TRUE;
}
/*
* Control Adaptive Noise Immunity Parameters
*/
HAL_BOOL
ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
{
typedef int TABLE[];
struct ath_hal_5212 *ahp = AH5212(ah);
struct ar5212AniState *aniState = ahp->ah_curani;
const struct ar5212AniParams *params = aniState->params;
OS_MARK(ah, AH_MARK_ANI_CONTROL, cmd);
switch (cmd) {
case HAL_ANI_NOISE_IMMUNITY_LEVEL: {
u_int level = param;
if (level >= params->maxNoiseImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: immunity level out of range (%u > %u)\n",
__func__, level, params->maxNoiseImmunityLevel);
return AH_FALSE;
}
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
AR_PHY_DESIRED_SZ_TOT_DES, params->totalSizeDesired[level]);
OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
AR_PHY_AGC_CTL1_COARSE_LOW, params->coarseLow[level]);
OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
AR_PHY_AGC_CTL1_COARSE_HIGH, params->coarseHigh[level]);
OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
AR_PHY_FIND_SIG_FIRPWR, params->firpwr[level]);
if (level > aniState->noiseImmunityLevel)
ahp->ah_stats.ast_ani_niup++;
else if (level < aniState->noiseImmunityLevel)
ahp->ah_stats.ast_ani_nidown++;
aniState->noiseImmunityLevel = level;
break;
}
case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: {
static const TABLE m1ThreshLow = { 127, 50 };
static const TABLE m2ThreshLow = { 127, 40 };
static const TABLE m1Thresh = { 127, 0x4d };
static const TABLE m2Thresh = { 127, 0x40 };
static const TABLE m2CountThr = { 31, 16 };
static const TABLE m2CountThrLow = { 63, 48 };
u_int on = param ? 1 : 0;
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1ThreshLow[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2ThreshLow[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
if (on) {
OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
} else {
OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
}
if (on)
ahp->ah_stats.ast_ani_ofdmon++;
else
ahp->ah_stats.ast_ani_ofdmoff++;
aniState->ofdmWeakSigDetectOff = !on;
break;
}
case HAL_ANI_CCK_WEAK_SIGNAL_THR: {
static const TABLE weakSigThrCck = { 8, 6 };
u_int high = param ? 1 : 0;
OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, weakSigThrCck[high]);
if (high)
ahp->ah_stats.ast_ani_cckhigh++;
else
ahp->ah_stats.ast_ani_ccklow++;
aniState->cckWeakSigThreshold = high;
break;
}
case HAL_ANI_FIRSTEP_LEVEL: {
u_int level = param;
if (level >= params->maxFirstepLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: firstep level out of range (%u > %u)\n",
__func__, level, params->maxFirstepLevel);
return AH_FALSE;
}
OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
AR_PHY_FIND_SIG_FIRSTEP, params->firstep[level]);
if (level > aniState->firstepLevel)
ahp->ah_stats.ast_ani_stepup++;
else if (level < aniState->firstepLevel)
ahp->ah_stats.ast_ani_stepdown++;
aniState->firstepLevel = level;
break;
}
case HAL_ANI_SPUR_IMMUNITY_LEVEL: {
u_int level = param;
if (level >= params->maxSpurImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: spur immunity level out of range (%u > %u)\n",
__func__, level, params->maxSpurImmunityLevel);
return AH_FALSE;
}
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
AR_PHY_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]);
if (level > aniState->spurImmunityLevel)
ahp->ah_stats.ast_ani_spurup++;
else if (level < aniState->spurImmunityLevel)
ahp->ah_stats.ast_ani_spurdown++;
aniState->spurImmunityLevel = level;
break;
}
case HAL_ANI_PRESENT:
break;
case HAL_ANI_MODE:
if (param == 0) {
ahp->ah_procPhyErr &= ~HAL_ANI_ENA;
/* Turn off HW counters if we have them */
ar5416AniDetach(ah);
ar5212SetRxFilter(ah,
ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
} else { /* normal/auto mode */
/* don't mess with state if already enabled */
if (ahp->ah_procPhyErr & HAL_ANI_ENA)
break;
ar5212SetRxFilter(ah,
ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
/* Enable MIB Counters */
enableAniMIBCounters(ah, ahp->ah_curani != AH_NULL ?
ahp->ah_curani->params: &ahp->ah_aniParams24 /*XXX*/);
ahp->ah_procPhyErr |= HAL_ANI_ENA;
}
break;
#ifdef AH_PRIVATE_DIAG
case HAL_ANI_PHYERR_RESET:
ahp->ah_stats.ast_ani_ofdmerrs = 0;
ahp->ah_stats.ast_ani_cckerrs = 0;
break;
#endif /* AH_PRIVATE_DIAG */
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid cmd %u\n",
__func__, cmd);
return AH_FALSE;
}
return AH_TRUE;
}
/*
* Control Adaptive Noise Immunity Parameters
*/
HAL_BOOL
ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
{
#define N(a) (sizeof(a)/sizeof(a[0]))
typedef int TABLE[];
struct ath_hal_5212 *ahp = AH5212(ah);
struct ar5212AniState *aniState = ahp->ah_curani;
switch (cmd) {
case HAL_ANI_NOISE_IMMUNITY_LEVEL: {
u_int level = param;
if (level >= N(ahp->ah_totalSizeDesired)) {
HALDEBUG(ah, "%s: level out of range (%u > %u)\n",
__func__, level, N(ahp->ah_totalSizeDesired));
return AH_FALSE;
}
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
AR_PHY_DESIRED_SZ_TOT_DES, ahp->ah_totalSizeDesired[level]);
OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
AR_PHY_AGC_CTL1_COARSE_LOW, ahp->ah_coarseLow[level]);
OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
AR_PHY_AGC_CTL1_COARSE_HIGH, ahp->ah_coarseHigh[level]);
OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
AR_PHY_FIND_SIG_FIRPWR, ahp->ah_firpwr[level]);
if (level > aniState->noiseImmunityLevel)
ahp->ah_stats.ast_ani_niup++;
else if (level < aniState->noiseImmunityLevel)
ahp->ah_stats.ast_ani_nidown++;
aniState->noiseImmunityLevel = level;
break;
}
case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: {
const TABLE m1ThreshLow = { 127, 50 };
const TABLE m2ThreshLow = { 127, 40 };
const TABLE m1Thresh = { 127, 0x4d };
const TABLE m2Thresh = { 127, 0x40 };
const TABLE m2CountThr = { 31, 16 };
const TABLE m2CountThrLow = { 63, 48 };
u_int on = param ? 1 : 0;
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1ThreshLow[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2ThreshLow[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]);
if (on) {
OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
} else {
OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
}
if (!on != aniState->ofdmWeakSigDetectOff) {
if (on)
ahp->ah_stats.ast_ani_ofdmon++;
else
ahp->ah_stats.ast_ani_ofdmoff++;
aniState->ofdmWeakSigDetectOff = !on;
}
break;
}
case HAL_ANI_CCK_WEAK_SIGNAL_THR: {
const TABLE weakSigThrCck = { 8, 6 };
u_int high = param ? 1 : 0;
OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
weakSigThrCck[high]);
if (high != aniState->cckWeakSigThreshold) {
if (high)
ahp->ah_stats.ast_ani_cckhigh++;
else
ahp->ah_stats.ast_ani_ccklow++;
aniState->cckWeakSigThreshold = high;
}
break;
}
case HAL_ANI_FIRSTEP_LEVEL: {
const TABLE firstep = { 0, 4, 8 };
u_int level = param;
if (level >= N(firstep)) {
HALDEBUG(ah, "%s: level out of range (%u > %u)\n",
__func__, level, N(firstep));
return AH_FALSE;
}
OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
AR_PHY_FIND_SIG_FIRSTEP, firstep[level]);
if (level > aniState->firstepLevel)
ahp->ah_stats.ast_ani_stepup++;
else if (level < aniState->firstepLevel)
ahp->ah_stats.ast_ani_stepdown++;
aniState->firstepLevel = level;
break;
}
case HAL_ANI_SPUR_IMMUNITY_LEVEL: {
const TABLE cycpwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 };
u_int level = param;
if (level >= N(cycpwrThr1)) {
HALDEBUG(ah, "%s: level out of range (%u > %u)\n",
__func__, level, N(cycpwrThr1));
return AH_FALSE;
}
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
AR_PHY_TIMING5_CYCPWR_THR1, cycpwrThr1[level]);
if (level > aniState->spurImmunityLevel)
ahp->ah_stats.ast_ani_spurup++;
else if (level < aniState->spurImmunityLevel)
ahp->ah_stats.ast_ani_spurdown++;
aniState->spurImmunityLevel = level;
break;
}
case HAL_ANI_PRESENT:
break;
#ifdef AH_PRIVATE_DIAG
case HAL_ANI_MODE:
if (param == 0) {
ahp->ah_procPhyErr &= ~HAL_PROCESS_ANI;
/* Turn off HW counters if we have them */
ar5212AniDetach(ah);
ar5212SetRxFilter(ah,
ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
} else { /* normal/auto mode */
ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
if (ahp->ah_hasHwPhyCounters) {
ar5212SetRxFilter(ah,
ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
} else {
ar5212SetRxFilter(ah,
ar5212GetRxFilter(ah) | HAL_RX_FILTER_PHYERR);
}
}
break;
case HAL_ANI_PHYERR_RESET:
ahp->ah_stats.ast_ani_ofdmerrs = 0;
ahp->ah_stats.ast_ani_cckerrs = 0;
break;
#endif /* AH_PRIVATE_DIAG */
default:
HALDEBUG(ah, "%s: invalid cmd %u\n", __func__, cmd);
return AH_FALSE;
}
return AH_TRUE;
#undef N
}
/*
* Process a MIB interrupt. We may potentially be invoked because
* any of the MIB counters overflow/trigger so don't assume we're
* here because a PHY error counter triggered.
*/
void
ar5416ProcessMibIntr(struct ath_hal *ah, const HAL_NODE_STATS *stats)
{
struct ath_hal_5212 *ahp = AH5212(ah);
uint32_t phyCnt1, phyCnt2;
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: mibc 0x%x phyCnt1 0x%x phyCnt2 0x%x "
"filtofdm 0x%x filtcck 0x%x\n",
__func__, OS_REG_READ(ah, AR_MIBC),
OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),
OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));
/*
* First order of business is to clear whatever caused
* the interrupt so we don't keep getting interrupted.
* We have the usual mib counters that are reset-on-read
* and the additional counters that appeared starting in
* Hainan. We collect the mib counters and explicitly
* zero additional counters we are not using. Anything
* else is reset only if it caused the interrupt.
*/
/* NB: these are not reset-on-read */
phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);
phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);
/* not used, always reset them in case they are the cause */
OS_REG_WRITE(ah, AR_FILTOFDM, 0);
OS_REG_WRITE(ah, AR_FILTCCK, 0);
if ((OS_REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING) == 0)
OS_REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
/* Clear the mib counters and save them in the stats */
ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
ahp->ah_stats.ast_nodestats = *stats;
/*
* Check for an ani stat hitting the trigger threshold.
* When this happens we get a MIB interrupt and the top
* 2 bits of the counter register will be 0b11, hence
* the mask check of phyCnt?.
*/
if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
struct ar5212AniState *aniState = ahp->ah_curani;
const struct ar5212AniParams *params = aniState->params;
uint32_t ofdmPhyErrCnt, cckPhyErrCnt;
ofdmPhyErrCnt = phyCnt1 - params->ofdmPhyErrBase;
ahp->ah_stats.ast_ani_ofdmerrs +=
ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
cckPhyErrCnt = phyCnt2 - params->cckPhyErrBase;
ahp->ah_stats.ast_ani_cckerrs +=
cckPhyErrCnt - aniState->cckPhyErrCount;
aniState->cckPhyErrCount = cckPhyErrCnt;
/*
* NB: figure out which counter triggered. If both
* trigger we'll only deal with one as the processing
* clobbers the error counter so the trigger threshold
* check will never be true.
*/
if (aniState->ofdmPhyErrCount > params->ofdmTrigHigh)
ar5416AniOfdmErrTrigger(ah);
if (aniState->cckPhyErrCount > params->cckTrigHigh)
ar5416AniCckErrTrigger(ah);
/* NB: always restart to insure the h/w counters are reset */
ar5416AniRestart(ah, aniState);
}
}
/*
* Restore the ANI parameters in the HAL and reset the statistics.
* This routine should be called for every hardware reset and for
* every channel change. NOTE: This must be called for every channel
* change for ah_curani to be set correctly.
*/
void
ar5212AniReset(struct ath_hal *ah)
{
struct ath_hal_5212 *ahp = AH5212(ah);
struct ar5212AniState *aniState;
HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
int index;
HALASSERT(chan != AH_NULL);
index = ar5212GetAniChannelIndex(ah, chan);
aniState = &ahp->ah_ani[index];
ahp->ah_curani = aniState;
/*
* ANI is enabled but we're not operating in station
* mode. Reset all parameters. This can happen, for
* example, when starting up AP operation.
*/
if (DO_ANI(ah) && AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) {
HALDEBUG(ah,"%s: Reset ANI state opmode %u\n",
__func__, AH_PRIVATE(ah)->ah_opmode);
ahp->ah_stats.ast_ani_reset++;
ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
ar5212AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
!HAL_ANI_USE_OFDM_WEAK_SIG);
ar5212AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
HAL_ANI_CCK_WEAK_SIG_THR);
/* NB: enable phy frames so the driver gets stats */
ar5212SetRxFilter(ah,
ar5212GetRxFilter(ah) | HAL_RX_FILTER_PHYERR);
ar5212AniRestart(ah);
return;
}
if (aniState->noiseImmunityLevel != 0)
ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
aniState->noiseImmunityLevel);
if (aniState->spurImmunityLevel != 0)
ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
aniState->spurImmunityLevel);
if (aniState->ofdmWeakSigDetectOff)
ar5212AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
!aniState->ofdmWeakSigDetectOff);
if (aniState->cckWeakSigThreshold)
ar5212AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
aniState->cckWeakSigThreshold);
if (aniState->firstepLevel != 0)
ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, aniState->firstepLevel);
if (ahp->ah_hasHwPhyCounters) {
ar5212SetRxFilter(ah,
ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
ar5212AniRestart(ah);
OS_REG_WRITE(ah, AR_PHYCNTMASK1, AR_PHY_ERR_OFDM_TIMING);
OS_REG_WRITE(ah, AR_PHYCNTMASK2, AR_PHY_ERR_CCK_TIMING);
} else {
ar5212AniRestart(ah);
ar5212SetRxFilter(ah, ar5212GetRxFilter(ah) | HAL_RX_FILTER_PHYERR);
}
}
/*
* Uses the data points read from EEPROM to reconstruct the pdadc power table
* Called by ar2316SetPowerTable()
*/
static int
ar2316getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
const RAW_DATA_STRUCT_2316 *pRawDataset,
uint16_t pdGainOverlap_t2,
int16_t *pMinCalPower, uint16_t pPdGainBoundaries[],
uint16_t pPdGainValues[], uint16_t pPDADCValues[])
{
struct ar2316State *priv = AR2316(ah);
#define VpdTable_L priv->vpdTable_L
#define VpdTable_R priv->vpdTable_R
#define VpdTable_I priv->vpdTable_I
uint32_t ii, jj, kk;
int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
uint32_t idxL, idxR;
uint32_t numPdGainsUsed = 0;
/*
* If desired to support -ve power levels in future, just
* change pwr_I_0 to signed 5-bits.
*/
int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
/* to accommodate -ve power levels later on. */
int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
/* to accommodate -ve power levels later on */
uint16_t numVpd = 0;
uint16_t Vpd_step;
int16_t tmpVal ;
uint32_t sizeCurrVpdTable, maxIndex, tgtIndex;
/* Get upper lower index */
GetLowerUpperIndex(channel, pRawDataset->pChannels,
pRawDataset->numChannels, &(idxL), &(idxR));
for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
/* work backwards 'cause highest pdGain for lowest power */
numVpd = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].numVpd;
if (numVpd > 0) {
pPdGainValues[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pd_gain;
Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0];
if (Pmin_t2[numPdGainsUsed] >pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]) {
Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0];
}
Pmin_t2[numPdGainsUsed] = (int16_t)
(Pmin_t2[numPdGainsUsed] / 2);
Pmax_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[numVpd-1];
if (Pmax_t2[numPdGainsUsed] > pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1])
Pmax_t2[numPdGainsUsed] =
pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1];
Pmax_t2[numPdGainsUsed] = (int16_t)(Pmax_t2[numPdGainsUsed] / 2);
ar2316FillVpdTable(
numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed],
&(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0]),
&(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_L
);
ar2316FillVpdTable(
numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed],
&(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]),
&(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_R
);
for (kk = 0; kk < (uint16_t)(Pmax_t2[numPdGainsUsed] - Pmin_t2[numPdGainsUsed]); kk++) {
VpdTable_I[numPdGainsUsed][kk] =
interpolate_signed(
channel, pRawDataset->pChannels[idxL], pRawDataset->pChannels[idxR],
(int16_t)VpdTable_L[numPdGainsUsed][kk], (int16_t)VpdTable_R[numPdGainsUsed][kk]);
}
/* fill VpdTable_I for this pdGain */
numPdGainsUsed++;
}
/* if this pdGain is used */
}
*pMinCalPower = Pmin_t2[0];
kk = 0; /* index for the final table */
for (ii = 0; ii < numPdGainsUsed; ii++) {
if (ii == (numPdGainsUsed - 1))
pPdGainBoundaries[ii] = Pmax_t2[ii] +
PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB;
else
pPdGainBoundaries[ii] = (uint16_t)
((Pmax_t2[ii] + Pmin_t2[ii+1]) / 2 );
if (pPdGainBoundaries[ii] > 63) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: clamp pPdGainBoundaries[%d] %d\n",
__func__, ii, pPdGainBoundaries[ii]);/*XXX*/
pPdGainBoundaries[ii] = 63;
}
/* Find starting index for this pdGain */
if (ii == 0)
ss = 0; /* for the first pdGain, start from index 0 */
else
ss = (pPdGainBoundaries[ii-1] - Pmin_t2[ii]) -
pdGainOverlap_t2;
Vpd_step = (uint16_t)(VpdTable_I[ii][1] - VpdTable_I[ii][0]);
Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);
/*
*-ve ss indicates need to extrapolate data below for this pdGain
*/
while (ss < 0) {
tmpVal = (int16_t)(VpdTable_I[ii][0] + ss*Vpd_step);
pPDADCValues[kk++] = (uint16_t)((tmpVal < 0) ? 0 : tmpVal);
ss++;
}
sizeCurrVpdTable = Pmax_t2[ii] - Pmin_t2[ii];
tgtIndex = pPdGainBoundaries[ii] + pdGainOverlap_t2 - Pmin_t2[ii];
maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
while (ss < (int16_t)maxIndex)
pPDADCValues[kk++] = VpdTable_I[ii][ss++];
Vpd_step = (uint16_t)(VpdTable_I[ii][sizeCurrVpdTable-1] -
VpdTable_I[ii][sizeCurrVpdTable-2]);
Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);
/*
* for last gain, pdGainBoundary == Pmax_t2, so will
* have to extrapolate
*/
if (tgtIndex > maxIndex) { /* need to extrapolate above */
while(ss < (int16_t)tgtIndex) {
tmpVal = (uint16_t)
(VpdTable_I[ii][sizeCurrVpdTable-1] +
(ss-maxIndex)*Vpd_step);
pPDADCValues[kk++] = (tmpVal > 127) ?
127 : tmpVal;
ss++;
}
} /* extrapolated above */
} /* for all pdGainUsed */
while (ii < MAX_NUM_PDGAINS_PER_CHANNEL) {
pPdGainBoundaries[ii] = pPdGainBoundaries[ii-1];
ii++;
}
while (kk < 128) {
pPDADCValues[kk] = pPDADCValues[kk-1];
kk++;
}
return numPdGainsUsed;
#undef VpdTable_L
#undef VpdTable_R
#undef VpdTable_I
}
HAL_BOOL
ar5416InitCal(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
HAL_CHANNEL_INTERNAL *ichan;
ichan = ath_hal_checkchannel(ah, chan);
HALASSERT(ichan != AH_NULL);
/* Do initial chipset-specific calibration */
if (! AH5416(ah)->ah_cal_initcal(ah, chan)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: initial chipset calibration did "
"not complete in time; noisy environment?\n", __func__);
return AH_FALSE;
}
/* If there's PA Cal, do it */
if (AH5416(ah)->ah_cal_pacal)
AH5416(ah)->ah_cal_pacal(ah, AH_TRUE);
/*
* Do NF calibration after DC offset and other CALs.
* Per system engineers, noise floor value can sometimes be 20 dB
* higher than normal value if DC offset and noise floor cal are
* triggered at the same time.
*/
OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
/*
* This may take a while to run; make sure subsequent
* calibration routines check that this has completed
* before reading the value and triggering a subsequent
* calibration.
*/
/* Initialize list pointers */
cal->cal_list = cal->cal_last = cal->cal_curr = AH_NULL;
/*
* Enable IQ, ADC Gain, ADC DC Offset Cals
*/
if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah)) {
/* Setup all non-periodic, init time only calibrations */
/* XXX: Init DC Offset not working yet */
#if 0
if (ar5416IsCalSupp(ah, chan, ADC_DC_INIT_CAL)) {
INIT_CAL(&cal->adcDcCalInitData);
INSERT_CAL(cal, &cal->adcDcCalInitData);
}
/* Initialize current pointer to first element in list */
cal->cal_curr = cal->cal_list;
if (cal->ah_cal_curr != AH_NULL && !ar5416RunInitCals(ah, 0))
return AH_FALSE;
#endif
}
/* If Cals are supported, add them to list via INIT/INSERT_CAL */
if (ar5416IsCalSupp(ah, chan, ADC_GAIN_CAL)) {
INIT_CAL(&cal->adcGainCalData);
INSERT_CAL(cal, &cal->adcGainCalData);
HALDEBUG(ah, HAL_DEBUG_PERCAL,
"%s: enable ADC Gain Calibration.\n", __func__);
}
if (ar5416IsCalSupp(ah, chan, ADC_DC_CAL)) {
INIT_CAL(&cal->adcDcCalData);
INSERT_CAL(cal, &cal->adcDcCalData);
HALDEBUG(ah, HAL_DEBUG_PERCAL,
"%s: enable ADC DC Calibration.\n", __func__);
}
if (ar5416IsCalSupp(ah, chan, IQ_MISMATCH_CAL)) {
INIT_CAL(&cal->iqCalData);
INSERT_CAL(cal, &cal->iqCalData);
HALDEBUG(ah, HAL_DEBUG_PERCAL,
"%s: enable IQ Calibration.\n", __func__);
}
/* Initialize current pointer to first element in list */
cal->cal_curr = cal->cal_list;
/* Kick off measurements for the first cal */
if (cal->cal_curr != AH_NULL)
ar5416ResetMeasurement(ah, cal->cal_curr);
/* Mark all calibrations on this channel as being invalid */
ichan->calValid = 0;
return AH_TRUE;
#undef MAX_CAL_CHECK
}
/*
* Take the MHz channel value and set the Channel value
*
* ASSUMES: Writes enabled to analog bus
*/
static HAL_BOOL
ar2316SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
{
uint32_t channelSel = 0;
uint32_t bModeSynth = 0;
uint32_t aModeRefSel = 0;
uint32_t reg32 = 0;
OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
if (chan->channel < 4800) {
uint32_t txctl;
if (((chan->channel - 2192) % 5) == 0) {
channelSel = ((chan->channel - 672) * 2 - 3040)/10;
bModeSynth = 0;
} else if (((chan->channel - 2224) % 5) == 0) {
channelSel = ((chan->channel - 704) * 2 - 3040) / 10;
bModeSynth = 1;
} else {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: invalid channel %u MHz\n",
__func__, chan->channel);
return AH_FALSE;
}
channelSel = (channelSel << 2) & 0xff;
channelSel = ath_hal_reverseBits(channelSel, 8);
txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
if (chan->channel == 2484) {
/* Enable channel spreading for channel 14 */
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
} else {
OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
}
} else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
channelSel = ath_hal_reverseBits(
((chan->channel - 4800) / 20 << 2), 8);
aModeRefSel = ath_hal_reverseBits(3, 2);
} else if ((chan->channel % 10) == 0) {
channelSel = ath_hal_reverseBits(
((chan->channel - 4800) / 10 << 1), 8);
aModeRefSel = ath_hal_reverseBits(2, 2);
} else if ((chan->channel % 5) == 0) {
channelSel = ath_hal_reverseBits(
(chan->channel - 4800) / 5, 8);
aModeRefSel = ath_hal_reverseBits(1, 2);
} else {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
__func__, chan->channel);
return AH_FALSE;
}
reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
(1 << 12) | 0x1;
OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
reg32 >>= 8;
OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);
AH_PRIVATE(ah)->ah_curchan = chan;
return AH_TRUE;
}
/*
* Do periodic processing. This routine is called from a timer
*/
void
ar9300_ani_ar_poll(struct ath_hal *ah, const HAL_NODE_STATS *stats,
const struct ieee80211_channel *chan, HAL_ANISTATS *ani_stats)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state;
int32_t listen_time;
u_int32_t ofdm_phy_err_rate, cck_phy_err_rate;
u_int32_t ofdm_phy_err_cnt, cck_phy_err_cnt;
HAL_BOOL old_phy_noise_spur;
ani_state = ahp->ah_curani;
ahp->ah_stats.ast_nodestats = *stats; /* XXX optimize? */
if (ani_state == NULL) {
/* should not happen */
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
"%s: can't poll - no ANI not initialized for this channel\n",
__func__);
return;
}
/*
* ar9300_ani_ar_poll is never called while scanning but we may have been
* scanning and now just restarted polling. In this case we need to
* restore historical values.
*/
if (ani_state->must_restore) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: must restore - calling ar9300_ani_restart\n", __func__);
ar9300_ani_reset(ah, AH_FALSE);
return;
}
listen_time = ar9300_ani_get_listen_time(ah, ani_stats);
if (listen_time <= 0) {
ahp->ah_stats.ast_ani_lneg++;
/* restart ANI period if listen_time is invalid */
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: listen_time=%d - calling ar9300_ani_restart\n",
__func__, listen_time);
ar9300_ani_restart(ah);
return;
}
/* XXX beware of overflow? */
ani_state->listen_time += listen_time;
/* Clear the mib counters and save them in the stats */
ar9300_update_mib_mac_stats(ah);
/* NB: these are not reset-on-read */
ofdm_phy_err_cnt = OS_REG_READ(ah, AR_PHY_ERR_1);
cck_phy_err_cnt = OS_REG_READ(ah, AR_PHY_ERR_2);
/* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
ahp->ah_stats.ast_ani_ofdmerrs +=
ofdm_phy_err_cnt - ani_state->ofdm_phy_err_count;
ani_state->ofdm_phy_err_count = ofdm_phy_err_cnt;
ahp->ah_stats.ast_ani_cckerrs +=
cck_phy_err_cnt - ani_state->cck_phy_err_count;
ani_state->cck_phy_err_count = cck_phy_err_cnt;
#if HAL_ANI_DEBUG
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: Errors: OFDM=0x%08x-0x0=%d CCK=0x%08x-0x0=%d\n",
__func__, ofdm_phy_err_cnt, ofdm_phy_err_cnt,
cck_phy_err_cnt, cck_phy_err_cnt);
#endif
/*
* If ani is not enabled, return after we've collected
* statistics
*/
if (!DO_ANI(ah)) {
return;
}
ofdm_phy_err_rate =
ani_state->ofdm_phy_err_count * 1000 / ani_state->listen_time;
cck_phy_err_rate =
ani_state->cck_phy_err_count * 1000 / ani_state->listen_time;
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: listen_time=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
__func__, listen_time,
ani_state->ofdm_noise_immunity_level, ofdm_phy_err_rate,
ani_state->cck_noise_immunity_level, cck_phy_err_rate,
ani_state->ofdms_turn);
if (ani_state->listen_time >= HAL_NOISE_DETECT_PERIOD) {
old_phy_noise_spur = ani_state->phy_noise_spur;
if (ofdm_phy_err_rate <= ani_state->ofdm_trig_low &&
cck_phy_err_rate <= ani_state->cck_trig_low) {
if (ani_state->listen_time >= HAL_NOISE_RECOVER_PERIOD) {
ani_state->phy_noise_spur = 0;
}
} else {
ani_state->phy_noise_spur = 1;
}
if (old_phy_noise_spur != ani_state->phy_noise_spur) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: enviroment change from %d to %d\n",
__func__, old_phy_noise_spur, ani_state->phy_noise_spur);
}
}
if (ani_state->listen_time > 5 * ahp->ah_ani_period) {
/*
* Check to see if need to lower immunity if
* 5 ani_periods have passed
*/
if (ofdm_phy_err_rate <= ani_state->ofdm_trig_low &&
cck_phy_err_rate <= ani_state->cck_trig_low)
{
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: 1. listen_time=%d OFDM:%d errs=%d/s(<%d) "
"CCK:%d errs=%d/s(<%d) -> ar9300_ani_lower_immunity\n",
__func__, ani_state->listen_time,
ani_state->ofdm_noise_immunity_level, ofdm_phy_err_rate,
ani_state->ofdm_trig_low, ani_state->cck_noise_immunity_level,
cck_phy_err_rate, ani_state->cck_trig_low);
ar9300_ani_lower_immunity(ah);
ani_state->ofdms_turn = !ani_state->ofdms_turn;
}
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: 1 listen_time=%d ofdm=%d/s cck=%d/s - "
"calling ar9300_ani_restart\n",
__func__, ani_state->listen_time,
ofdm_phy_err_rate, cck_phy_err_rate);
ar9300_ani_restart(ah);
} else if (ani_state->listen_time > ahp->ah_ani_period) {
/* check to see if need to raise immunity */
if (ofdm_phy_err_rate > ani_state->ofdm_trig_high &&
(cck_phy_err_rate <= ani_state->cck_trig_high ||
ani_state->ofdms_turn))
{
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: 2 listen_time=%d OFDM:%d errs=%d/s(>%d) -> "
"ar9300_ani_ofdm_err_trigger\n",
__func__, ani_state->listen_time,
ani_state->ofdm_noise_immunity_level, ofdm_phy_err_rate,
ani_state->ofdm_trig_high);
ar9300_ani_ofdm_err_trigger(ah);
ar9300_ani_restart(ah);
ani_state->ofdms_turn = AH_FALSE;
} else if (cck_phy_err_rate > ani_state->cck_trig_high) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: 3 listen_time=%d CCK:%d errs=%d/s(>%d) -> "
"ar9300_ani_cck_err_trigger\n",
__func__, ani_state->listen_time,
ani_state->cck_noise_immunity_level, cck_phy_err_rate,
ani_state->cck_trig_high);
ar9300_ani_cck_err_trigger(ah);
ar9300_ani_restart(ah);
ani_state->ofdms_turn = AH_TRUE;
}
}
}
