static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
{
va_list ap;
va_start(ap, __func);
ret = chan->baud_rate;
chan->baud_rate = va_arg(ap, cyg_int32);
init_serial_channel(chan);
va_end(ap);
}
break;
case __COMMCTL_IRQ_ENABLE:
HAL_INTERRUPT_SET_LEVEL(chan->imb3_vector, chan->level);
HAL_INTERRUPT_UNMASK(chan->imb3_vector);
HAL_INTERRUPT_UNMASK(chan->siu_vector);
irq_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->imb3_vector);
HAL_INTERRUPT_MASK(chan->siu_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->siu_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
// Disable interrupts.
HAL_INTERRUPT_MASK(channels[0].isr_vector);
#if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1)
HAL_INTERRUPT_MASK(channels[1].isr_vector);
#endif
// Init channels
init_serial_channel(&channels[0]);
#if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1)
init_serial_channel(&channels[1]);
#endif
// Setup procs in the vector table
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
#if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1)
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
#endif
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
void
init_ser(void)
{
cyg_uint8* base = (cyg_uint8*)E7T_UART1_BASE;
// 8-1-no parity.
HAL_WRITE_UINT32(base+E7T_UART_LCON,
E7T_UART_LCON_8_DBITS|E7T_UART_LCON_1_SBITS|E7T_UART_LCON_NO_PARITY);
// Mask interrupts.
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_UART0_RX);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_UART0_TX);
HAL_WRITE_UINT32(base+E7T_UART_BRDIV, SIO_BRDDIV);
}
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
// CYGACC_CALL_VV1(__call_if_set_console_comm_t*, CYGNUM_CALL_IF_SET_CONSOLE_COMM, -1)
//__call_VV1(CYGNUM_CALL_IF_SET_CONSOLE_COMM, __call_if_set_console_comm_t, int, int)
// Disable interrupts.
HAL_INTERRUPT_MASK(smdk_ser_channels[0].isr_vector);
HAL_INTERRUPT_MASK(smdk_ser_channels[1].isr_vector);
//Unmask UART0/1 RX interrupt
HAL_WRITE_UINT32(INTSUBMSK, __READ_UINT32(INTSUBMSK) & ~(BIT_SUB_RXD0|BIT_SUB_RXD1));
// Init channels
cyg_hal_plf_serial_init_channel(&smdk_ser_channels[0]);
cyg_hal_plf_serial_init_channel(&smdk_ser_channels[1]);
// Setup procs in the vector table
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &smdk_ser_channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &smdk_ser_channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
externC hal_mpc5xx_arbitration_data *
hal_mpc5xx_remove_arbitration_isr(cyg_uint32 apriority)
{
hal_mpc5xx_arbitration_data * result = 0;
// Find the SIU vector from the priority
CYG_ADDRWORD vector = 2*(1 + apriority);
if(vector < CYGNUM_HAL_INTERRUPT_SIU_LVL7)
{
result = (hal_mpc5xx_arbitration_data *)(hal_interrupt_objects[vector]);
HAL_INTERRUPT_DETACH(vector, hal_interrupt_handlers[vector]);
}
else
{
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
// Prevent anything from coming through while manipulating the list
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
result = mpc5xx_remove(imb3_data_head, apriority);
// If something was removed, update the list.
if(result) imb3_data_head = result->reserved;
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#else
result = (hal_mpc5xx_arbitration_data *)(hal_interrupt_objects[CYGNUM_HAL_INTERRUPT_SIU_LVL7]);
HAL_INTERRUPT_DETACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, hal_interrupt_handlers[CYGNUM_HAL_INTERRUPT_SIU_LVL7]);
#endif
}
return result;
}
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int i, cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
#define NUM_CHANNELS CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS
for (i = 0; i < NUM_CHANNELS; i++) {
// Disable interrupts.
HAL_INTERRUPT_MASK(channels[i].isr_vector);
// Init channels
cyg_hal_plf_serial_init_channel((void*)&channels[i]);
// Setup procs in the vector table
// Set COMM callbacks for channel
CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
}
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
void
cyg_hal_am33_serial_init(int first_chan)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
int i;
for (i = 0; i < AM33_NUM_UARTS; i++) {
// Disable interrupts.
HAL_INTERRUPT_MASK(channels[0].isr_vector);
// Init channel
cyg_hal_plf_serial_init_channel((void*)&channels[i]);
cyg_hal_plf_serial_set_baud(channels[i].base, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD);
// Setup procs in the vector table
CYGACC_CALL_IF_SET_CONSOLE_COMM(i + first_chan);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
}
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
static void cyg_hal_plf_duart_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
int i;
// Init channels
#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
for (i = 0; i < NUMOF(channels); i++) {
HAL_INTERRUPT_MASK(channels[i].isr_vector);
init_duart_channel(&channels[i]);
CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
}
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
static void cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
int iChannels = sizeof(s_atSerialChannels) / sizeof(s_atSerialChannels[0]);
int iIdx;
for(iIdx = 0; iIdx < iChannels; iIdx++)
{
// Disable interrupts.
HAL_INTERRUPT_MASK(s_atSerialChannels[iIdx].isr_vector);
// Init channels
cyg_hal_plf_serial_init_channel(&s_atSerialChannels[iIdx]);
// Setup procs in the vector table
CYGACC_CALL_IF_SET_CONSOLE_COMM(iIdx);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &s_atSerialChannels[iIdx]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
}
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
void cyg_hal_plf_screen_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
// Disable interrupts.
HAL_INTERRUPT_MASK(pc_ser_channels[PCMB_PORT_INDEX].isr_vector);
// Init channels
cyg_hal_plf_screen_init_channel(&pc_ser_channels[PCMB_PORT_INDEX]);
// Setup procs in the vector table
// Set channel 2
CYGACC_CALL_IF_SET_CONSOLE_COMM(PCMB_PORT_INDEX);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &pc_ser_channels[PCMB_PORT_INDEX]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_screen_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_screen_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_screen_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_screen_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_screen_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_screen_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_screen_getc_timeout);
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
int ret = 0;
struct port_info *info = (struct port_info *)__ch_data;
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
HAL_INTERRUPT_UNMASK(info->intnum);
info->irq_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
ret = info->irq_state;
info->irq_state = 0;
HAL_INTERRUPT_MASK(info->intnum);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = info->intnum;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = msec_timeout;
msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
return ret;
}
void
cyg_hal_ixp425_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int i, cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
for (i = 0; i < IXP425_NUM_UARTS; i++) {
// Disable interrupts.
HAL_INTERRUPT_MASK(plf_ser_channels[i].isr_vector);
// Init channels
cyg_hal_plf_serial_init_channel(&plf_ser_channels[i]);
// Setup procs in the vector table
CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &plf_ser_channels[i]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
}
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
static void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
// 8-1-no parity.
HAL_WRITE_UINT32(base+E7T_UART_LCON,
E7T_UART_LCON_8_DBITS|E7T_UART_LCON_1_SBITS|E7T_UART_LCON_NO_PARITY);
HAL_WRITE_UINT32(base+E7T_UART_BRDIV, SIO_BRDDIV);
// Mask interrupts
HAL_INTERRUPT_MASK(((channel_data_t*)__ch_data)->isr_vector_rx);
HAL_INTERRUPT_MASK(((channel_data_t*)__ch_data)->isr_vector_tx);
// Enable RX and TX
HAL_WRITE_UINT32(base+E7T_UART_CON, E7T_UART_CON_RXM_INT|E7T_UART_CON_TXM_INT);
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
{
va_list ap;
va_start(ap, __func);
ret = chan->baud_rate;
chan->baud_rate = va_arg(ap, cyg_int32);
init_serial_channel(chan);
va_end(ap);
}
break;
case __COMMCTL_IRQ_ENABLE:
// Just enable the interrupt on the IMB3. The debugged application is
// must make sure that the interrupt is properly decoded
HAL_INTERRUPT_UNMASK(chan->imb3_vector);
irq_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
// Same remark as above
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->imb3_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->imb3_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
cyg_hal_plf_serial_control(void* __ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
volatile cyg_uint32* pulBase = chan->pulBase;
int ret = 0;
cyg_uint8 status;
CYGARC_HAL_SAVE_GP();
switch (__func)
{
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
// Ensure that only Receive ints are generated.
status = pulBase[REL_Adr_uartcr / sizeof(cyg_uint8)];
status |= (MSK_uartcr_RTIE | MSK_uartcr_RIE);
pulBase[REL_Adr_uartcr / sizeof(cyg_uint8)] = status;
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
status = pulBase[REL_Adr_uartcr / sizeof(cyg_uint8)];
status &= ~(MSK_uartcr_RTIE | MSK_uartcr_TIE | MSK_uartcr_RIE | MSK_uartcr_MSIE);
pulBase[REL_Adr_uartcr / sizeof(cyg_uint8)] = status;
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint16 ser_port_reg;
int ret = 0;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
cyg_hal_plf_serial_init_channel(chan);
ret = 0;
break;
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
ser_port_reg |= FREESCALE_ESCI_CR12_RIE;
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
ser_port_reg &= ~(cyg_uint16)FREESCALE_ESCI_CR12_RIE;
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
externC void
hal_mpc5xx_remove_arbitration_isr(hal_mpc5xx_arbitration_data * adata)
{
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
// Prevent anything from coming through while manipulating the list
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
imb3_data_head = mpc5xx_remove(imb3_data_head, adata);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#endif
}
static int
net_io_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int vector = 0;
int ret = 0;
static int irq_state = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
if (vector == 0) {
vector = eth_drv_int_vector();
}
HAL_INTERRUPT_UNMASK(vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
if (vector == 0) {
vector = eth_drv_int_vector();
}
HAL_INTERRUPT_MASK(vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = _timeout;
_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
break;
}
case __COMMCTL_FLUSH_OUTPUT:
net_io_flush();
break;
case __COMMCTL_ENABLE_LINE_FLUSH:
flush_output_lines = true;
break;
case __COMMCTL_DISABLE_LINE_FLUSH:
flush_output_lines = false;
break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base;
cyg_uint8 ser_port_reg;
int ret = 0;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
chan->irq_state = 1;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE;
HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
break;
case __COMMCTL_IRQ_DISABLE:
ret = chan->irq_state;
chan->irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE;
HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
cyg_hal_plf_serial_init_channel(chan);
ret = 0;
break;
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
externC void
hal_variant_IRQ_init(void)
{
HAL_INTERRUPT_MASK (CYGNUM_EXPANSION);
/* clear the mask register */
HAL_WRITE_UINT32(INTR_MASK_REG, 0); /* all expansion interrupts are masked */
HAL_INTERRUPT_ATTACH (CYGNUM_EXPANSION, &hal_extended_isr, 0, 0);
HAL_INTERRUPT_UNMASK (CYGNUM_EXPANSION);
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
{
va_list ap;
va_start(ap, __func);
chan->baud_rate = va_arg(ap, cyg_int32);
va_end(ap);
ret = set_baud(chan);
break;
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
externC void
hal_IRQ_init(void)
{
int i;
/* yes this is a quick fix; arch.inc should be changed, but this is
* good enough for now */
for (i=0; i <= CYGNUM_HAL_INTERRUPT_5;++i )
HAL_INTERRUPT_MASK (i);
hal_variant_IRQ_init();
}
externC void cyg_drv_interrupt_mask_intunsafe( cyg_vector_t vector )
{
CYG_REPORT_FUNCTION();
CYG_REPORT_FUNCARG1("vector=%d", vector);
CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
HAL_INTERRUPT_MASK( vector );
CYG_REPORT_RETURN();
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = -1;
cyg_uint8 ier;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
init_channel(chan);
ret = 0;
break;
case __COMMCTL_IRQ_ENABLE:
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier);
ier |= PXA2X0_UART_IER_RAVIE;
HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier);
irq_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier);
ier &= ~PXA2X0_UART_IER_RAVIE;
HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
break;
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
cyg_uint8 status;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
// Ensure that only Receive ints are generated.
status = IO_READ(chan->base + AMBA_UARTCR);
status |= (AMBA_UARTCR_RTIE | AMBA_UARTCR_RIE);
HAL_WRITE_UINT32(chan->base + AMBA_UARTCR, status);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
status = IO_READ(chan->base + AMBA_UARTCR);
status &= ~(AMBA_UARTCR_RTIE | AMBA_UARTCR_TIE | AMBA_UARTCR_RIE | AMBA_UARTCR_MSIE);
HAL_WRITE_UINT32(chan->base + AMBA_UARTCR, status);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8 ier;
int ret = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
ier |= CYG_DEVICE_BK0_IER_RXHDL_IE;
HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
ier &= ~CYG_DEVICE_BK0_IER_RXHDL_IE;
HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
externC void cyg_drv_interrupt_mask( cyg_vector_t vector )
{
CYG_INTERRUPT_STATE old_ints;
CYG_REPORT_FUNCTION();
CYG_REPORT_FUNCARG1("vector=%d", vector);
CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
HAL_DISABLE_INTERRUPTS(old_ints);
HAL_INTERRUPT_MASK( vector );
HAL_RESTORE_INTERRUPTS(old_ints);
CYG_REPORT_RETURN();
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
cyg_uint32 intm;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
int ret = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_READ_UINT32(base+AAEC_UART_INTM, intm);
intm |= AAEC_UART_INT_RIS|AAEC_UART_INT_RTIS;
HAL_WRITE_UINT32(base+AAEC_UART_INTM, intm);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_READ_UINT32(base+AAEC_UART_INTM, intm);
intm &= ~(AAEC_UART_INT_RIS|AAEC_UART_INT_RTIS);
HAL_WRITE_UINT32(base+AAEC_UART_INTM, intm);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
cyg_hal_plf_serial_dbg_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
cyg_hal_plf_serial_dbg_init_channel(chan);
ret = 0;
break;
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_WRITE_UINT32((chan->base+AT91_DBG_IER), AT91_DBG_CSR_RXRDY);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_WRITE_UINT32((chan->base+AT91_DBG_IDR), AT91_DBG_CSR_RXRDY);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
cyg_hal_plf_serial_control(channel_data_t *chan, __comm_control_cmd_t func, ...)
{
Xuint16 opt;
int ret = 0;
led(1);
if (!chan->dev_ok) return ret;
switch (func) {
case __COMMCTL_IRQ_ENABLE:
opt = XUartNs550_GetOptions(&chan->dev) | XUN_OPTION_DATA_INTR;
XUartNs550_SetOptions(&chan->dev, opt);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
chan->int_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
ret = chan->int_state;
chan->int_state = 0;
opt = XUartNs550_GetOptions(&chan->dev) & ~XUN_OPTION_DATA_INTR;
XUartNs550_SetOptions(&chan->dev, opt);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
return ret;
}
