static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) { int res = 0; cyg_uint8 eir, c; channel_data_t* chan = (channel_data_t*)__ch_data; CYGARC_HAL_SAVE_GP(); HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_EIR, eir); *__ctrlc = 0; if( (eir & CYG_DEVICE_BK0_EIR_mask) == CYG_DEVICE_BK0_EIR_IRQ_RX ) { HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_RXD, c); if( cyg_hal_is_break( &c , 1 ) ) *__ctrlc = 1; res = CYG_ISR_HANDLED; } CYGARC_HAL_RESTORE_GP(); return res; }
static int cyg_hal_plf_sci_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) { cyg_uint8 c, sr; cyg_uint8* base = ((channel_data_t*)__ch_data)->base; int res = 0; CYGARC_HAL_SAVE_GP(); *__ctrlc = 0; HAL_READ_UINT8(base+_REG_SCSSR, sr); if (sr & CYGARC_REG_SCI_SCSSR_ORER) { // Serial RX overrun. Clear error and hope protocol recovers. HAL_WRITE_UINT8(base+_REG_SCSSR, CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_ORER); res = CYG_ISR_HANDLED; } else if (sr & CYGARC_REG_SCI_SCSSR_RDRF) { // Received character HAL_READ_UINT8(base+_REG_SCRDR, c); // Clear buffer full flag. HAL_WRITE_UINT8(base+_REG_SCSSR, CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_RDRF); if( cyg_hal_is_break( &c , 1 ) ) *__ctrlc = 1; res = CYG_ISR_HANDLED; } CYGARC_HAL_RESTORE_GP(); return res; }
static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) { cyg_uint8* port; cyg_uint8 _status; // Some of the diagnostic print code calls through here with no idea what the ch_data is. // Go ahead and assume it is channels[0]. if (__ch_data == 0) __ch_data = (void*)&channels[0]; port = ((channel_data_t*)__ch_data)->base; HAL_READ_UINT8(port + _SERIAL_SR, _status); if ((_status & SIO_LSTAT_RRDY) == 0) return false; HAL_READ_UINT8(port + _SERIAL_RXR, *ch); // We must ack the interrupt caused by that read to avoid // confusing the GDB stub ROM. HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SERIAL_0_RX ); return true; }
//static cyg_bool cyg_hal_plf_scif_getc_nonblock(void* __ch_data, cyg_uint8* ch) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; cyg_uint16 fdr, sr; cyg_bool res = false; HAL_READ_UINT16(base+_REG_SCSSR, sr); if (sr & CYGARC_REG_SCIF_SCSSR_ER) { cyg_uint8 ssr2; HAL_WRITE_UINT16(base+_REG_SCFER, 0); HAL_READ_UINT8(base+_REG_SC2SSR, ssr2); ssr2 &= ~CYGARC_REG_SCIF_SC2SSR_ORER; HAL_WRITE_UINT8(base+_REG_SC2SSR, ssr2); HAL_WRITE_UINT16(base+_REG_SCSSR, CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_BRK | CYGARC_REG_SCIF_SCSSR_FER | CYGARC_REG_SCIF_SCSSR_PER)); } HAL_READ_UINT16(base+_REG_SCFDR, fdr); if (0 != (fdr & CYGARC_REG_SCIF_SCFDR_RCOUNT_MASK)) { HAL_READ_UINT8(base+_REG_SCFRDR, *ch); // Clear DR/RDF flags HAL_READ_UINT16(base+_REG_SCSSR, sr); HAL_WRITE_UINT16(base+_REG_SCSSR, CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF | CYGARC_REG_SCIF_SCSSR_DR)); res = true; } return res; }
static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) { channel_data_t* chan = (channel_data_t*)__ch_data; CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base; cyg_uint8 uart_s1; int res = 0; cyg_uint8 ch_in; CYGARC_HAL_SAVE_GP(); *__ctrlc = 0; HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1); if (uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF) { HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in); if( cyg_hal_is_break( (char *) &ch_in , 1 ) ) *__ctrlc = 1; res = CYG_ISR_HANDLED; } HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); CYGARC_HAL_RESTORE_GP(); return res; }
// Sending out a command. The controller command, if any, gets sent here. // This is followed by the first byte for the keyboard or mouse. The // remaining bytes and any retransmits will be handled by the interrupt // handler. static void ps2_send_command(int controller_command, unsigned char* command, int length, int mouse) { int status; CYG_PRECONDITION(NULL == ps2_command, "Only one send command is allowed at a time"); CYG_PRECONDITION((KC_CONTROL_NULL != controller_command) || (NULL != command), "no-op"); CYG_PRECONDITION(!mouse || (KC_CONTROL_NULL == controller_command), "cannot combine controller and mouse commands"); ps2_command = command; ps2_command_index = 0; ps2_command_length = length; ps2_command_mouse = 0; ps2_command_ack = 0; if (KC_CONTROL_NULL != controller_command) { do { HAL_READ_UINT8(KC_STATUS, status); } while (status & KC_STATUS_INPB); HAL_WRITE_UINT8(KC_CONTROL, controller_command); } if (length > 0) { if (mouse) { do { HAL_READ_UINT8(KC_STATUS, status); } while (status & KC_STATUS_INPB); HAL_WRITE_UINT8(KC_CONTROL, KC_CONTROL_WRITE_AUX); } do { HAL_READ_UINT8(KC_STATUS, status); } while (status & KC_STATUS_INPB); HAL_WRITE_UINT8(KC_INPUT, command[0]); } }
static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) { int res = 0; channel_data_t* chan = (channel_data_t*)__ch_data; char c; cyg_uint8 lsr; CYGARC_HAL_SAVE_GP(); cyg_drv_interrupt_acknowledge(chan->isr_vector); *__ctrlc = 0; HAL_READ_UINT8(chan->base+CYG_DEV_LSR, lsr); if ( (lsr & SIO_LSR_DR) != 0 ) { HAL_READ_UINT8(chan->base+CYG_DEV_RBR, c); if( cyg_hal_is_break( &c , 1 ) ) *__ctrlc = 1; res = CYG_ISR_HANDLED; } CYGARC_HAL_RESTORE_GP(); return res; }
static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) { channel_data_t* chan = (channel_data_t*)__ch_data; cyg_uint8 iir; int res = 0; CYGARC_HAL_SAVE_GP(); HAL_READ_UINT8(chan->base+PXA2X0_UART_IIR, iir); iir &= PXA2X0_UART_IIR_ID_MASK; *__ctrlc = 0; if ( iir == 0x04 ) { cyg_uint8 c, lsr; HAL_READ_UINT8(chan->base+PXA2X0_UART_LSR, lsr); if (lsr & PXA2X0_UART_LSR_DR) { HAL_READ_UINT8(chan->base+PXA2X0_UART_RBR, c); if( cyg_hal_is_break( &c , 1 ) ) *__ctrlc = 1; } // Acknowledge the interrupt HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); res = CYG_ISR_HANDLED; } CYGARC_HAL_RESTORE_GP(); return res; }
void cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c) { channel_data_t* chan = (channel_data_t*)__ch_data; cyg_uint8* base = chan->base; cyg_uint16 fdr, sr; cyg_uint8 scscr = 0; CYGARC_HAL_SAVE_GP(); HAL_READ_UINT8(base+_REG_SCSCR, scscr); if (chan->irda_mode) { HAL_WRITE_UINT8(base+_REG_SCSCR, scscr|CYGARC_REG_SCIF_SCSCR_TE); } #ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX if (chan->async_rxtx_mode) { HAL_WRITE_UINT8(base+_REG_SCSCR, (scscr|CYGARC_REG_SCIF_SCSCR_TE)&~CYGARC_REG_SCIF_SCSCR_RE); } #endif do { HAL_READ_UINT16(base+_REG_SCFDR, fdr); } while (((fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) >> CYGARC_REG_SCIF_SCFDR_TCOUNT_shift) == 16); HAL_WRITE_UINT8(base+_REG_SCFTDR, c); // Clear FIFO-empty/transmit end flags (read back SR first) HAL_READ_UINT16(base+_REG_SCSSR, sr); HAL_WRITE_UINT16(base+_REG_SCSSR, CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_TDFE | CYGARC_REG_SCIF_SCSSR_TEND )); // Hang around until all characters have been safely sent. do { HAL_READ_UINT16(base+_REG_SCSSR, sr); } while ((sr & CYGARC_REG_SCIF_SCSSR_TEND) == 0); if (chan->irda_mode) { #ifdef CYGHWR_HAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION // In IrDA mode there will be generated spurious RX events when // the TX unit is switched on. Eat that character. cyg_uint8 _junk; HAL_READ_UINT8(base+_REG_SCFRDR, _junk); // Clear buffer full flag (read back first) HAL_READ_UINT16(base+_REG_SCSSR, sr); HAL_WRITE_UINT16(base+_REG_SCSSR, CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF|CYGARC_REG_SCIF_SCSSR_DR)); #endif // CYGHWR_HAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION // Disable transmitter again HAL_WRITE_UINT8(base+_REG_SCSCR, scscr); } #ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX if (chan->async_rxtx_mode) { // Disable transmitter, enable receiver HAL_WRITE_UINT8(base+_REG_SCSCR, scscr); } #endif // CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX CYGARC_HAL_RESTORE_GP(); }
static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) { int res = 0; cyg_uint8 _iir, c; channel_data_t* chan; CYGARC_HAL_SAVE_GP(); // Some of the diagnostic print code calls through here with no idea what the ch_data is. // Go ahead and assume it is channels[0]. if (__ch_data == 0) __ch_data = (void*)&channels[0]; chan = (channel_data_t*)__ch_data; HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); HAL_READ_UINT8(chan->base + SER_16550_IIR, _iir); _iir &= SIO_IIR_ID_MASK; *__ctrlc = 0; if ((_iir == ISR_Rx_Avail) || (_iir == ISR_Rx_Char_Timeout)) { HAL_READ_UINT8(chan->base + SER_16550_RBR, c); if( cyg_hal_is_break( &c , 1 ) ) *__ctrlc = 1; res = CYG_ISR_HANDLED; } CYGARC_HAL_RESTORE_GP(); return res; }
void cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch) { cyg_uint8* port; cyg_uint8 _lsr; // Some of the diagnostic print code calls through here with no idea what the ch_data is. // Go ahead and assume it is channels[0]. if (__ch_data == 0) __ch_data = (void*)&channels[0]; port = ((channel_data_t*)__ch_data)->base; CYGARC_HAL_SAVE_GP(); do { HAL_READ_UINT8(port+SER_16550_LSR, _lsr); } while ((_lsr & SIO_LSR_THRE) == 0); // Now, the transmit buffer is empty HAL_WRITE_UINT8(port+SER_16550_THR, __ch); // Hang around until the character has been safely sent. do { HAL_READ_UINT8(port+SER_16550_LSR, _lsr); } while ((_lsr & SIO_LSR_THRE) == 0); CYGARC_HAL_RESTORE_GP(); }
void cyg_hal_plf_serial_init_channel(void* __ch_data) { cyg_uint8 port; cyg_uint8 value; port = ((channel_data_t*)__ch_data)->base; // set the port direction and function registers to serial switch (port){ case CYG_HAL_FR30_MB91301_SER0_BASE: HAL_READ_UINT8(CYG_HAL_FR30_MB91301_DDRJ, value); value |= 0x6; value &= ~0x1; HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_DDRJ, value); HAL_READ_UINT8(CYG_HAL_FR30_MB91301_PFRJ, value); HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_PFRJ, value | 0x7); if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT == 0){ cyg_hal_plf_serial_set_baudrate_internal(port, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD); } else { cyg_hal_plf_serial_set_baudrate_internal(port, CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD); } break; case CYG_HAL_FR30_MB91301_SER1_BASE: HAL_READ_UINT8(CYG_HAL_FR30_MB91301_DDRJ, value); value |= 0x30; value &= ~0x8; HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_DDRJ, value); HAL_READ_UINT8(CYG_HAL_FR30_MB91301_PFRJ, value); HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_PFRJ, value | 0x38); if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT == 1){ cyg_hal_plf_serial_set_baudrate_internal(port, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD); } else { cyg_hal_plf_serial_set_baudrate_internal(port, CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD); } break; /* case CYG_HAL_FR30_MB91301_SER2_BASE: HAL_READ_UINT8(CYG_HAL_FR30_MB91301_DDRG, value); HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_DDRG, value | 0x40); HAL_READ_UINT8(CYG_HAL_FR30_MB91301_PFRG, value); HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_PFRG, value | 0x60); break; */ } // set up U-Timer /* HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_UTIMC_OFFSET, 0x02); // 115200 bps HAL_WRITE_UINT16(port + CYG_HAL_FR30_MB91301_UTIMR_OFFSET, 0x7); cyg_hal_plf_serial_set_baudrate_internal(port, baudrate); */ // setup UART HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_SCR_OFFSET, 0x13); HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_SMR_OFFSET, 0x30); }
static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) { channel_data_t* chan = (channel_data_t*)__ch_data; CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base; cyg_uint8 ser_port_reg; int ret = 0; va_list ap; CYGARC_HAL_SAVE_GP(); va_start(ap, __func); switch (__func) { case __COMMCTL_IRQ_ENABLE: chan->irq_state = 1; HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); HAL_INTERRUPT_UNMASK(chan->isr_vector); HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE; HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); break; case __COMMCTL_IRQ_DISABLE: ret = chan->irq_state; chan->irq_state = 0; HAL_INTERRUPT_MASK(chan->isr_vector); HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE; HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); break; case __COMMCTL_DBG_ISR_VECTOR: ret = chan->isr_vector; break; case __COMMCTL_SET_TIMEOUT: ret = chan->msec_timeout; chan->msec_timeout = va_arg(ap, cyg_uint32); case __COMMCTL_GETBAUD: ret = chan->baud_rate; break; case __COMMCTL_SETBAUD: chan->baud_rate = va_arg(ap, cyg_int32); // Should we verify this value here? cyg_hal_plf_serial_init_channel(chan); ret = 0; break; default: break; } va_end(ap); CYGARC_HAL_RESTORE_GP(); return ret; }
externC bool hal_ppc405_i2c_put_bytes(int addr, cyg_uint8 *val, int len) { cyg_uint8 stat, extstat, xfrcnt, cmd, size; int i, j; // The hardware can only move up to 4 bytes in a single operation // This code breaks the request down into chunks of up to 4 bytes // and checks the status after each chunk. // Note: the actual device may impose additional size restrictions, // e.g. some EEPROM devices may limit a single write to 32 bytes. for (i = 0; i < len; i += size) { HAL_WRITE_UINT8(IIC0_STS, (IIC0_STS_SCMP|IIC0_STS_IRQA)); HAL_WRITE_UINT8(IIC0_EXTSTS, (IIC0_EXTSTS_IRQP|IIC0_EXTSTS_IRQD)); HAL_WRITE_UINT8(IIC0_MDCNTL, (IIC0_MDCNTL_FSDB|IIC0_MDCNTL_FMDB)); cmd = IIC0_CNTL_RW_WRITE|IIC0_CNTL_PT; size = (len - i); if (size > 4) { size = 4; cmd |= IIC0_CNTL_CHT; } cmd |= ((size-1)<<IIC0_CNTL_TCT_SHIFT); for (j = 0; j < size; j++) { HAL_WRITE_UINT8(IIC0_MDBUF, val[i+j]); } HAL_WRITE_UINT8(IIC0_LMADR, addr); HAL_WRITE_UINT8(IIC0_CNTL, cmd); while (true) { CYGACC_CALL_IF_DELAY_US(10); // 10us HAL_READ_UINT8(IIC0_STS, stat); if ((stat & IIC0_STS_PT) == 0) { if ((stat & IIC0_STS_ERR) != 0) { // Some sort of error HAL_READ_UINT8(IIC0_EXTSTS, extstat); HAL_READ_UINT8(IIC0_XFRCNT, xfrcnt); HAL_WRITE_UINT8(IIC0_EXTSTS, extstat); HAL_WRITE_UINT8(IIC0_MDCNTL, (IIC0_MDCNTL_FSDB|IIC0_MDCNTL_FMDB)); HAL_WRITE_UINT8(IIC0_STS, (IIC0_STS_SCMP|IIC0_STS_IRQA)); diag_printf("%s addr: %x, len: %d, err: %x/%x, count: %d, cmd: %x\n", __FUNCTION__, addr, len, stat, extstat, xfrcnt, cmd); diag_printf("buf: "); for (j = 0; j < size; j++) { diag_printf("0x%02x ", val[i+j]); } diag_printf("\n"); return false; } break; } } } return true; }
static int cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) { static int irq_state = 0; channel_data_t* chan = (channel_data_t*)__ch_data; int ret = -1; cyg_uint8 ier; va_list ap; CYGARC_HAL_SAVE_GP(); va_start(ap, __func); switch (__func) { case __COMMCTL_GETBAUD: ret = chan->baud_rate; break; case __COMMCTL_SETBAUD: chan->baud_rate = va_arg(ap, cyg_int32); // Should we verify this value here? init_channel(chan); ret = 0; break; case __COMMCTL_IRQ_ENABLE: HAL_INTERRUPT_UNMASK(chan->isr_vector); HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1); HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier); ier |= PXA2X0_UART_IER_RAVIE; HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier); irq_state = 1; break; case __COMMCTL_IRQ_DISABLE: ret = irq_state; irq_state = 0; HAL_INTERRUPT_MASK(chan->isr_vector); HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier); ier &= ~PXA2X0_UART_IER_RAVIE; HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier); break; case __COMMCTL_DBG_ISR_VECTOR: ret = chan->isr_vector; break; case __COMMCTL_SET_TIMEOUT: ret = chan->msec_timeout; chan->msec_timeout = va_arg(ap, cyg_uint32); break; default: break; } va_end(ap); CYGARC_HAL_RESTORE_GP(); return ret; }
void hal_interrupt_status(void) { int irq_status, irq_enable, ipr_value, timer_value; cyg_uint8 reg; HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // LSB timer_value = reg; HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // MSB timer_value |= (reg << 8); HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQSR, irq_status); HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, irq_enable); HAL_READ_UINT32(CYG_DEVICE_ICTL_IPR, ipr_value); diag_printf("Interrupt: IRQ: %x.%x.%x, Timer: %x\n", irq_status, irq_enable, ipr_value, timer_value); }
// Fetch a character from the device input buffer, waiting if necessary static unsigned char mipsidt_serial_getc(serial_channel *chan) { unsigned char c; mipsidt_serial_info *mipsidt_chan = (mipsidt_serial_info *)chan->dev_priv; cyg_addrword_t port = mipsidt_chan->base; cyg_uint8 _lsr; do { HAL_READ_UINT8(port+SER_16550_LSR, _lsr); } while ((_lsr & SIO_LSR_DR) == 0); HAL_READ_UINT8(port+SER_16550_RBR, c); return c; }
static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; cyg_uint8 lsr; HAL_READ_UINT8(base+PXA2X0_UART_LSR, lsr); if ((lsr & PXA2X0_UART_LSR_DR) == 0) return false; HAL_READ_UINT8(base+PXA2X0_UART_RBR, *ch); return true; }
static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; cyg_uint8 lsr; HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr); if ((lsr & CYG_DEVICE_BK0_LSR_RXDA) == 0) return false; HAL_READ_UINT8 (base+CYG_DEVICE_BK0_RXD, *ch); return true; }
static int cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) { static int irq_state = 0; channel_data_t* chan = (channel_data_t*)__ch_data; cyg_uint8 ier; int ret = 0; CYGARC_HAL_SAVE_GP(); switch (__func) { case __COMMCTL_IRQ_ENABLE: irq_state = 1; HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier); ier |= CYG_DEVICE_BK0_IER_RXHDL_IE; HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier); HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1); HAL_INTERRUPT_UNMASK(chan->isr_vector); break; case __COMMCTL_IRQ_DISABLE: ret = irq_state; irq_state = 0; HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier); ier &= ~CYG_DEVICE_BK0_IER_RXHDL_IE; HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier); HAL_INTERRUPT_MASK(chan->isr_vector); break; case __COMMCTL_DBG_ISR_VECTOR: ret = chan->isr_vector; break; case __COMMCTL_SET_TIMEOUT: { va_list ap; va_start(ap, __func); ret = chan->msec_timeout; chan->msec_timeout = va_arg(ap, cyg_uint32); va_end(ap); } default: break; } CYGARC_HAL_RESTORE_GP(); return ret; }
void hal_clock_read(cyg_uint32 *pvalue) { cyg_uint32 value; cyg_uint8 reg; do { HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL, TIMER_CTL_RW_LATCH|TIMER_CTL_SC_CTR0); HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // LSB value = reg; HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // MSB value |= (reg << 8); } while (value <= 2); // Hardware malfunction? *pvalue = _period - (value & 0xFFFF); // Note: counter is only 16 bits // and decreases }
static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) { cyg_uint8 ssr; cyg_uint8 port; port = ((channel_data_t*)__ch_data)->base; HAL_READ_UINT8(port + CYG_HAL_FR30_MB91301_SSR_OFFSET, ssr); if (!(ssr & BIT4)) return false; HAL_READ_UINT8(port + CYG_HAL_FR30_MB91301_SIDR_OFFSET, *ch); // hal_diag_led(port); return true; }
// Serial I/O - high level interrupt handler (DSR) static void smdk2410_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) { serial_channel *chan = (serial_channel *)data; smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv; CYG_ADDRWORD base = smdk2410_chan->base; cyg_uint32 _intsubpnd, _status, _c; cyg_uint32 _rxd_bit = (smdk2410_chan->bit_sub_rxd<<0), _txd_bit=(smdk2410_chan->bit_sub_rxd<<1); HAL_READ_UINT32(SUBSRCPND, _intsubpnd); // Empty Rx FIFO if (_intsubpnd & _rxd_bit) { HAL_READ_UINT32(base+OFS_UFSTAT, _status); while((_status & 0x0f) != 0) { HAL_READ_UINT8(base+OFS_URXH, _c); (chan->callbacks->rcv_char)(chan, (unsigned char)_c); HAL_READ_UINT32(base+OFS_UFSTAT, _status); } HAL_WRITE_UINT32(SUBSRCPND, _rxd_bit); } // Fill into Tx FIFO. xmt_char will mask the interrupt when it // runs out of chars, so doing this in a loop is OK. if (_intsubpnd & _txd_bit) { (chan->callbacks->xmt_char)(chan); HAL_WRITE_UINT32(SUBSRCPND, _txd_bit); } cyg_drv_interrupt_unmask(smdk2410_chan->int_num); }
static int cyg_hal_plf_scif_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) { cyg_uint8 c; cyg_uint16 fdr, sr; cyg_uint8* base = ((channel_data_t*)__ch_data)->base; int res = 0; CYGARC_HAL_SAVE_GP(); *__ctrlc = 0; HAL_READ_UINT16(base+_REG_SCFDR, fdr); if ((fdr & CYGARC_REG_SCIF_SCFDR_RCOUNT_MASK) != 0) { HAL_READ_UINT8(base+_REG_SCFRDR, c); // Clear buffer full flag (read back first). HAL_READ_UINT16(base+_REG_SCSSR, sr); HAL_WRITE_UINT16(base+_REG_SCSSR, CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~CYGARC_REG_SCIF_SCSSR_RDF); if( cyg_hal_is_break( &c , 1 ) ) *__ctrlc = 1; res = CYG_ISR_HANDLED; } CYGARC_HAL_RESTORE_GP(); return res; }
void cyg_hal_plf_scif_init_channel(channel_data_t* chan) { cyg_uint8* base = chan->base; cyg_uint8 tmp; cyg_uint16 sr; int baud_rate = CYGNUM_HAL_SH_SH2_SCIF_BAUD_RATE; // Disable everything. HAL_WRITE_UINT8(base+_REG_SCSCR, 0); // Reset FIFO. HAL_WRITE_UINT8(base+_REG_SCFCR, CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST); HAL_WRITE_UINT16(base+_REG_SCFER, 0); // 8-1-no parity. This is also fine for IrDA mode HAL_WRITE_UINT8(base+_REG_SCSMR, 0); if (chan->irda_mode) HAL_WRITE_UINT8(base+_REG_SCIMR, CYGARC_REG_SCIF_SCIMR_IRMOD); else { HAL_WRITE_UINT8(base+_REG_SCIMR, 0); } // Set speed to CYGNUM_HAL_SH_SH2_SCIF_DEFAULT_BAUD_RATE HAL_READ_UINT8(base+_REG_SCSMR, tmp); tmp &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK; tmp |= CYGARC_SCBRR_CKSx(baud_rate); HAL_WRITE_UINT8(base+_REG_SCSMR, tmp); HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(baud_rate)); // Let things settle: Here we should should wait the equivalent of // one bit interval, // i.e. 1/CYGNUM_HAL_SH_SH2_SCIF_DEFAULT_BAUD_RATE second, but // until we have something like the Linux delay loop, it's hard to // do reliably. So just move on and hope for the best (this is // unlikely to cause problems since the CPU has just come out of // reset anyway). // Clear status register (read back first). HAL_READ_UINT16(base+_REG_SCSSR, sr); HAL_WRITE_UINT16(base+_REG_SCSSR, 0); HAL_WRITE_UINT8(base+_REG_SC2SSR, CYGARC_REG_SCIF_SC2SSR_BITRATE_16|CYGARC_REG_SCIF_SC2SSR_EI); // Bring FIFO out of reset and set to trigger on every char in // FIFO (or C-c input would not be processed). HAL_WRITE_UINT8(base+_REG_SCFCR, CYGARC_REG_SCIF_SCFCR_RTRG_1|CYGARC_REG_SCIF_SCFCR_TTRG_1); // Leave Tx/Rx interrupts disabled, but enable Rx/Tx (only Rx for IrDA) if (chan->irda_mode) HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE); #ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX else if (chan->async_rxtx_mode) HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE); #endif else HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_TE|CYGARC_REG_SCIF_SCSCR_RE); }
// Return one byte from DM9000 register static cyg_uint8 getreg(struct dm9000 *p, cyg_uint8 reg) { cyg_uint8 val; HAL_WRITE_UINT8(p->io_addr, reg); HAL_READ_UINT8(p->io_data, val); return val; }
static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) { channel_data_t* chan = (channel_data_t*)__ch_data; CYG_ADDRESS esci_base = (CYG_ADDRESS) chan->base; cyg_uint16 esci_sr; int res = 0; cyg_uint8 ch_in; CYGARC_HAL_SAVE_GP(); *__ctrlc = 0; HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr); if (esci_sr & FREESCALE_ESCI_SR_RDRF) { HAL_READ_UINT8(FREESCALE_ESCI_DRL(esci_base), ch_in); if( cyg_hal_is_break( (char *) &ch_in , 1 ) ) *__ctrlc = 1; res = CYG_ISR_HANDLED; HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_RDRF); } HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); CYGARC_HAL_RESTORE_GP(); return res; }
cyg_uint32 keyb_isr_handler(cyg_vector_t vector, cyg_addrword_t data) { cyg_interrupt_acknowledge(vector); // Read Keyboard status cyg_uint8 kbstat, code = 0; HAL_READ_UINT8( KBSTATPORT, kbstat ); // If Data available, read them -> implicitly acknowledges interrupt on hardware side! if( (kbstat & 0x01) != 0 ){ HAL_READ_UINT8( KBDATAPORT, code ); g_keycode = code; // Only resume thread, if there is a new keycode. return CYG_ISR_CALL_DSR | CYG_ISR_HANDLED; } return CYG_ISR_HANDLED; }
static cyg_uint32 mn10300_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) { serial_channel *chan = (serial_channel *)data; mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; cyg_uint8 sr = mn10300_read_sr( mn10300_chan); while( (sr & SR_RBF) != 0 ) { register cyg_int32 head = mn10300_chan->fifo_head; cyg_uint8 c; int i; HAL_READ_UINT8( mn10300_chan->base+SERIAL_RXB, c ); mn10300_chan->fifo[head++] = c; if( head >= sizeof(mn10300_chan->fifo) ) head = 0; mn10300_chan->fifo_head = head; sr = mn10300_read_sr( mn10300_chan); } cyg_drv_interrupt_acknowledge(mn10300_chan->rx_int); return CYG_ISR_CALL_DSR; // Cause DSR to be run }
void hal_clock_initialize(cyg_uint32 period) { cyg_uint8 prescale; cyg_uint8 tmp; #if CYGNUM_HAL_H8300_RTC_PRESCALE == 8 prescale = 0x01; #else #if CYGNUM_HAL_H8300_RTC_PRESCALE == 64 prescale = 0x02; #else #if CYGNUM_HAL_H8300_RTC_PRESCALE == 8192 prescale = 0x03; #else #error illigal RTC prescale setting #endif #endif #endif HAL_READ_UINT8(CYGARC_MSTPCRL, tmp); tmp &= ~0x01; HAL_WRITE_UINT8(CYGARC_MSTPCRL, tmp); HAL_WRITE_UINT8(CYGARC_8TCORA1, period); HAL_WRITE_UINT8(CYGARC_8TCNT1, 0x00); HAL_WRITE_UINT8(CYGARC_8TCR1, 0x48 | prescale); HAL_WRITE_UINT8(CYGARC_8TCSR1, 0x00); }