static void
program_flash(cyg_addrword_t arg)
{
diag_printf("PROGRAM FLASH here!\n");
HAL_UCACHE_SYNC(); // ROM space is marked cacheable which causes problems!
HAL_UCACHE_DISABLE(); // So, just disable caches.
identify_FLASH();
diag_printf("About to program FLASH using data at %x..%x\n", flash_buffer, flash_buffer_end);
diag_printf("*** Press RESET now to abort!\n");
cyg_thread_delay(5*100);
diag_printf("\n");
diag_printf("... Erase sector\n");
if (erase_sector(ROM_address)) {
diag_printf("... Programming FLASH\n");
while (flash_buffer < flash_buffer_end) {
if (!write_flash(flash_buffer++, ROM_address++)) break;
}
}
// Exit Program Mode
switch (manuf_code) {
case ATMEL_MANUF:
FLASH[ATMEL_SEQ_ADD1] = ATMEL_START_CMD1;
FLASH[ATMEL_SEQ_ADD2] = ATMEL_START_CMD2;
FLASH[ATMEL_SEQ_ADD1] = ATMEL_STOP_CMD;
break;
case INTEL_MANUF:
FLASH[0] = INTEL_STOP_CMD;
break;
}
diag_printf("All done!\n");
cyg_test_exit();
}
static void entry0( cyg_addrword_t data )
{
register CYG_INTERRUPT_STATE oldints;
#ifdef HAL_CACHE_UNIFIED
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL(); // rely on above definition
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL(); // rely on above definition
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache on");
time1();
#ifdef HAL_DCACHE_INVALIDATE_ALL
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache on: invalidate Cache (expect bogus timing)");
time1DI();
#endif
#else // HAL_CACHE_UNIFIED
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache on");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache off (again)");
time1();
#if defined(HAL_DCACHE_INVALIDATE_ALL) || defined(HAL_ICACHE_INVALIDATE_ALL)
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on (again)");
time1();
#if defined(CYGPKG_HAL_MIPS)
// In some architectures, the time taken for the next two tests is
// very long, partly because HAL_XCACHE_INVALIDATE_ALL() is implemented
// with a loop over the cache. Hence these tests take longer than the
// testing infrastructure is prepared to wait. The simplest way to get
// these tests to run quickly is to make them think they are running
// under a simulator.
// If the target actually is a simulator, skip the below - it's very
// slow on the simulator, even with reduced loop counts.
if (cyg_test_is_simulator)
CYG_TEST_PASS_FINISH("End of test");
#if defined(CYGPKG_HAL_MIPS_TX49)
// The TX49 has a large cache, and even with reduced loop count,
// 90+ seconds elapses between each INFO output.
CYG_TEST_PASS_FINISH("End of test");
#endif
cyg_test_is_simulator = 1;
#endif
#ifdef HAL_ICACHE_INVALIDATE_ALL
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on: invalidate ICache each time");
time1II();
#endif
#ifdef HAL_DCACHE_INVALIDATE_ALL
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on: invalidate DCache (expect bogus times)");
time1DI();
#endif
#endif // either INVALIDATE_ALL macro
#endif // HAL_CACHE_UNIFIED
CYG_TEST_PASS_FINISH("End of test");
}
static void entry0( void )
{
register CYG_INTERRUPT_STATE oldints;
#ifdef HAL_CACHE_UNIFIED
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL(); // rely on above definition
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL(); // rely on above definition
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache on");
time1();
#else // HAL_CACHE_UNIFIED
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache on");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache off");
time1();
#endif // HAL_CACHE_UNIFIED
CYG_TEST_PASS_FINISH("End of test");
}
