/** \brief Configures the EBI for NandFlash access at 133Mhz.
*/
void BOARD_ConfigureNandFlash( uint8_t busWidth )
{
PMC_EnablePeripheral(ID_HSMC);
matrix_configure_slave_nand();
HSMC->HSMC_CS_NUMBER[3].HSMC_SETUP = 0
| HSMC_SETUP_NWE_SETUP(2)
| HSMC_SETUP_NCS_WR_SETUP(2)
| HSMC_SETUP_NRD_SETUP(2)
| HSMC_SETUP_NCS_RD_SETUP(2);
HSMC->HSMC_CS_NUMBER[3].HSMC_PULSE = 0
| HSMC_PULSE_NWE_PULSE(7)
| HSMC_PULSE_NCS_WR_PULSE(7)
| HSMC_PULSE_NRD_PULSE(7)
| HSMC_PULSE_NCS_RD_PULSE(7);
HSMC->HSMC_CS_NUMBER[3].HSMC_CYCLE = 0
| HSMC_CYCLE_NWE_CYCLE(13)
| HSMC_CYCLE_NRD_CYCLE(13);
HSMC->HSMC_CS_NUMBER[3].HSMC_TIMINGS = HSMC_TIMINGS_TCLR(3)
| HSMC_TIMINGS_TADL(27)
| HSMC_TIMINGS_TAR(3)
| HSMC_TIMINGS_TRR(6)
| HSMC_TIMINGS_TWB(5)
| HSMC_TIMINGS_RBNSEL(3)
|(HSMC_TIMINGS_NFSEL);
HSMC->HSMC_CS_NUMBER[3].HSMC_MODE = HSMC_MODE_READ_MODE |
HSMC_MODE_WRITE_MODE |
((busWidth == 8 )? HSMC_MODE_DBW_BIT_8 :HSMC_MODE_DBW_BIT_16) |
HSMC_MODE_TDF_CYCLES(1);
}
int board_nandflash_config(int cs)
{
uint32_t regval;
/* The Embest and Ronetix CM boards and one Hynix NAND HY27UF(08/16)2G2B
* Series NAND (MT29F2G08ABAEAWP). This part has a capacity of 256Mx8bit
* () with spare 8Mx8 bit capacity. The device contains 2048 blocks, composed
* by 64 x 2112 byte pages. The effective size is approximately 256MiB.
*
* NAND is available on CS3.
*/
if (cs == HSMC_CS3)
{
/* Make sure that the SMC peripheral is enabled. */
sam_hsmc_enableclk();
/* Configure the SMC */
regval = HSMC_SETUP_NWE_SETUP(1) | HSMC_SETUP_NCS_WRSETUP(1) |
HSMC_SETUP_NRD_SETUP(2) | HSMC_SETUP_NCS_RDSETUP(1);
putreg32(regval, SAM_HSMC_SETUP(HSMC_CS3));
regval = HSMC_PULSE_NWE_PULSE(5) | HSMC_PULSE_NCS_WRPULSE(7) |
HSMC_PULSE_NRD_PULSE(5) | HSMC_PULSE_NCS_RDPULSE(7);
putreg32(regval, SAM_HSMC_PULSE(HSMC_CS3));
regval = HSMC_CYCLE_NWE_CYCLE(8) | HSMC_CYCLE_NRD_CYCLE(9);
putreg32(regval, SAM_HSMC_CYCLE(HSMC_CS3));
regval = HSMC_TIMINGS_TCLR(3) | HSMC_TIMINGS_TADL(10) |
HSMC_TIMINGS_TAR(3) | HSMC_TIMINGS_TRR(4) |
HSMC_TIMINGS_TWB(5) | HSMC_TIMINGS_RBNSEL(3) |
HSMC_TIMINGS_NFSEL;
putreg32(regval, SAM_HSMC_TIMINGS(HSMC_CS3));
regval = HSMC_MODE_READMODE | HSMC_MODE_WRITEMODE |
HSMC_MODE_BIT_8 | HSMC_MODE_TDFCYCLES(1);
putreg32(regval, SAM_HSMC_MODE(HSMC_CS3));
/* Configure NAND PIO pins
*
* NAND Interface:
*
* NCS3/NANDCE - Dedicated pin; no configuration needed
* NANDCLE - PE21
* NANDALE - PE22
* NRD/NANDOE - Dedicated pin; no configuration needed
* NWE/NANDWE - Dedicated pin; no configuration needed
* NANDRDY - Dedicated pin; no configuration needed
* M_EBI_D0-7 - Dedicated pins; no configuration needed
*/
sam_configpio(PIO_HSMC_NANDALE);
sam_configpio(PIO_HSMC_NANDCLE);
return OK;
}
return -ENODEV;
}
int nor_main(int argc, char *argv)
{
uint32_t regval;
/* Here we have a in memory value we can change in the debugger
* to begin booting in NOR Flash
*/
static volatile uint32_t wait = NOR_BOOT_MODE;
printf("Configuring NOR FLASH on CS0 and %s\n", wait ? "waiting" : "booting");
/* Make sure that the SMC peripheral is enabled (But of course it is... we
* are executing from NOR FLASH now).
*/
sam_hsmc_enableclk();
/* The SAMA5D3x-EK has 118MB of 16-bit NOR FLASH at CS0. The NOR FLASH
* has already been configured by the first level ROM bootloader... we
* simply need to modify the timing here.
*/
regval = HSMC_SETUP_NWE_SETUP(1) | HSMC_SETUP_NCS_WRSETUP(0) |
HSMC_SETUP_NRD_SETUP(2) | HSMC_SETUP_NCS_RDSETUP(0);
putreg32(regval, SAM_HSMC_SETUP(HSMC_CS0));
regval = HSMC_PULSE_NWE_PULSE(10) | HSMC_PULSE_NCS_WRPULSE(10) |
HSMC_PULSE_NRD_PULSE(11) | HSMC_PULSE_NCS_RDPULSE(11);
putreg32(regval, SAM_HSMC_PULSE(HSMC_CS0));
regval = HSMC_CYCLE_NWE_CYCLE(11) | HSMC_CYCLE_NRD_CYCLE(14);
putreg32(regval, SAM_HSMC_CYCLE(HSMC_CS0));
regval = HSMC_TIMINGS_TCLR(0) | HSMC_TIMINGS_TADL(0) |
HSMC_TIMINGS_TAR(0) | HSMC_TIMINGS_TRR(0) |
HSMC_TIMINGS_TWB(0) | HSMC_TIMINGS_RBNSEL(0);
putreg32(regval, SAM_HSMC_TIMINGS(HSMC_CS0));
regval = HSMC_MODE_READMODE | HSMC_MODE_WRITEMODE |
HSMC_MODE_EXNWMODE_DISABLED | HSMC_MODE_BIT_16 |
HSMC_MODE_TDFCYCLES(1);
putreg32(regval, SAM_HSMC_MODE(HSMC_CS0));
/* Interrupts must be disabled through the following. In this configuration,
* there should only be timer interrupts. Your NuttX configuration must use
* CONFIG_SERIAL_LOWCONSOLE=y or printf() will hang when the interrupts
* are disabled!
*/
(void)irqsave();
/* Disable MATRIX write protection */
#if 0 /* Disabled on reset */
putreg32(MATRIX_WPMR_WPKEY, SAM_MATRIX_WPMR);
#endif
/* Set remap state 1.
*
* Boot state: ROM is seen at address 0x00000000
* Remap State 0: SRAM is seen at address 0x00000000 (through AHB slave
* interface) instead of ROM.
* Remap State 1: HEBI is seen at address 0x00000000 (through AHB slave
* interface) instead of ROM for external boot.
*
* REVISIT: This does not work. No matter what I do, the internal
* SRAM is always visible at address zero. I am missing something.
*/
putreg32(MATRIX_MRCR_RCB0, SAM_MATRIX_MRCR); /* Enable remap */
putreg32(AXIMX_REMAP_REMAP1, SAM_AXIMX_REMAP); /* Remap HEBI */
/* Restore MATRIX write protection */
#if 0 /* Disabled on reset */
putreg32(MATRIX_WPMR_WPKEY | MATRIX_WPMR_WPEN, SAM_MATRIX_WPMR);
#endif
/* Disable the caches and the MMU. Disabling the MMU should be safe here
* because there is a 1-to-1 identity mapping between the physical and
* virtual addressing.
*/
/* NOTE: This generates crashes and lots of error, but does leave the
* system in the proper state to run from NOR: very ugly but usable.
* Better than the alternative.
*/
cp15_disable_mmu();
cp15_disable_caches();
/* Invalidate caches and TLBs */
arch_invalidate_icache();
arch_invalidate_dcache_all();
cp15_invalidate_tlbs();
/* Then jump into NOR flash */
while (wait)
{
}
NOR_ENTRY();
return 0; /* We should not get here in either case */
}