//*****************************************************************************
//
//! Configures the controls of the selected memory buffer.
//!
//! \param baseAddress is the base address of the ADC12 module.
//! \param memoryBufferControlIndex is the selected memory buffer to set the
//! configuration for.
//! Valid values are
//! \b ADC12_MEMORY_0 [Default]
//! \b ADC12_MEMORY_1
//! \b ADC12_MEMORY_2
//! \b ADC12_MEMORY_3
//! \b ADC12_MEMORY_4
//! \b ADC12_MEMORY_5
//! \b ADC12_MEMORY_6
//! \b ADC12_MEMORY_7
//! \b ADC12_MEMORY_8
//! \b ADC12_MEMORY_9
//! \b ADC12_MEMORY_10
//! \b ADC12_MEMORY_11
//! \b ADC12_MEMORY_12
//! \b ADC12_MEMORY_13
//! \b ADC12_MEMORY_14
//! \b ADC12_MEMORY_15
//! \param inputSourceSelect is the input that will store the converted data
//! into the specified memory buffer.
//! Valid values are
//! \b ADC12_INPUT_A0 [Default]
//! \b ADC12_INPUT_A1
//! \b ADC12_INPUT_A2
//! \b ADC12_INPUT_A3
//! \b ADC12_INPUT_A4
//! \b ADC12_INPUT_A5
//! \b ADC12_INPUT_A6
//! \b ADC12_INPUT_A7
//! \b ADC12_INPUT_A8
//! \b ADC12_INPUT_A9
//! \b ADC12_INPUT_TEMPSENSOR
//! \b ADC12_INPUT_BATTERYMONITOR
//! \b ADC12_INPUT_A12
//! \b ADC12_INPUT_A13
//! \b ADC12_INPUT_A14
//! \b ADC12_INPUT_A15
//! Modified bits are \b ADC12INCHx of \b ADC12MCTLx register.
//! \param positiveRefVoltageSourceSelect is the reference voltage source to set
//! as the upper limit for the conversion stored in the specified memory.
//! Valid values are
//! \b ADC12_VREFPOS_AVCC [Default]
//! \b ADC12_VREFPOS_EXT
//! \b ADC12_VREFPOS_INT
//! Modified bits are \b ADC12SREF of \b ADC12MCTLx register.
//! \param negativeRefVoltageSourceSelect is the reference voltage source to set
//! as the lower limit for the conversion stored in the specified memory.
//! Valid values are
//! \b ADC12_VREFNEG_AVSS [Default]
//! \b ADC12_VREFNEG_EXT
//! Modified bits are \b ADC12SREF of \b ADC12MCTLx register.
//! \param endOfSequence indicates that the specified memory buffer will be
//! the end of the sequence if a sequenced conversion mode is selected
//! Valid values are
//! \b ADC12_NOTENDOFSEQUENCE - The specified memory buffer will NOT be the
//! end of the sequence OR a sequenced conversion mode is not
//! selected. [Default]
//! \b ADC12_ENDOFSEQUENCE - The specified memory buffer will be the end
//! of the sequence.
//! Modified bits are \b ADC12EOS of \b ADC12MCTLx register.
//!
//! Maps an input signal conversion into the selected memory buffer, as
//! well as the positive and negative reference voltages for each conversion
//! being stored into this memory buffer. If the internal reference is used for
//! the positive reference voltage, the internal REF module must be used to
//! control the voltage level. Note that if a conversion has been started with
//! the startConversion() function, then a call to disableConversions() is
//! required before this function may be called.
//!
//! \return NONE
//
//*****************************************************************************
void ADC12_memoryConfigure (unsigned int baseAddress,
unsigned char memoryBufferControlIndex,
unsigned char inputSourceSelect,
unsigned char positiveRefVoltageSourceSelect,
unsigned char negativeRefVoltageSourceSelect,
unsigned short endOfSequence)
{
//Make sure the ENC bit is cleared before configuring a Memory Buffer Control
ASSERT( !(HWREGB(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) );
ASSERT(memoryBufferControlIndex <= ADC12_MEMORY_15);
ASSERT(inputSourceSelect <= ADC12_INPUT_A15);
ASSERT(positiveRefVoltageSourceSelect <= ADC12_VREFPOS_INT);
ASSERT(negativeRefVoltageSourceSelect <= ADC12_VREFNEG_EXT);
//Set the offset in respect to ADC12MCTL0
unsigned int memoryBufferControlOffset =
(OFS_ADC12MCTL0 + memoryBufferControlIndex);
//Reset the memory buffer control and Set the input source
HWREGB(baseAddress + memoryBufferControlOffset) =
inputSourceSelect //Set Input Source
+ positiveRefVoltageSourceSelect //Set Vref+
+ negativeRefVoltageSourceSelect //Set Vref-
+ endOfSequence; //Set End of Sequence
}
//*****************************************************************************
//
//! Erase a single bank of the flash memory.
//!
//! \param baseAddress is the base address of the Flash module.
//! \param Flash_ptr is a pointer into the bank to be erased
//!
//! \returns NONE
//
//*****************************************************************************
void Flash_bankErase (unsigned int baseAddress, unsigned char *Flash_ptr)
{
//5xx Workaround: Disable global interrupt while erasing.
//local variable to store GIE status
unsigned int gieStatus;
//Store current SR register
gieStatus = __get_SR_register() & GIE;
//Disable global interrupt
__disable_interrupt();
//Clear Lock bit
HWREG(baseAddress + OFS_FCTL3) = FWKEY;
while (HWREGB(baseAddress + OFS_FCTL3) & BUSY) ;
//Set MERAS bit
HWREG(baseAddress + OFS_FCTL1) = FWKEY + MERAS;
//Dummy write to erase Flash seg
*Flash_ptr = 0;
//test busy
while (HWREGB(baseAddress + OFS_FCTL3) & BUSY) ;
//Clear WRT bit
HWREG(baseAddress + OFS_FCTL1) = FWKEY;
//Set LOCK bit
HWREG(baseAddress + OFS_FCTL3) = FWKEY + LOCK;
//Reinstate SR register
__bis_SR_register(gieStatus);
}
//*****************************************************************************
//
//! Use to set the reference buffer's sampling rate.
//!
//! \param baseAddress is the base address of the ADC12 module.
//! \param samplingRateSelect is the specified maximum sampling rate.
//! Valid values are
//! \b ADC12_MAXSAMPLINGRATE_200KSPS [Default]
//! \b ADC12_MAXSAMPLINGRATE_50KSPS
//! Modified bits are \b ADC12SR of \b ADC12CTL2 register.
//!
//! Sets the reference buffer's sampling rate to the selected sampling rate. The
//! default sampling rate is maximum of 200-ksps, and can be reduced to a
//! maximum of 50-ksps to conserve power.
//!
//! \return NONE
//
//*****************************************************************************
void ADC12_setReferenceBufferSamplingRate (unsigned int baseAddress,
unsigned short samplingRateSelect)
{
ASSERT(samplingRateSelect <= ADC12_MAXSAMPLINGRATE_50KSPS);
HWREGB(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12SR);
HWREGB(baseAddress + OFS_ADC12CTL2_L) |= samplingRateSelect;
}
//*****************************************************************************
//
//! Use to set the read-back format of the converted data.
//!
//! \param baseAddress is the base address of the ADC12 module.
//! \param readBackFormat is the specified format to store the conversions in
//! the memory buffer.
//! Valid values are
//! \b ADC12_UNSIGNED_BINARY [Default]
//! \b ADC12_SIGNED_2SCOMPLEMENT
//! Modified bits are \b ADC12DF of \b ADC12CTL2 register.
//!
//! Sets the format of the converted data: how it will be stored into the
//! memory buffer, and how it should be read back. The format can be set as
//! right-justified (default), which indicates that the number will be unsigned,
//! or left-justified, which indicates that the number will be signed in
//! 2's complement format. This change affects all memory buffers for subsequent
//! conversions.
//!
//! \return NONE
//
//*****************************************************************************
void ADC12_setDataReadBackFormat (unsigned int baseAddress,
unsigned short readBackFormat)
{
ASSERT(readBackFormat <= ADC12_SIGNED_2SCOMPLEMENT);
HWREGB(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12DF);
HWREGB(baseAddress + OFS_ADC12CTL2_L) |= readBackFormat;
}
//*****************************************************************************
//
//! Use to change the resolution of the converted data.
//!
//! \param baseAddress is the base address of the ADC12 module.
//! \param resolutionSelect determines the resolution of the converted data.
//! Valid values are
//! \b ADC12_RESOLUTION_8BIT
//! \b ADC12_RESOLUTION_10BIT
//! \b ADC12_RESOLUTION_12BIT [Default]
//! Modified bits are \b ADC12RESx of \b ADC12CTL2 register.
//!
//! This function can be used to change the resolution of the converted data
//! from the default of 12-bits.
//!
//! \return NONE
//
//*****************************************************************************
void ADC12_setResolution (unsigned int baseAddress,
unsigned char resolutionSelect)
{
ASSERT(resolutionSelect <= ADC12_RESOLUTION_12BIT);
HWREGB(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12RES_3);
HWREGB(baseAddress + OFS_ADC12CTL2_L) |= resolutionSelect;
}
//*****************************************************************************
//
//! Transmits the next byte to be transmitted marked as address depending on
//! selected multiprocessor mode
//!
//! \param baseAddress is the base address of the UART module.
//! \param transmitAddress is the next byte to be transmitted
//!
//! Modified register is \b UCAxCTL1, \b UCAxTXBUF
//!
//! \return None.
//
//*****************************************************************************
void UART_transmitAddress (unsigned int baseAddress,
unsigned char transmitAddress)
{
//Set UCTXADDR bit
HWREGB(baseAddress + OFS_UCAxCTL1) |= UCTXADDR;
//Place next byte to be sent into the transmit buffer
HWREGB(baseAddress + OFS_UCAxTXBUF) = transmitAddress;
}
//*****************************************************************************
//
//! Disables the ADC from converting any more signals.
//!
//! \param baseAddress is the base address of the ADC12 module.
//! \param preempt specifies if the current conversion should be preemptly
//! stopped before the end of the conversion.
//! Valid values are
//! \b ADC12_COMPLETECONVERSION - Allows the ADC12 to end the current
//! conversion before disabling conversions.
//! \b ADC12_PREEMPTCONVERSION - Stops the ADC12 immediatly, with
//! unpredicatble results of the current conversion.
//!
//! Disables the ADC from converting any more signals.
//! If there is a conversion in progress, this function can stop it immediatly
//! if the preempt parameter is set as TRUE, by changing the conversion mode to
//! single-channel, single-conversion and disabling conversions. If the
//! conversion mode is set as single-channel, single-conversion and this
//! function is called without preemption, then the ADC core conversion status
//! is polled until the conversion is complete before disabling conversions to
//! prevent unpredictable data. If the ADC12_startConversion() has been called,
//! then this function has to be called to re-initialize the ADC, reconfigure a
//! memory buffer control, enable/disable the sampling pulse mode, or change the
//! internal reference voltage.
//!
//! Modified registers are \b ADC12CTL0 and \b ADC12CTL1.
//!
//! \return NONE
//
//*****************************************************************************
void ADC12_disableConversions (unsigned int baseAddress, unsigned short preempt)
{
if (ADC12_PREEMPTCONVERSION == preempt){
HWREGB(baseAddress + OFS_ADC12CTL1_L) &= ~(ADC12CONSEQ_3);
//Reset conversion sequence mode to single-channel, single-conversion
} else if (~(HWREGB(baseAddress + OFS_ADC12CTL1_L) & ADC12CONSEQ_3)){
//To prevent preemoption of a single-channel, single-conversion we must
//wait for the ADC core to finish the conversion.
while (ADC12_isBusy(baseAddress)) ;
}
HWREGB(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC);
}
//*****************************************************************************
//
//! Initializes the SD24B Module
//!
//! \param baseAddress is the base address of the SD24B module.
//! \param clockSourceSelect selects the clock that will be used as the SD24B
//! core
//! Valid values are
//! \b SD24B_CLOCKSOURCE_MCLK [Default]
//! \b SD24B_CLOCKSOURCE_SMCLK
//! \b SD24B_CLOCKSOURCE_ACLK
//! \b SD24B_CLOCKSOURCE_SD24CLK
//! Modified bits are \b SD24SSEL of \b SD24BCTL0 register.
//! \param clockPreDivider selects the amount that the clock will be predivided
//! Valid values are
//! \b SD24B_PRECLOCKDIVIDER_1 [Default]
//! \b SD24B_PRECLOCKDIVIDER_2
//! \b SD24B_PRECLOCKDIVIDER_4
//! \b SD24B_PRECLOCKDIVIDER_8
//! \b SD24B_PRECLOCKDIVIDER_16
//! \b SD24B_PRECLOCKDIVIDER_32
//! \b SD24B_PRECLOCKDIVIDER_64
//! \b SD24B_PRECLOCKDIVIDER_128
//! Modified bits are \b SD24PDIVx of \b SD24BCTL0 register.
//! \param clockDivider selects the amount that the clock will be divided.
//! Valid values are
//! \b SD24B_CLOCKDIVIDER_1 [Default]
//! \b SD24B_CLOCKDIVIDER_2
//! \b SD24B_CLOCKDIVIDER_3
//! \b SD24B_CLOCKDIVIDER_4
//! \b SD24B_CLOCKDIVIDER_5
//! \b SD24B_CLOCKDIVIDER_6
//! \b SD24B_CLOCKDIVIDER_7
//! \b SD24B_CLOCKDIVIDER_8
//! \b SD24B_CLOCKDIVIDER_9
//! \b SD24B_CLOCKDIVIDER_10
//! \b SD24B_CLOCKDIVIDER_11
//! \b SD24B_CLOCKDIVIDER_12
//! \b SD24B_CLOCKDIVIDER_13
//! \b SD24B_CLOCKDIVIDER_14
//! \b SD24B_CLOCKDIVIDER_15
//! \b SD24B_CLOCKDIVIDER_16
//! \b SD24B_CLOCKDIVIDER_17
//! \b SD24B_CLOCKDIVIDER_18
//! \b SD24B_CLOCKDIVIDER_19
//! \b SD24B_CLOCKDIVIDER_20
//! \b SD24B_CLOCKDIVIDER_21
//! \b SD24B_CLOCKDIVIDER_22
//! \b SD24B_CLOCKDIVIDER_23
//! \b SD24B_CLOCKDIVIDER_24
//! \b SD24B_CLOCKDIVIDER_25
//! \b SD24B_CLOCKDIVIDER_26
//! \b SD24B_CLOCKDIVIDER_27
//! \b SD24B_CLOCKDIVIDER_28
//! \b SD24B_CLOCKDIVIDER_29
//! \b SD24B_CLOCKDIVIDER_30
//! \b SD24B_CLOCKDIVIDER_31
//! \b SD24B_CLOCKDIVIDER_32
//! Modified bits are \b SD24DIVx of \b SD24BCTL0 register.
//! \param referenceSelect selects the reference source for the SD24B core
//! Valid values are
//! \b SD24B_REF_EXTERNAL [Default]
//! \b SD24B_REF_INTERNAL
//! Modified bits are \b SD24REFS of \b SD24BCTL0 register.
//!
//! This function initializes the SD24B module sigma-delta analog-to-digital
//! conversions. Specifically the function sets up the clock source for the
//! SD24B core to use for conversions. Upon completion of the initialization
//! the SD24B interrupt registers will be reset and the given parameters will
//! be set. The converter configuration settings are independent of this function.
//! The values you choose for the clock divider and predivider are used to
//! determine the effective clock frequency. The formula used is:
//! f_sd24 = f_clk /(divider * predivider)
//!
//! \return none
//
//*****************************************************************************
void SD24B_init(unsigned int baseAddress,
unsigned char clockSourceSelect,
unsigned char clockPreDivider,
unsigned char clockDivider,
unsigned char referenceSelect )
{
assert(
(SD24B_CLOCKSOURCE_MCLK == clockSourceSelect) ||
(SD24B_CLOCKSOURCE_SMCLK == clockSourceSelect) ||
(SD24B_CLOCKSOURCE_ACLK == clockSourceSelect) ||
(SD24B_CLOCKSOURCE_SD24CLK == clockSourceSelect)
);
assert(
(SD24B_REF_EXTERNAL == referenceSelect) ||
(SD24B_REF_INTERNAL == referenceSelect)
);
// Reset all interrupts and flags
HWREG(baseAddress + OFS_SD24BIE) &= 0x0000; //Reset ALL interrupt enables
HWREG(baseAddress + OFS_SD24BIFG) &= 0x0000; //Reset ALL interrupt flags
HWREG(baseAddress + OFS_SD24BTRGCTL) &= ~(SD24TRGIE | SD24TRGIFG);
// Turn off all group conversions
HWREG(baseAddress + OFS_SD24BCTL1) &= ~(SD24GRP0SC | SD24GRP1SC
| SD24GRP2SC | SD24GRP3SC);
// Configure SD24_B
HWREG(baseAddress + OFS_SD24BCTL0) &= ~((SD24DIV4 | SD24DIV3 | SD24DIV2
| SD24DIV1 | SD24DIV0) | SD24PDIV_7 | SD24SSEL_3 | SD24REFS);
HWREGB(baseAddress + OFS_SD24BCTL0) |= (clockSourceSelect | clockPreDivider
| clockDivider | referenceSelect);
return;
}
//*****************************************************************************
//
//! Write data into the flash memory in byte format.
//!
//! \param baseAddress is the base address of the Flash module.
//! \param Data_ptr is the pointer to the data to be written
//! \param Flash_ptr is the pointer into which to write the data
//! \param numberOfBytes is the number of bytes to be written
//!
//! \returns NONE
//
//*****************************************************************************
void Flash_write8 (unsigned int baseAddress,
unsigned char *Data_ptr,
unsigned char *Flash_ptr,
unsigned int numberOfBytes
)
{
//Clear Lock bit
HWREG(baseAddress + OFS_FCTL3) = FWKEY;
//Enable byte/word write mode
HWREG(baseAddress + OFS_FCTL1) = FWKEY + WRT;
while (numberOfBytes > 0)
{
//test busy
while (HWREGB(baseAddress + OFS_FCTL3) & BUSY) ;
//Write to Flash
*Flash_ptr++ = *Data_ptr++;
numberOfBytes--;
}
//Clear write bit
HWREG(baseAddress + OFS_FCTL1) = FWKEY;
//Set LOCK bit
HWREG(baseAddress + OFS_FCTL3) = FWKEY + LOCK;
}
//*****************************************************************************
//
//! Write data into the flash memory in long format, pass by reference
//!
//! \param baseAddress is the base address of the Flash module.
//! \param Data_ptr is the pointer to the data to be written
//! \param Flash_ptr is the pointer into which to write the data
//! \param numberOfBytes is the number of bytes to be written
//!
//! \returns NONE
//
//*****************************************************************************
void Flash_write32 (unsigned int baseAddress,
unsigned long *Data_ptr,
unsigned long *Flash_ptr,
unsigned int numberOfBytes
)
{
//Clear Lock bit
HWREG(baseAddress + OFS_FCTL3) = FWKEY;
//Enable long-word write
HWREG(baseAddress + OFS_FCTL1) = FWKEY + BLKWRT;
while (numberOfBytes > 0)
{
//test busy
while (HWREGB(baseAddress + OFS_FCTL3) & BUSY) ;
//Write to Flash
*Flash_ptr++ = *Data_ptr++;
numberOfBytes--;
}
//Clear Erase bit
HWREG(baseAddress + OFS_FCTL1) = FWKEY;
//Set LOCK bit
HWREG(baseAddress + OFS_FCTL3) = FWKEY + LOCK;
}
//*****************************************************************************
//
//! Disables Sampling Timer Pulse Mode.
//!
//! \param baseAddress is the base address of the ADC12 module.
//!
//! Disables the Sampling Timer Pulse Mode. Note that if a conversion has been
//! started with the startConversion() function, then a call to
//! disableConversions() is required before this function may be called.
//!
//! Modified bits are \b ADC12SHP of \b ADC12CTL0 register.
//! \return NONE
//
//*****************************************************************************
void ADC12_disableSamplingTimer (unsigned int baseAddress)
{
//Make sure the ENC bit is cleared before disabling sampling pulse mode
ASSERT( !(HWREGB(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) );
HWREG(baseAddress + OFS_ADC12CTL1) &= ~(ADC12SHP);
}
//*****************************************************************************
//
//! Write data into the flash memory in long format, pass by value
//!
//! \param baseAddress is the base address of the Flash module.
//! \param Data_ptr is the pointer to the data to be written
//! \param Flash_ptr is the pointer into which to write the data
//! \param numberOfBytes is the number of bytes to be written
//!
//! \returns NONE
//
//*****************************************************************************
void Flash_memoryFill32 (unsigned int baseAddress,
unsigned long value,
unsigned long *Flash_ptr,
unsigned int count
)
{
//Clear Lock bit
HWREG(baseAddress + OFS_FCTL3) = FWKEY;
//Enable long-word write
HWREG(baseAddress + OFS_FCTL1) = FWKEY + BLKWRT;
//test busy
while (count > 0)
{
while ((HWREGB(baseAddress + OFS_FCTL3)) & BUSY) ;
//Write to Flash
*Flash_ptr++ = value;
count--;
}
//Clear Erase bit
HWREG(baseAddress + OFS_FCTL1) = FWKEY;
//Set LOCK bit
HWREG(baseAddress + OFS_FCTL3) = FWKEY + LOCK;
}
//*****************************************************************************
//
//! Initializes the ADC12 Module.
//!
//! \param baseAddress is the base address of the ADC12 module.
//! \param sampleHoldSignalSourceSelect is the signal that will trigger a
//! sample-and-hold for an input signal to be converted.
//! Valid values are
//! \b ADC12_SAMPLEHOLDSOURCE_SC [Default]
//! \b ADC12_SAMPLEHOLDSOURCE_1
//! \b ADC12_SAMPLEHOLDSOURCE_2
//! \b ADC12_SAMPLEHOLDSOURCE_3
//! This parameter is device specific and sources should be found in the
//! device's datasheet.
//! Modified bits are \b ADC12SHSx of \b ADC12CTL1 register.
//! \param clockSourceSelect selects the clock that will be used by the ADC12
//! core, and the sampling timer if a sampling pulse mode is enabled.
//! Valid values are
//! \b ADC12_CLOCKSOURCE_ADC12OSC - MODOSC 5 MHz oscillator from the UCS
//! [Default]
//! \b ADC12_CLOCKSOURCE_ACLK - The Auxilary Clock
//! \b ADC12_CLOCKSOURCE_MCLK - The Master Clock
//! \b ADC12_CLOCKSOURCE_SMCLK - The Sub-Master Clock
//! Modified bits are \b ADC12SSELx of \b ADC12CTL1 register.
//! \param clockSourceDivider selects the amount that the clock will be divided.
//! Valid values are
//! \b ADC12_CLOCKDIVIDER_1 [Default]
//! \b ADC12_CLOCKDIVIDER_2
//! \b ADC12_CLOCKDIVIDER_3
//! \b ADC12_CLOCKDIVIDER_4
//! \b ADC12_CLOCKDIVIDER_5
//! \b ADC12_CLOCKDIVIDER_6
//! \b ADC12_CLOCKDIVIDER_7
//! \b ADC12_CLOCKDIVIDER_8
//! \b ADC12_CLOCKDIVIDER_12
//! \b ADC12_CLOCKDIVIDER_16
//! \b ADC12_CLOCKDIVIDER_20
//! \b ADC12_CLOCKDIVIDER_24
//! \b ADC12_CLOCKDIVIDER_28
//! \b ADC12_CLOCKDIVIDER_32
//! Modified bits are \b ADC12DIVx of \b ADC12CTL1 register and
//! \b ADC12PDIV of \b ADC12CTL2 register.
//!
//! This function initializes the ADC module to allow for analog-to-digital
//! conversions. Specifically this function sets up the sample-and-hold signal
//! and clock sources for the ADC core to use for conversions. Upon successful
//! completion of the initialization all of the ADC control registers will be
//! reset, excluding the memory controls and reference module bits, the given
//! parameters will be set, and the ADC core will be turned on (Note, that the
//! ADC core only draws power during conversions and remains off when not
//! converting).Note that sample/hold signal sources are device dependent. Note
//! that if re-initializing the ADC after starting a conversion with the
//! startConversion() function, the disableConversion() must be called BEFORE
//! this function can be called.
//!
//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process.
//
//*****************************************************************************
unsigned short ADC12_init (unsigned int baseAddress,
unsigned int sampleHoldSignalSourceSelect,
unsigned char clockSourceSelect,
unsigned int clockSourceDivider)
{
//Make sure the ENC bit is cleared before initializing the ADC12
ASSERT( !(HWREGB(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) );
ASSERT(sampleHoldSignalSourceSelect <= ADC12_SAMPLEHOLDSOURCE_3);
ASSERT(clockSourceSelect <= ADC12_CLOCKSOURCE_SMCLK);
ASSERT(clockSourceDivider <= ADC12_CLOCKDIVIDER_32);
unsigned char retVal = STATUS_SUCCESS;
//Turn OFF ADC10 Module & Clear Interrupt Registers
HWREG(baseAddress + OFS_ADC12CTL0) &= ~(ADC12ON + ADC12OVIE + ADC12TOVIE
+ ADC12ENC + ADC12SC);
HWREG(baseAddress + OFS_ADC12IE) &= 0x0000; //Reset ALL interrupt enables
HWREG(baseAddress + OFS_ADC12IFG) &= 0x0000; //Reset ALL interrupt flags
//Set ADC12 Control 1
HWREG(baseAddress + OFS_ADC12CTL1) =
sampleHoldSignalSourceSelect //Setup the Sample-and-Hold Source
+ (clockSourceDivider & ADC12DIV_7) //Set Clock Divider
+ clockSourceSelect; //Setup Clock Source
//Set ADC12 Control 2
HWREG(baseAddress + OFS_ADC12CTL2) =
(clockSourceDivider & ADC12PDIV) //Set Clock Pre-Divider
+ ADC12RES_2; //Default resolution to 12-bits
return ( retVal) ;
}
void isr_uart_for_keyboard(unsigned int intNum){
unsigned int baseaddr = modulelist[intNum].baseAddr;
if(UARTIntPendingStatusGet(baseaddr) == UART_N0_INT_PENDING)
return;
unsigned int intval = UARTIntIdentityGet(baseaddr);
if (intval == UART_INTID_RX_THRES_REACH) {
for (int i=0;i<8;i++) {
volatile unsigned char tempval = HWREGB(baseaddr+UART_RHR);
((unsigned char *)&keyTouchpadMsg)[i] = tempval;
//UARTPutc(tempval);
}
if (isKeyTouchEvent(&keyTouchpadMsg)) {
if(keyTouchpadMsg.type & MSG_TYPE_KEY){
g_keycode = keyCode(keyTouchpadMsg.keycode);
atomicSet(&g_keyPushed);
if(keyhandler!=NULL)
keyhandler(g_keycode);
}
if (keyTouchpadMsg.type & MSG_TYPE_TOUCH) {
g_ts.x = g_tsRaw.x = keyTouchpadMsg.tscval & 0xffff;
g_ts.y = g_tsRaw.y = keyTouchpadMsg.tscval >>16;
ts_linear(&tsCalibration, (int *)&g_ts.x, (int *)&g_ts.y);
atomicSet(&g_touched);
}
if (keyTouchpadMsg.type & MSG_TYPE_KEYRESET) {
atomicSet(&g_keyRest);
}
}
}
//*****************************************************************************
//
//! Enables/Starts an Analog-to-Digital Conversion.
//!
//! \param baseAddress is the base address of the ADC12 module.
//! \param startingMemoryBufferIndex is the memory buffer that will hold the
//! first or only conversion.
//! Valid values are
//! \b ADC12_MEMORY_0 [Default]
//! \b ADC12_MEMORY_1
//! \b ADC12_MEMORY_2
//! \b ADC12_MEMORY_3
//! \b ADC12_MEMORY_4
//! \b ADC12_MEMORY_5
//! \b ADC12_MEMORY_6
//! \b ADC12_MEMORY_7
//! \b ADC12_MEMORY_8
//! \b ADC12_MEMORY_9
//! \b ADC12_MEMORY_10
//! \b ADC12_MEMORY_11
//! \b ADC12_MEMORY_12
//! \b ADC12_MEMORY_13
//! \b ADC12_MEMORY_14
//! \b ADC12_MEMORY_15
//! Modified bits are \b ADC12STARTADDx of \b ADC12CTL1 register.
//! \param conversionSequenceModeSelect determines the ADC operating mode.
//! Valid values are
//! \b ADC12_SINGLECHANNEL - one-time conversion of a single channel into
//! a single memory buffer. [Default]
//! \b ADC12_SEQOFCHANNELS - one time conversion of multiple channels
//! into the specified starting memory buffer and each subsequent
//! memory buffer up until the conversion is stored in a memory buffer
//! dedicated as the end-of-sequence by the memory's control register.
//! \b ADC12_REPEATED_SINGLECHANNEL - repeated conversions of one channel
//! into a single memory buffer.
//! \b ADC12_REPEATED_SEQOFCHANNELS - repeated conversions of multiple
//! channels into the specified starting memory buffer and each
//! subsequent memory buffer up until the conversion is stored in a
//! memory buffer dedicated as the end-of-sequence by the memory's
//! control register.
//! Modified bits are \b ADC12CONSEQx of \b ADC12CTL1 register.
//!
//! This function enables/starts the conversion process of the ADC.
//! If the sample/hold signal source chosen during initialization was
//! ADC12OSC, then the conversion is started immediately, otherwise the chosen
//! sample/hold signal source starts the conversion by a rising edge of the
//! signal. Keep in mind when selecting conversion modes, that for sequenced
//! and/or repeated modes, to keep the sample/hold-and-convert process
//! continuing without a trigger from the sample/hold signal source, the
//! multiple samples must be enabled using the ADC12_setupSamplingTimer()
//! function. Note that after this function is called, the
//! ADC12_stopConversions() has to be called to re-initialize the ADC,
//! reconfigure a memory buffer control, enable/disable the sampling timer, or
//! to change the internal reference voltage.
//!
//! Modified registers are \b ADC12CTL0 and \b ADC12CTL1.
//! \return NONE
//
//*****************************************************************************
void ADC12_startConversion (unsigned int baseAddress,
unsigned int startingMemoryBufferIndex,
unsigned char conversionSequenceModeSelect)
{
ASSERT(startingMemoryBufferIndex <= ADC12_MEMORY_15);
ASSERT(conversionSequenceModeSelect <= ADC12_REPEATED_SEQOFCHANNELS);
//Reset the ENC bit to set the starting memory address and conversion mode
//sequence
HWREGB(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC);
//Reset the bits about to be set
HWREG(baseAddress + OFS_ADC12CTL0) &= ~(ADC12CSTARTADD_15 + ADC12CONSEQ_3);
HWREGB(baseAddress + OFS_ADC12CTL1_H) |= (startingMemoryBufferIndex << 4);
HWREGB(baseAddress + OFS_ADC12CTL1_L) |= conversionSequenceModeSelect;
HWREGB(baseAddress + OFS_ADC12CTL0_L) |= ADC12ENC + ADC12SC;
}
//*****************************************************************************
//
//! Transmit break. Transmits a break with the next write to the transmit
//! buffer. In UART mode with automatic baud-rate detection,
//! UART_AUTOMATICBAUDRATE_SYNC(0x55) must be written into UCAxTXBUF to
//! generate the required break/synch fields.
//! Otherwise, DEFAULT_SYNC(0x00) must be written into the transmit buffer.
//! Also ensures module is ready for transmitting the next data
//!
//! \param baseAddress is the base address of the UART module.
//!
//! Modified register is \b UCAxCTL1, \b UCAxTXBUF
//!
//! \return None.
//
//*****************************************************************************
void UART_transmitBreak (unsigned int baseAddress)
{
//Set UCTXADDR bit
HWREGB(baseAddress + OFS_UCAxCTL1) |= UCTXBRK;
//If current mode is automatic baud-rate detection
if (UART_AUTOMATIC_BAUDRATE_DETECTION_MODE ==
(HWREGB(baseAddress + OFS_UCAxCTL0) &
UART_AUTOMATIC_BAUDRATE_DETECTION_MODE)){
HWREGB(baseAddress + OFS_UCAxTXBUF) = UART_AUTOMATICBAUDRATE_SYNC;
} else {
HWREGB(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC;
}
//USCI TX buffer ready?
while (!UART_getInterruptStatus(baseAddress, UCTXIFG)) ;
}
//*****************************************************************************
//
//! Returns the busy status of the ADC12 core.
//!
//! \param baseAddress is the base address of the ADC12 module.
//!
//! Returns the status of the ADC core if there is a conversion currently taking
//! place.
//!
//! \return ADC12_BUSY or ADC12_NOTBUSY dependent if there is a conversion
//! currently taking place.
//
//*****************************************************************************
unsigned short ADC12_isBusy (unsigned int baseAddress)
{
if (HWREGB(baseAddress + OFS_ADC12CTL1_L) & ADC12BUSY){
return ( ADC12_BUSY) ;
} else {
return ( ADC12_NOTBUSY) ;
}
}
//*****************************************************************************
//
// Check to determine whether or not the flash appears to be present. We do
// this by attempting to read the first 3 bytes of the CFI Query Identification
// String which should contain "QRY". If we get this, we assume all is well,
// otherwise we assume the flash is not accessible.
//
//*****************************************************************************
static tBoolean
CheckFlashPresent(void)
{
tBoolean bRetcode;
//
// Set autoselect mode
//
HWREGB(EXT_FLASH_BASE + 0xAAA) = 0xAA;
HWREGB(EXT_FLASH_BASE + 0x555) = 0x55;
HWREGB(EXT_FLASH_BASE + 0xAAA) = 0x90;
//
// Set CFI query
//
HWREGB(EXT_FLASH_BASE + 0xAA) = 0x98;
//
// Check that the query string is returned correctly.
//
if((HWREGB(EXT_FLASH_BASE + 0x20) != 'Q') ||
(HWREGB(EXT_FLASH_BASE + 0x22) != 'R') ||
(HWREGB(EXT_FLASH_BASE + 0x24) != 'Y'))
{
//
// We can't access the flash correctly - the query string was not
// read as expected.
//
bRetcode = false;
}
else
{
//
// We read the query string so tell the caller all is well.
//
bRetcode = true;
}
//
// Return to read array mode. We need to do this twice. The first write
// gets us back to autoselect mode and the second returns us to array
// read.
//
HWREGB(EXT_FLASH_BASE) = 0xF0;
HWREGB(EXT_FLASH_BASE) = 0xF0;
//
// Tell the caller whether or not the flash is accessible.
//
return(bRetcode);
}
//*****************************************************************************
//
//! Gets the current UART interrupt status.
//!
//! \param baseAddress is the base address of the UART module.
//! \param mask is the masked interrupt flag status to be returned.
//!
//! This returns the interrupt status for the UART module based on which
//! flag is passed. mask parameter can be either any of the following
//! selection.
//! - \b UART_RECEIVE_INTERRUPT_FLAG -Receive interrupt flag
//! - \b UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag
//!
//! Modified register is \b UCAxIFG.
//!
//! \return The current interrupt status, returned as with the respective bits
//! set if the corresponding interrupt flag is set
//
//*****************************************************************************
unsigned char UART_getInterruptStatus (unsigned int baseAddress,
unsigned char mask)
{
ASSERT( (UART_RECEIVE_INTERRUPT_FLAG == mask) ||
(UART_TRANSMIT_INTERRUPT_FLAG == mask)
);
return ( HWREGB(baseAddress + OFS_UCAxIFG) & mask );
}
//*****************************************************************************
//
//! Use to invert or un-invert the sample/hold signal.
//!
//! \param baseAddress is the base address of the ADC12 module.
//! \param invertedSignal set if the sample/hold signal should be inverted
//! Valid values are
//! \b ADC12_NONINVERTEDSIGNAL - a sample-and-hold of an input signal for
//! conversion will be started on a rising edge of the
//! sample/hold signal. [Default]
//! \b ADC12_INVERTEDSIGNAL - a sample-and-hold of an input signal for
//! conversion will be started on a falling edge of the
//! sample/hold signal.
//! Modified bits are \b ADC12ISSH of \b ADC12CTL1 register.
//!
//! This function can be used to invert or un-invert the sample/hold signal.
//! Note that if a conversion has been started with the startConversion()
//! function, then a call to disableConversions() is required before this
//! function may be called.
//!
//! \return NONE
//
//*****************************************************************************
void ADC12_setSampleHoldSignalInversion (unsigned int baseAddress,
unsigned int invertedSignal)
{
//Make sure the ENC bit is cleared before using this function
ASSERT( !(HWREGB(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) );
HWREG(baseAddress + OFS_ADC12CTL1) &= ~(ADC12ISSH);
HWREG(baseAddress + OFS_ADC12CTL1) |= invertedSignal;
}
//*****************************************************************************
//
//! Disables individual UART interrupt sources.
//!
//! \param baseAddress is the base address of the UART module.
//! \param mask is the bit mask of the interrupt sources to be
//! disabled.
//!
//! Disables the indicated UART interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! The mask parameter is the logical OR of any of the following:
//! - \b UART_RECEIVE_INTERRUPT -Receive interrupt
//! - \b UART_TRANSMIT_INTERRUPT - Transmit interrupt
//! - \b UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive erroneous-character
//! interrupt enable
//! - \b UART_BREAKCHAR_INTERRUPT - Receive break character interrupt enable
//!
//! Modified register is \b UCAxIFG, \b UCAxIE and \b UCAxCTL1
//! \return None.
//
//*****************************************************************************
void UART_disableInterrupt (unsigned int baseAddress,
unsigned char mask
)
{
ASSERT((UART_RECEIVE_INTERRUPT == mask) ||
(UART_TRANSMIT_INTERRUPT == mask) ||
(UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT == mask) ||
(UART_BREAKCHAR_INTERRUPT == mask)
);
switch (mask){
case UART_RECEIVE_INTERRUPT:
case UART_TRANSMIT_INTERRUPT:
//Disable Interrupt
HWREGB(baseAddress + OFS_UCAxIE) &= ~mask;
break;
case UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT:
case UART_BREAKCHAR_INTERRUPT:
//Disable Interrupt
HWREGB(baseAddress + OFS_UCAxCTL1) &= ~mask;
break;
}
}
//*****************************************************************************
//
//! Set SD24B converter data format
//!
//! \param baseAddress is the base address of the SD24B module.
//! \param converter selects the converter that will be configured. Check
//! check datasheet for available converters on device.
//! Valid values are dependent on device, check datasheet
//! \b SD24B_CONVERTER_0
//! \b SD24B_CONVERTER_1
//! \b SD24B_CONVERTER_2
//! \b SD24B_CONVERTER_3
//! \b SD24B_CONVERTER_4
//! \b SD24B_CONVERTER_5
//! \b SD24B_CONVERTER_6
//! \b SD24B_CONVERTER_7
//! \param dataFormat selects how the data format of the results
//! Valid values are
//! \b SD24_DATA_FORMAT_BINARY [Default]
//! \b SD24_DATA_FORMAT_2COMPLEMENT
//! Modified bits are \b SD24DFx of \b SD24BCCTLx register.
//!
//! This function sets the converter format so that the resulting data can be
//! viewed in either binary or 2's complement.
//!
//! \return none
//
//*****************************************************************************
void SD24B_setConverterDataFormat(unsigned int baseAddress,
unsigned char converter,
unsigned char dataFormat) {
unsigned int address = baseAddress + (OFS_SD24BCCTL0_L +
(converter * 0x08));
assert(
(SD24B_CONVERTER_0 == converter) ||
(SD24B_CONVERTER_1 == converter) ||
(SD24B_CONVERTER_2 == converter) ||
(SD24B_CONVERTER_3 == converter) ||
(SD24B_CONVERTER_4 == converter) ||
(SD24B_CONVERTER_5 == converter) ||
(SD24B_CONVERTER_6 == converter) ||
(SD24B_CONVERTER_7 == converter)
);
// Clearing previous settings for configuration
HWREGB(address) &= ~(SD24DF0 | SD24DF1);
HWREGB(address) |= dataFormat;
}
//*****************************************************************************
//
//! Determines whether the last erase operation has completed.
//!
//! \param ulAddress is an address within the area of flash which was last
//! erased using a call to ExtFlashBlockErase() or any valid flash address if
//! ExtFlashChipErase() was last issued.
//! \param pbError is storage for the returned error indicator.
//!
//! This function determines whether the last flash erase operation has
//! completed. The address passed in parameter \e ulAddress must correspond to
//! an address in the region which was last erased. When the operation
//! completes, \b true is returned and the caller should check the value of
//! \e *pbError to determine whether or not the operation was successful. If
//! \e *pbError is \b true, an error was reported by the device and the flash
//! may not have been correctly erased. If \e *pbError is \b false, the
//! operation completed successfully.
//!
//! It is assumed that the EPI configuration has previously been set correctly
//! using a call to PinoutSet().
//!
//! \return Returns \b true if the erase operation completed or \b false if it
//! is still ongoing.
//
//*****************************************************************************
tBoolean
ExtFlashEraseIsComplete(unsigned long ulAddress, tBoolean *pbError)
{
//
// If reading the location returns 0xFF, the erase must be complete.
//
if(HWREGB(ulAddress) == 0xFF)
{
*pbError = false;
return(true);
}
else
{
//
// The erase is not complete so we look at the value read to determine
// whether an error occurred or not.
//
if(HWREGB(ulAddress) & FLASH_STATUS_ERROR)
{
//
// An error seems to have been reported. Check once more as
// indicated in the datasheet.
if(HWREGB(ulAddress) == 0xFF)
{
//
// False alarm - tell the caller the operation completed.
//
*pbError = false;
return(true);
}
else
{
//
// Looks as if the error was real so issue a Read/Reset to get
// the chip back into read mode and clear the error condition.
// then report the failure to the caller.
//
HWREGB(EXT_FLASH_BASE + 0xAAA) = 0xAA;
HWREGB(EXT_FLASH_BASE + 0x555) = 0x55;
HWREGB(EXT_FLASH_BASE) = 0xF0;
*pbError = true;
}
}
else
{
*pbError = false;
}
//
// If an error occurred, we return true so that any polling loop will
// exit. If no error occurred, the operation is not complete so we
// return false.
//
return(*pbError);
}
}
/**
* \brief This function will switch on the USB Phy
*
*
* \param None
*
* \return None
*
**/
void UsbPhyOn(unsigned int ulIndex)
{
unsigned int usbphycfg = 0;
#if defined (am335x_15x15) || defined(am335x) || defined(c6a811x)
ASSERT((0==ulIndex)||(1==ulIndex));
#else
ASSERT(0==ulIndex);
#endif /* defined (am335x_15x15) || ... */
#ifdef USB_MODE_FULLSPEED
if (0==ulIndex)
HWREGB(USB0_BASE + USB_O_POWER) &= 0xdf;
#if defined (am335x_15x15) || defined(am335x) || defined(c6a811x)
else
HWREGB(USB1_BASE + USB_O_POWER) &= 0xdf;
#endif /* defined (am335x_15x15) || ... */
#endif /* USB_MODE_HS_DISABLE */
usbphycfg = HWREG(g_USBInstance[ulIndex].uiPHYConfigRegAddr);
usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN);
usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN);
HWREG(g_USBInstance[ulIndex].uiPHYConfigRegAddr) = usbphycfg;
}
//*****************************************************************************
//
//! Enables individual UART interrupt sources.
//!
//! \param baseAddress is the base address of the UART module.
//! \param mask is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated UART interrupt sources. The interrupt flag is first
//! and then the corresponfing interrupt is enabled. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! The mask parameter is the logical OR of any of the following:
//! - \b UART_RECEIVE_INTERRUPT -Receive interrupt
//! - \b UART_TRANSMIT_INTERRUPT - Transmit interrupt
//! - \b UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive erroneous-character
//! interrupt enable
//! - \b UART_BREAKCHAR_INTERRUPT - Receive break character interrupt enable
//!
//! Modified register is \b UCAxIFG, \b UCAxIE and \b UCAxCTL1
//!
//! \return None.
//
//*****************************************************************************
void UART_enableInterrupt (unsigned int baseAddress,
unsigned char mask
)
{
ASSERT((UART_RECEIVE_INTERRUPT == mask) ||
(UART_TRANSMIT_INTERRUPT == mask) ||
(UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT == mask) ||
(UART_BREAKCHAR_INTERRUPT == mask)
);
switch (mask){
case UART_RECEIVE_INTERRUPT:
case UART_TRANSMIT_INTERRUPT:
//Clear interrupt flag
HWREG(baseAddress + OFS_UCAxIFG) &= ~(mask);
//Enable Interrupt
HWREGB(baseAddress + OFS_UCAxIE) |= mask;
break;
case UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT:
case UART_BREAKCHAR_INTERRUPT:
//Enable Interrupt
HWREGB(baseAddress + OFS_UCAxCTL1) |= mask;
break;
}
}
//*****************************************************************************
//
//! Gets the current UART status flags.
//!
//! \param baseAddress is the base address of the UART module.
//! \param mask is the masked interrupt flag status to be returned.
//!
//! This returns the status for the UART module based on which
//! flag is passed. mask parameter can be either any of the following
//! selection.
//! - \b UART_LISTEN_ENABLE
//! - \b UART_FRAMING_ERROR
//! - \b UART_OVERRUN_ERROR
//! - \b UART_PARITY_ERROR
//! - \b UARTBREAK_DETECT
//! - \b UART_RECEIVE_ERROR
//! - \b UART_ADDRESS_RECEIVED
//! - \b UART_IDLELINE
//! - \b UART_BUSY
//!
//! Modified register is \b UCAxSTAT
//!
//! \return the masked status flag
//
//*****************************************************************************
unsigned char UART_queryStatusFlags (unsigned int baseAddress,
unsigned char mask)
{
ASSERT((UART_LISTEN_ENABLE == mask) ||
(UART_FRAMING_ERROR == mask) ||
(UART_OVERRUN_ERROR == mask) ||
(UART_PARITY_ERROR == mask) ||
(UARTBREAK_DETECT == mask) ||
(UART_RECEIVE_ERROR == mask) ||
(UART_ADDRESS_RECEIVED == mask) ||
(UART_IDLELINE == mask) ||
(UART_BUSY == mask)
);
return ( HWREGB(baseAddress + OFS_UCAxSTAT) & mask );
}
//*****************************************************************************
//
//! Enable capture compare interrupt
//!
//! \param baseAddress is the base address of the Timer module.
//! \param captureCompareRegister is the selected capture compare regsiter
//!
//! Modified register is \b TAxCCTLn
//!
//! \return None
//
//*****************************************************************************
void Timer_enableCaptureCompareInterrupt (unsigned int baseAddress,
unsigned int captureCompareRegister
)
{
ASSERT((TIMER_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) ||
(TIMER_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) ||
(TIMER_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) ||
(TIMER_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) ||
(TIMER_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) ||
(TIMER_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) ||
(TIMER_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister)
);
HWREGB(baseAddress + captureCompareRegister) &= ~CCIFG;
HWREG(baseAddress + captureCompareRegister) |= CCIE;
}
//*****************************************************************************
//
//! Configures the controls of the selected memory buffer.
//!
//! \param baseAddress is the base address of the ADC10 module.
//! \param inputSourceSelect is the input that will store the converted data
//! into the specified memory buffer.
//! Valid values are
//! \b ADC10_INPUT_A0 [Default]
//! \b ADC10_INPUT_A1
//! \b ADC10_INPUT_A2
//! \b ADC10_INPUT_A3
//! \b ADC10_INPUT_A4
//! \b ADC10_INPUT_A5
//! \b ADC10_INPUT_A6
//! \b ADC10_INPUT_A7
//! \b ADC10_INPUT_A8
//! \b ADC10_INPUT_A9
//! \b ADC10_INPUT_TEMPSENSOR
//! \b ADC10_INPUT_BATTERYMONITOR
//! \b ADC10_INPUT_A12
//! \b ADC10_INPUT_A13
//! \b ADC10_INPUT_A14
//! \b ADC10_INPUT_A15
//! Modified bits are \b ADC10INCHx of \b ADC10MCTL0 register.
//! \param positiveRefVoltageSourceSelect is the reference voltage source to set
//! as the upper limit for the conversion that is to be stored in the
//! specified memory buffer.
//! Valid values are
//! \b ADC10_VREFPOS_AVCC [Default]
//! \b ADC10_VREFPOS_EXT
//! \b ADC10_VREFPOS_INT
//! Modified bits are \b ADC10SREF of \b ADC10MCTL0 register.
//! \param negativeRefVoltageSourceSelect is the reference voltage source to set
//! as the lower limit for the conversion that is to be stored in the
//! specified memory buffer.
//! Valid values are
//! \b ADC10_VREFPOS_AVSS [Default]
//! \b ADC10_VREFPOS_EXT
//! Modified bits are \b ADC10SREF of \b ADC10CTL0 register.
//!
//! Maps an input signal conversion into the memory buffer, as
//! well as the positive and negative reference voltages for each conversion
//! being stored into the memory buffer. If the internal reference is used for
//! the positive reference voltage, the internal REF module has to control
//! the voltage level. Note that if a conversion has been started with the
//! startConversion() function, then a call to disableConversions() is required
//! before this function may be called.
//!
//! \return NONE
//
//*****************************************************************************
void ADC10_memoryConfigure (unsigned int baseAddress,
unsigned char inputSourceSelect,
unsigned char positiveRefVoltageSourceSelect,
unsigned char negativeRefVoltageSourceSelect)
{
//Make sure the ENC bit is cleared before configuring a Memory Buffer Control
ASSERT( !(HWREG(baseAddress + OFS_ADC10CTL0) & ADC10ENC) );
ASSERT(inputSourceSelect <= ADC10_INPUT_A15);
ASSERT(positiveRefVoltageSourceSelect <= ADC10_VREFPOS_INT);
ASSERT(negativeRefVoltageSourceSelect <= ADC10_VREFNEG_EXT);
//Reset and Set the Memory Buffer Control Bits
HWREGB(baseAddress + OFS_ADC10MCTL0) = inputSourceSelect
+ positiveRefVoltageSourceSelect +
negativeRefVoltageSourceSelect;
}
//*****************************************************************************
//
//! Sets up and enables the Sampling Timer Pulse Mode.
//!
//! \param baseAddress is the base address of the ADC12 module.
//! \param clockCycleHoldCountLowMem sets the amount of clock cycles to
//! sample-and-hold for the higher memory buffers 0-7.
//! Valid values are
//! \b ADC12_CYCLEHOLD_4_CYCLES [Default]
//! \b ADC12_CYCLEHOLD_8_CYCLES
//! \b ADC12_CYCLEHOLD_16_CYCLES
//! \b ADC12_CYCLEHOLD_32_CYCLES
//! \b ADC12_CYCLEHOLD_64_CYCLES
//! \b ADC12_CYCLEHOLD_96_CYCLES
//! \b ADC12_CYCLEHOLD_128_CYCLES
//! \b ADC12_CYCLEHOLD_192_CYCLES
//! \b ADC12_CYCLEHOLD_256_CYCLES
//! \b ADC12_CYCLEHOLD_384_CYCLES
//! \b ADC12_CYCLEHOLD_512_CYCLES
//! \b ADC12_CYCLEHOLD_768_CYCLES
//! \b ADC12_CYCLEHOLD_1024_CYCLES
//! Modified bits are \b ADC12SHT0x of \b ADC12CTL0 register.
//! \param clockCycleHoldCountHighMem sets the amount of clock cycles to
//! sample-and-hold for the higher memory buffers 8-15.
//! Valid values are
//! \b ADC12_CYCLEHOLD_4_CYCLES [Default]
//! \b ADC12_CYCLEHOLD_8_CYCLES
//! \b ADC12_CYCLEHOLD_16_CYCLES
//! \b ADC12_CYCLEHOLD_32_CYCLES
//! \b ADC12_CYCLEHOLD_64_CYCLES
//! \b ADC12_CYCLEHOLD_96_CYCLES
//! \b ADC12_CYCLEHOLD_128_CYCLES
//! \b ADC12_CYCLEHOLD_192_CYCLES
//! \b ADC12_CYCLEHOLD_256_CYCLES
//! \b ADC12_CYCLEHOLD_384_CYCLES
//! \b ADC12_CYCLEHOLD_512_CYCLES
//! \b ADC12_CYCLEHOLD_768_CYCLES
//! \b ADC12_CYCLEHOLD_1024_CYCLES
//! Modified bits are \b ADC12SHT1x of \b ADC12CTL0 register.
//! \param multipleSamplesEnabled allows multiple conversions to start
//! without a trigger signal from the sample/hold signal
//! Valid values are
//! \b ADC12_MULTIPLESAMPLESDISABLE - a timer trigger will be needed to
//! start every ADC conversion. [Default]
//! \b ADC12_MULTIPLESAMPLESENABLE - during a sequenced and/or repeated
//! conversion mode, after the first conversion, no sample/hold
//! signal is necessary to start subsequent sample/hold and
//! convert processes.
//! Modified bits are \b ADC12MSC of \b ADC12CTL0 register.
//!
//! This function sets up the sampling timer pulse mode which allows the
//! sample/hold signal to trigger a sampling timer to sample-and-hold an input
//! signal for a specified number of clock cycles without having to hold the
//! sample/hold signal for the entire period of sampling. Note that if a
//! conversion has been started with the startConversion() function, then a call
//! to disableConversions() is required before this function may be called.
//!
//! \return NONE
//
//*****************************************************************************
void ADC12_setupSamplingTimer (unsigned int baseAddress,
unsigned int clockCycleHoldCountLowMem,
unsigned int clockCycleHoldCountHighMem,
unsigned short multipleSamplesEnabled)
{
//Make sure the ENC bit is cleared before setting up sampling pulse mode
ASSERT( !(HWREGB(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) );
ASSERT(clockCycleHoldCountLowMem <= ADC12_CYCLEHOLD_1024_CYCLES);
ASSERT(clockCycleHoldCountHighMem <= ADC12_CYCLEHOLD_1024_CYCLES);
HWREG(baseAddress + OFS_ADC12CTL1) |= ADC12SHP;
//Reset clock cycle hold counts and msc bit before setting them
HWREG(baseAddress + OFS_ADC12CTL0) &=
~(ADC12SHT0_15 + ADC12SHT1_15 + ADC12MSC);
//Set clock cycle hold counts and msc bit
HWREG(baseAddress + OFS_ADC12CTL0) |= clockCycleHoldCountLowMem
+ (clockCycleHoldCountHighMem << 4)
+ multipleSamplesEnabled;
}
static void dump_usbmsc() {
syslog(LOG_EMERG, "USB0 OTG registers:");
syslog(LOG_EMERG, "CFGCHIP2: 0x%08x", HWREG(CFGCHIP2_USBPHYCTRL));
syslog(LOG_EMERG, "CTRL: 0x%08x", HWREG(USB_0_OTGBASE + USB_0_CTRL));
syslog(LOG_EMERG, "STAT: 0x%08x", HWREG(USB_0_OTGBASE + USB_0_STAT));
syslog(LOG_EMERG, "EMULATION: 0x%08x", HWREG(USB_0_OTGBASE + USB_0_EMULATION));
syslog(LOG_EMERG, "MODE: 0x%08x", HWREG(USB_0_OTGBASE + USB_0_MODE));
syslog(LOG_EMERG, "INTR_SRC: 0x%08x", HWREG(USB_0_OTGBASE + USB_0_INTR_SRC));
syslog(LOG_EMERG, "INTR_MASK: 0x%08x", HWREG(USB_0_OTGBASE + USB_0_INTR_MASK));
syslog(LOG_EMERG, "INTR_SRC_MASKED: 0x%08x", HWREG(USB_0_OTGBASE + USB_0_INTR_SRC_MASKED));
syslog(LOG_EMERG, "Common USB registers:");
syslog(LOG_EMERG, "FADDR: 0x%08x", HWREGB(USB0_BASE + USB_O_FADDR));
syslog(LOG_EMERG, "POWER: 0x%08x", HWREGB(USB0_BASE + USB_O_POWER));
syslog(LOG_EMERG, "INTRUSB: 0x%08x", HWREGB(USB0_BASE + USB_O_IS));
syslog(LOG_EMERG, "INTRUSBE: 0x%08x", HWREGB(USB0_BASE + USB_O_IE));
syslog(LOG_EMERG, "TESTMODE: 0x%08x", HWREGB(USB0_BASE + USB_O_TEST));
syslog(LOG_EMERG, "DEVCTL: 0x%08x", HWREGB(USB0_BASE + USB_O_DEVCTL));
}
