bool DispatchStage::checkScheduler(const InstRef &IR) { HWStallEvent::GenericEventType Event; const bool Ready = SC.canBeDispatched(IR, Event); if (!Ready) notifyEvent<HWStallEvent>(HWStallEvent(Event, IR)); return Ready; }
bool DispatchStage::checkRCU(const InstRef &IR) { const unsigned NumMicroOps = IR.getInstruction()->getDesc().NumMicroOps; if (RCU.isAvailable(NumMicroOps)) return true; notifyEvent<HWStallEvent>( HWStallEvent(HWStallEvent::RetireControlUnitStall, IR)); return false; }
bool DispatchStage::checkPRF(const InstRef &IR) { SmallVector<unsigned, 4> RegDefs; for (const std::unique_ptr<WriteState> &RegDef : IR.getInstruction()->getDefs()) RegDefs.emplace_back(RegDef->getRegisterID()); const unsigned RegisterMask = PRF.isAvailable(RegDefs); // A mask with all zeroes means: register files are available. if (RegisterMask) { notifyEvent<HWStallEvent>( HWStallEvent(HWStallEvent::RegisterFileStall, IR)); return false; } return true; }
bool Scheduler::canBeDispatched(const InstRef &IR) const { HWStallEvent::GenericEventType Type = HWStallEvent::Invalid; const InstrDesc &Desc = IR.getInstruction()->getDesc(); if (Desc.MayLoad && LSU->isLQFull()) Type = HWStallEvent::LoadQueueFull; else if (Desc.MayStore && LSU->isSQFull()) Type = HWStallEvent::StoreQueueFull; else { switch (Resources->canBeDispatched(Desc.Buffers)) { default: return true; case ResourceStateEvent::RS_BUFFER_UNAVAILABLE: Type = HWStallEvent::SchedulerQueueFull; break; case ResourceStateEvent::RS_RESERVED: Type = HWStallEvent::DispatchGroupStall; } } Owner->notifyStallEvent(HWStallEvent(Type, IR)); return false; }