/////////////////////////////////////////////////////////////////////
// 函数名称：
// 函数功能：
// 入口参数：
//
//
// 出口参数：无
////////////////////////////////////////////////////////////////////
uint8 Sound_init(void)
{
NetP *pnet;
uint8 tmp;
uint16 i;
// memset(blank_buf,0,512);
memset((BYTE *)&Sound_Contrl, 0, sizeof(struct SOUND_CONTRL_TYPE));
TMS320AIC23_init();
I2SInit();
DMA_Init();
I2SStart();
pnet = (NetP *)Get_NetPort();
tmp = pnet->Test_TTL;
pnet->Test_TTL = 6;
for (i = 0; i < 20000; i++)
{
if ( Sound_Contrl.play_contrl & SOUND_DMA1_OK)
{
IP_printf("IP:%d.%d.%d.%d声卡DMA1打开成功", pnet->My_Ip[0], pnet->My_Ip[1], pnet->My_Ip[2], pnet->My_Ip[3]);
break;
}
IO_FlagLingt_Flash();
}
if (( Sound_Contrl.play_contrl & SOUND_DMA1_OK) == 0)
IP_printf("IP:%d.%d.%d.%d声卡DMA1打开失败", pnet->My_Ip[0], pnet->My_Ip[1], pnet->My_Ip[2], pnet->My_Ip[3]);
for (i = 0; i < 10000; i++)
{
if ( Sound_Contrl.play_contrl & SOUND_DMA2_OK)
{
IP_printf("IP:%d.%d.%d.%d声卡DMA2打开成功", pnet->My_Ip[0], pnet->My_Ip[1], pnet->My_Ip[2], pnet->My_Ip[3]);
break;
}
IO_FlagLingt_Flash();
}
if (( Sound_Contrl.play_contrl & SOUND_DMA1_OK) == 0)
IP_printf("IP:%d.%d.%d.%d声卡DMA2打开失败", pnet->My_Ip[0], pnet->My_Ip[1], pnet->My_Ip[2], pnet->My_Ip[3]);
pnet->Test_TTL = tmp;
return 0;
}
/*******************************************************************************
** Main Function main()
*******************************************************************************/
int main (void)
{
uint32_t i;
SystemInit();
/* The test program is to connect CLK, WS, and SDA lines between the
TX and RX. DAO is the master output, DAI is the slave input. This test
is not a real-world application but test both TX and RX channel in
a single program. However, due to the sync issue, the TX will start with
MUTE data 0 once it starts while RX is not ready. So, it may begins
with some MUTE value in the beginning of the RX buffer. This is beyond
control unless throw away the very first few bytes in the RX buffer.
In this program, the very first byte is not compared between the TX buffer
and RX buffer due to this synchonization issue. */
/* Configure temp register before reading */
for ( i = 0; i < BUFSIZE; i++ ) /* clear buffer */
{
I2STXBuffer[i] = i;
I2SRXBuffer[i] = 0;
}
if ( I2SInit() == FALSE ) /* initialize I2S */
{
while ( 1 ); /* Fatal error */
}
#if I2S_DMA_ENABLED
/* USB RAM is used for test.
Please note, Ethernet has its own SRAM, but GPDMA can't access
that. GPDMA can access USB SRAM and IRAM. Ethernet DMA controller can
access both IRAM and Ethernet SRAM. */
SC -> PCONP |= (1 << 29); /* Enable GPDMA clock */
GPDMA -> DMACIntTCClear = 0x03;
GPDMA -> DMACIntErrClr = 0x03;
GPDMA -> DMACConfig = 0x01; /* Enable DMA channels, little endian */
while ( !(GPDMA -> DMACConfig & 0x01) );
/* on DMA channel 0, Source is memory, destination is I2S TX FIFO,
on DMA channel 1, source is I2S RX FIFO, Destination is memory */
/* Enable channel and IE bit */
DMA_Init( 0, M2P );
GPDMACH0 -> DMACCConfig |= 0x18001 | (0x00 << 1) | (0x05 << 6) | (0x01 << 11);
DMA_Init( 1, P2M );
GPDMACH1 -> DMACCConfig |= 0x08001 | (0x06 << 1) | (0x00 << 6) | (0x02 << 11);
NVIC_EnableIRQ(DMA_IRQn);
I2SStart();
I2S -> I2SDMA2 = (0x01<<0) | (0x08<<8); /* Channel 2 is for RX, enable RX first. */
I2S -> I2SDMA1 = (0x01<<1) | (0x01<<16);/* Channel 1 is for TX. */
/* Wait for both DMA0 and DMA1 to finish before verifying. */
while ( !I2SDMA0Done || !I2SDMA1Done );
#else
/* Not DMA mode, enable I2S interrupts. */
/* RX FIFO depth is 1, TX FIFO depth is 8. */
I2SStart();
I2S -> I2SIRQ = (8 << 16) | (1 << 8) | (0x01 << 0);
while ( I2SWriteLength < BUFSIZE )
{
while (((I2S -> I2SSTATE >> 16) & 0xFF) == TXFIFO_FULL);
I2S -> I2STXFIFO = I2STXBuffer[I2SWriteLength++];
}
I2STXDone = 1;
/* Wait for RX and TX complete before comparison */
while ( !I2SRXDone || !I2STXDone );
#endif
/* Validate TX and RX buffer */
for ( i=1; i<BUFSIZE; i++ )
{
if ( I2SRXBuffer[i] != I2STXBuffer[i-1] )
{
while ( 1 ); /* Validation error */
}
}
return 0;
}
/*******************************************************************************
** Main Function main()
*******************************************************************************/
int main (void)
{
uint32_t i;
/* SystemClockUpdate() updates the SystemFrequency variable */
SystemClockUpdate();
/* The test program is to connect CLK, WS, and SDA lines between the
TX and RX. DAO is the master output, DAI is the slave input. This test
is not a real-world application but test both TX and RX channel in
a single program. However, due to the sync issue, the TX will start with
MUTE data 0 once it starts while RX is not ready. So, it may begins
with some MUTE value in the beginning of the RX buffer. This is beyond
control unless throw away the very first few bytes in the RX buffer.
In this program, the very first byte is not compared between the TX buffer
and RX buffer due to this synchonization issue. */
/* Configure temp register before reading */
for ( i = 0; i < BUFSIZE; i++ ) /* clear buffer */
{
I2STXBuffer[i] = i;
I2SRXBuffer[i] = 0;
}
I2SInit(); /* initialize I2S */
#if I2S_DMA_ENABLED
DMA_Init();
/* Select secondary function(I2S) in DMA channels */
LPC_SC->DMAREQSEL = (0x1<<DMA_I2S_REQ0)|(0x1<<DMA_I2S_REQ1);
/* on DMA channel 0, Source is memory, destination is I2S TX FIFO,
on DMA channel 1, source is I2S RX FIFO, Destination is memory */
/* Enable channel and IE bit */
DMAChannel_Init( 0, M2P );
LPC_GPDMACH0->CConfig |= (0x18001|(0x00<<1)|(DMA_I2S_REQ0<<6)|(0x01<<11));
DMAChannel_Init( 1, P2M );
LPC_GPDMACH1->CConfig |= (0x08001|(DMA_I2S_REQ1<<1)|(0x00<<6)|(0x02<<11));
NVIC_EnableIRQ(DMA_IRQn);
I2SStart();
LPC_I2S->DMA2 = (0x01<<0) | (0x08<<8); /* Channel 2 is for RX, enable RX first. */
LPC_I2S->DMA1 = (0x01<<1) | (0x01<<16); /* Channel 1 is for TX. */
/* Wait for both DMA0 and DMA1 to finish before verifying. */
while ( !I2SDMA0Done || !I2SDMA1Done );
#else
/* Not DMA mode, enable I2S interrupts. */
NVIC_EnableIRQ(I2S_IRQn);
/* RX FIFO depth is 1, TX FIFO depth is 8. */
I2SStart();
LPC_I2S->IRQ = (8 << 16) | (1 << 8) | (0x01 << 0);
while ( I2SWriteLength < BUFSIZE )
{
while (((LPC_I2S->STATE >> 16) & 0xFF) == TXFIFO_FULL);
LPC_I2S->TXFIFO = I2STXBuffer[I2SWriteLength++];
}
I2STXDone = 1;
/* Wait for RX and TX complete before comparison */
while ( !I2SRXDone || !I2STXDone );
#endif
/* Validate TX and RX buffer */
for ( i=1; i<BUFSIZE; i++ )
{
if ( I2SRXBuffer[i] != I2STXBuffer[i-1] )
{
while ( 1 ); /* Validation error */
}
}
while ( 1 ); /* Don't exit from main when finishing. */
}
