/* Configure I2S for Audio Format input */
Status Chip_I2S_Config(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *fmt)
{
volatile uint32_t cfg1 = 0, cfg2 = 0;
switch (fmt->MSCfg) { /* program the correct master/slave configuration */
case NORMAL_SLAVE: /* set to normal slave */
cfg1 |= I2S_CFG1_MSTSLVCFG(0);
break;
case WS_SYNC_MASTER: /* set to WS sync master mode */
cfg1 |= I2S_CFG1_MSTSLVCFG(1);
break;
case EXT_SCLCK_MASTER: /* set to SCLK master mode */
cfg1 |= I2S_CFG1_MSTSLVCFG(2);
break;
case NORMAL_MASTER: /* set to normal master mode */
cfg1 |= I2S_CFG1_MSTSLVCFG(3);
break;
}
switch (fmt->Mode) { /* set I2S mode */
case I2S_CLASSIC:
cfg1 |= I2S_CFG1_MODE(0);
break;
case DSP_WS_50:
cfg1 |= I2S_CFG1_MODE(1);
break;
case DSP_WS_SHORT:
cfg1 |= I2S_CFG1_MODE(2);
break;
case DSP_WS_LONG:
cfg1 |= I2S_CFG1_MODE(3);
break;
}
cfg1 |= (fmt->RightLow == true) ? I2S_CFG1_RIGHTLOW : 0; /* set right low (channel swap) */
cfg1 |= (fmt->LeftJust == true) ? I2S_CFG1_LEFTJUST : 0; /* set data justification */
cfg1 |= (fmt->PDMData == true) ? I2S_CFG1_PDMDATA : 0; /* set source to PDM dmic */
cfg1 |= (fmt->SCKPol == true) ? I2S_CFG1_PDMDATA : 0; /* set SCLK polarity */
cfg1 |= (fmt->WSPol == true) ? I2S_CFG1_PDMDATA : 0; /* set WS polarity */
cfg1 |= (fmt->ChannelNumber == 1) ? I2S_CFG1_ONECHANNEL : 0; /* set mono mode */
cfg1 |= I2S_CFG1_DATALEN(fmt->WordWidth-1); /* set data length */
cfg2 |= I2S_CFG2_FRAMELEN(fmt->FrameWidth-1); /* set frame width */
cfg2 |= I2S_CFG2_POSITION(fmt->DataPos); /* set data position within the frame */
pI2S->CFG1 = cfg1; /* set configuration in registers */
pI2S->CFG2 = cfg2;
pI2S->DIV = ((fmt->Divider-1) & 0x1ff); /* set the clock divider */
return SUCCESS;
}
static void I2S_Config(I2S_Type *base, const i2s_config_t *config)
{
assert(config);
uint32_t cfg1 = 0U;
uint32_t cfg2 = 0U;
/* set master/slave configuration */
cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave);
/* set I2S mode */
cfg1 |= I2S_CFG1_MODE(config->mode);
/* set right low (channel swap) */
cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow);
/* set data justification */
cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust);
/* set source to PDM dmic */
cfg1 |= I2S_CFG1_PDMDATA(config->pdmData);
/* set SCLK polarity */
cfg1 |= I2S_CFG1_SCK_POL(config->sckPol);
/* set WS polarity */
cfg1 |= I2S_CFG1_WS_POL(config->wsPol);
/* set mono mode */
cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel);
/* set data length */
cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1U);
/* set frame length */
cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1U);
/* set data position of this channel pair within the frame */
cfg2 |= I2S_CFG2_POSITION(config->position);
/* write to registers */
base->CFG1 = cfg1;
base->CFG2 = cfg2;
/* set the clock divider */
base->DIV = I2S_DIV_DIV(config->divider - 1U);
}
