AGESA_STATUS
PcieEarlyInterfaceCZ (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
PCIe_PLATFORM_CONFIG *Pcie;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceCZ Enter\n");
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
PciePortsVisibilityControlV5 (UnhidePorts, Pcie);
Status = PcieEarlyInitCZ (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieEarlyPortInitCZ (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieTrainingV2 (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader);
PciePortsVisibilityControlV5 (HidePorts, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceCZ Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* FchInitEnv - Config Fch before PCI emulation
*
*
*
* @param[in] EnvParams
*
*/
AGESA_STATUS
FchInitEnv (
IN AMD_ENV_PARAMS *EnvParams
)
{
UINT8 i;
UINT8 Data;
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Enter... \n");
FchParams = FchInitEnvCreatePrivateData (EnvParams);
// Override internal data with IDS (Optional, internal build only)
IDS_OPTION_CALLOUT (IDS_CALLOUT_FCH_INIT_ENV, FchParams, FchParams->StdHeader);
//
//to_do-Initialize PCI IRQ routing registers for INTA#-INTH#
//
for (i = 0; i < 8; i++) {
Data = i | BIT7; // Select IRQ routing to APIC
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Data, &EnvParams->StdHeader);
Data = i | BIT4;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Data, &EnvParams->StdHeader);
}
AgesaFchOemCallout (FchParams);
Status = FchTaskLauncher (&FchInitEnvTaskTable[0], FchParams);
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Exit... Status = [0x%x]\n", Status);
return Status;
}
AGESA_STATUS
STATIC
PcieEarlyPortInitCZ (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
Status = AGESA_SUCCESS;
// Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit
if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
Pcie->TrainingExitState = LinkStateResetExit;
}
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieEarlyPortInitCallbackCZ,
NULL,
Pcie
);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_EARLY_PORT_CONFIG, Pcie, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
return Status;
}
/**
* FchInitEnv - Config Fch before PCI emulation
*
*
*
* @param[in] EnvParams
*
*/
AGESA_STATUS
FchInitEnv (
IN AMD_ENV_PARAMS *EnvParams
)
{
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Enter... \n");
FchParams = FchInitEnvCreatePrivateData (EnvParams);
// Override internal data with IDS (Optional, internal build only)
IDS_OPTION_CALLOUT (IDS_CALLOUT_FCH_INIT_ENV, FchParams, FchParams->StdHeader);
AgesaFchOemCallout (FchParams);
Status = FchTaskLauncher (&FchInitEnvTaskTable[0], FchParams, TpFchInitEnvDispatching);
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Exit... Status = [0x%x]\n", Status);
return Status;
}
/**
* FchInitReset - Config Fch during power on stage.
*
*
*
* @param[in] ResetParams
*
*/
AGESA_STATUS
FchInitReset (
IN AMD_RESET_PARAMS *ResetParams
)
{
FCH_RESET_DATA_BLOCK FchParams;
// Load private data block with default
FchInitResetLoadPrivateDefault (&FchParams, &ResetParams->StdHeader);
// Override external data with input parameters
FchParams.StdHeader = &ResetParams->StdHeader;
FchParams.FchReset = &ResetParams->FchInterface;
// Override internal data with IDS (Optional, internal build only)
IDS_OPTION_CALLOUT (IDS_CALLOUT_FCH_INIT_RESET, &FchParams, &ResetParams->StdHeader);
AgesaFchOemCallout (&FchParams);
return FchTaskLauncher (&FchInitResetTaskTable[0], &FchParams);
}
AGESA_STATUS
GnbEarlyInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GNB_HANDLE *GnbHandle;
UINT32 Property;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceML Enter\n");
GnbHandle = GnbGetHandle (StdHeader);
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
ASSERT (GnbBuildOptionData != NULL);
Property = TABLE_PROPERTY_DEFAULT;
Property |= UserOptions.CfgGnbSyncFloodPinAsNmi ? TABLE_PROPERTY_NMI_SYNCFLOOD : 0;
IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PACKAGE_POWER_CONFIG, GnbHandle, StdHeader);
GnbInitSmuBiosTableML (StdHeader);
Status = GnbProcessTable (
GnbHandle,
GnbEarlyInitTableML,
Property,
0,
StdHeader
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (GnbBuildOptionData->CfgUseSMUServices == TRUE) {
GnbRequestVddNbPminML (GnbHandle, StdHeader);
}
Status = GfxGBifEnableML (StdHeader);
ASSERT (Status == AGESA_SUCCESS);
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceML Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* PCIe Post Init
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
PciePostInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceML Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
IDS_OPTION_HOOK (IDS_BEFORE_GEN2_INIT, Pcie, StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
ASSERT (GnbBuildOptionData != NULL);
if ((Status == AGESA_SUCCESS) &&
(GnbBuildOptionData->CfgUseSMUServices == TRUE)) {
PciePortsVisibilityControlV5 (UnhidePorts, Pcie);
Status = PciePostInitML (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PciePostPortInitML (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieTrainingV2 (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader);
GnbSmuBiosTableGetPcieInfoML (StdHeader, Pcie);
PciePortsVisibilityControlV5 (HidePorts, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceML Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* Pcie TxPreset loading sequence
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieEarlyWrapperTxPresetLoadingSequenceCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 Pif;
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyWrapperTxPresetLoadingSequenceCZ Enter\n");
// Step 1: program TX preset value of PCIE_WRAPPER:PSX80/81_WRP_BIF_LANE_EQUALIZATION_CNTL to 0x7 ( from h/w default 0xF )
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0050_ADDRESS),
D0F0xE4_WRAP_0050_StrapBifPcieLaneEqCntlDsPortTxPreset_MASK | D0F0xE4_WRAP_0050_StrapBifPcieLaneEqCntlUsPortTxPreset_MASK,
(7 << D0F0xE4_WRAP_0050_StrapBifPcieLaneEqCntlDsPortTxPreset_OFFSET) | (7 << D0F0xE4_WRAP_0050_StrapBifPcieLaneEqCntlUsPortTxPreset_OFFSET),
TRUE,
Pcie
);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_BEFORE_TXPRESET_LOADING, Pcie, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
// Step 2: program TOGGLESTRAP bit of PCIE_WRAPPER:PSX80/81_BIF_SWRST_COMMAND_1 to 0x1
PcieRegisterRMW (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0103_ADDRESS),
D0F0xE4_CORE_0103_Togglestrap_MASK,
(1 << D0F0xE4_CORE_0103_Togglestrap_OFFSET),
TRUE,
Pcie
);
// Wait for ~50ns
GnbLibStall (1, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
// program TOGGLESTRAP bit of PCIE_WRAPPER:PSX80/81_BIF_SWRST_COMMAND_1 to 0x0
PcieRegisterRMW (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0103_ADDRESS),
D0F0xE4_CORE_0103_Togglestrap_MASK,
(0 << D0F0xE4_CORE_0103_Togglestrap_OFFSET),
TRUE,
Pcie
);
}
for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
// Step 3: program TXPWR_IN_INIT bit of PCIE_WRAPPER:PSX80/81_PIF0_TX_CTRL to 0x1 ( from h/w default 0x2 )
// program RXPWR_IN_INIT bit of PCIE_WRAPPER:PSX80/81_PIF0_RX_CTRL to 0x1 ( from h/w default 0x2 )
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS),
D0F0xE4_PIF_0008_TxpwrInInit_MASK,
(1 << D0F0xE4_PIF_0008_TxpwrInInit_OFFSET),
TRUE,
Pcie
);
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS),
D0F0xE4_PIF_000A_RxpwrInInit_MASK,
(1 << D0F0xE4_PIF_000A_RxpwrInInit_OFFSET),
TRUE,
Pcie
);
// Wait for ~1ns
GnbLibStall (1, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
//Step 5: program TXPWR_IN_INIT bit of PCIE_WRAPPER:PSX80/81_PIF0_TX_CTRL back to 0x2
// program RXPWR_IN_INIT bit of PCIE_WRAPPER:PSX80/81_PIF0_RX_CTRL back to 0x2
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS),
D0F0xE4_PIF_0008_TxpwrInInit_MASK,
(2 << D0F0xE4_PIF_0008_TxpwrInInit_OFFSET),
TRUE,
Pcie
);
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS),
D0F0xE4_PIF_000A_RxpwrInInit_MASK,
(2 << D0F0xE4_PIF_000A_RxpwrInInit_OFFSET),
TRUE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyWrapperTxPresetLoadingSequenceCZ Exit\n");
}
/**
* Build integrated info table
*
*
*
* @param[in] Gfx Gfx configuration info
* @retval AGESA_STATUS
*/
AGESA_STATUS
STATIC
GfxIntInfoTableInitTN (
IN GFX_PLATFORM_CONFIG *Gfx
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
ATOM_FUSION_SYSTEM_INFO_V2 SystemInfoTableV2;
PP_FUSE_ARRAY *PpFuseArray;
PCIe_PLATFORM_CONFIG *Pcie;
ATOM_PPLIB_POWERPLAYTABLE3 *PpTable;
UINT8 Channel;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitTN Enter\n");
LibAmdMemFill (&SystemInfoTableV2, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V2), GnbLibGetHeader (Gfx));
SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7);
ASSERT (SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize == 512);
SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableContentRevision = 7;
SystemInfoTableV2.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetSytemPllCofTN (GnbLibGetHeader (Gfx)) * 100;
SystemInfoTableV2.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100;
SystemInfoTableV2.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl;
SystemInfoTableV2.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
SystemInfoTableV2.sIntegratedSysInfo.ucMemoryType = 3; //DDR3
SystemInfoTableV2.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ
SystemInfoTableV2.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx));
SystemInfoTableV2.sIntegratedSysInfo.ulMinEngineClock = 200 * 100;
SystemInfoTableV2.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate;
SystemInfoTableV2.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
//Locate PCIe configuration data to get definitions of display connectors
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1;
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex;
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport;
SystemInfoTableV2.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7, sExtDispConnInfo);
SystemInfoTableV2.sIntegratedSysInfo.ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx));
SystemInfoTableV2.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum;
SystemInfoTableV2.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value;
IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value);
if (Gfx->LvdsMiscControl.Field.TravisLvdsVoltOverwriteEn) {
SystemInfoTableV2.sIntegratedSysInfo.gnbgfxline429 = Gfx->gfxplmcfg0 ;
IDS_HDT_CONSOLE (GNB_TRACE, "TravisLVDSVoltAdjust : %x\n", Gfx->gfxplmcfg0 );
}
SystemInfoTableV2.sIntegratedSysInfo.ulOtherDisplayMisc = Gfx->DisplayMiscControl.Value;
IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value);
// LVDS
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl;
SystemInfoTableV2.sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue;
SystemInfoTableV2.sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq;
Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
Status = GfxIntegratedEnumerateAllConnectors (
&SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sPath[0],
Pcie,
Gfx
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
GfxIntegrateducEDPToLVDSRxIdCallback,
&SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId,
Pcie
);
// Build PP table
PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoTableV2.ulPowerplayTable;
// Build PP table
Status = GfxPowerPlayBuildTable (PpTable, Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
// Assign usFormatID to 0x000B to represent Trinity
PpTable->usFormatID = 0xB;
// Build info from fuses
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
ASSERT (PpFuseArray != NULL);
if (PpFuseArray != NULL) {
// Build Display clock info
GfxIntInfoTableInitDispclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx);
// Build Sclk info table
GfxIntInfoTableInitSclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx);
} else {
Status = AGESA_ERROR;
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
//@todo review if thouse parameters needed
// Fill in Nb P-state MemclkFreq Data
GfxFillNbPstateMemclkFreqTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
// Fill in HTC Data
GfxFillHtcDataTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
// Fill in NB P states VID
GfxFillNbPStateVidTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
// Fill in NCLK info
//GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Fill in the M3 arbitration control tables
//GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Family specific data update
// Determine ulGMCRestoreResetTime
Status = GfxCalculateRestoreResetTimeTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx, PpFuseArray);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
//GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
SystemInfoTableV2.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940;
SystemInfoTableV2.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000;
if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
Channel = 0;
} else {
Channel = 1;
}
if (GfxLibGetMemPhyPllPdModeTN (Channel, GnbLibGetHeader (Gfx)) != 0) {
SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT2;
}
if (GfxLibGetDisDllShutdownSRTN (Channel, GnbLibGetHeader (Gfx)) == 0) {
SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT1;
}
if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) {
SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT0;
}
SystemInfoTableV2.sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE;
IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoTableV2.sIntegratedSysInfo, GnbLibGetHeader (Gfx));
//Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.)
GfxIntInfoTabablePostToFb (&SystemInfoTableV2, Gfx);
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status);
return Status;
}
/**
* Family 15h core 0 entry point for performing power plane initialization.
*
* The steps are as follows:
* 1. Configure D18F3xD8[VSRampSlamTime] based on platform
* requirements.
* 2. Configure F3xD4[PowerStepUp & PowerStepDown]
* 3. Optionally configure F3xA0[PsiVidEn & PsiVid]
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F15TnPmPwrPlaneInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
UINT32 SystemSlewRate;
UINT32 WaitTime;
UINT32 VSRampSlamTime;
UINT32 LocalPciRegister;
CLK_PWR_TIMING_CTRL1_REGISTER ClkPwrTimingCtrl1;
BOOLEAN SkipPowerPlan;
SkipPowerPlan = FALSE;
IDS_OPTION_CALLOUT (IDS_CALLOUT_POWER_PLAN_INIT, &SkipPowerPlan, StdHeader);
if (!SkipPowerPlan) {
// Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements.
// Voltage Ramp Time = maximum time to change voltage by 15mV rounded to the next higher encoding.
SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <=
CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ?
CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate :
CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate;
ASSERT (SystemSlewRate != 0);
// First, calculate the time it takes to change 15mV using the VRM slew rate.
WaitTime = (15000 * 100) / SystemSlewRate;
if (((15000 * 100) % SystemSlewRate) != 0) {
WaitTime++;
}
// Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds
// to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable
// VRM can be.
for (VSRampSlamTime = ((sizeof (F15TnVSRampSlamWaitTimes) / sizeof (F15TnVSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) {
if (WaitTime <= F15TnVSRampSlamWaitTimes[VSRampSlamTime]) {
break;
}
}
if (WaitTime > F15TnVSRampSlamWaitTimes[0]) {
// The VRMs on this motherboard are too slow for this CPU.
IDS_ERROR_TRAP;
}
// Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value.
PciAddress.AddressValue = CPTC1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl1, StdHeader);
ClkPwrTimingCtrl1.VSRampSlamTime = VSRampSlamTime;
LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl1, StdHeader);
// Configure PowerStepUp/PowerStepDown
PciAddress.AddressValue = CPTC0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepUp = 8;
((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepDown = 8;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
/**
* Build integrated info table
*
*
*
* @param[in] Gfx Gfx configuration info
* @retval AGESA_STATUS
*/
AGESA_STATUS
GfxIntegratedInfoTableInit (
IN GFX_PLATFORM_CONFIG *Gfx
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
ATOM_FUSION_SYSTEM_INFO_V1 SystemInfoV1Table;
PP_FUSE_ARRAY *PpFuseArray;
PCIe_PLATFORM_CONFIG *Pcie;
UINT32 IntegratedInfoAddress;
ATOM_PPLIB_POWERPLAYTABLE3 *PpTable;
UINT8 Channel;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Enter\n");
LibAmdMemFill (&SystemInfoV1Table, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), GnbLibGetHeader (Gfx));
SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V6);
ASSERT (SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize == 512);
SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableContentRevision = 6;
SystemInfoV1Table.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetMainPllFreq (GnbLibGetHeader (Gfx)) * 100;
SystemInfoV1Table.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100;
SystemInfoV1Table.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl;
SystemInfoV1Table.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
SystemInfoV1Table.sIntegratedSysInfo.ucMemoryType = 3; //DDR3
SystemInfoV1Table.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ
SystemInfoV1Table.sIntegratedSysInfo.usBootUpNBVoltage = GfxLibMaxVidIndex (GnbLibGetHeader (Gfx));
SystemInfoV1Table.sIntegratedSysInfo.ulMinEngineClock = GfxLibGetMinSclk (GnbLibGetHeader (Gfx));
SystemInfoV1Table.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate;
SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSpreadRateIn10Hz = Gfx->LvdsSpreadSpectrumRate;
SystemInfoV1Table.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum;
// SystemInfoV1Table.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value;
//Locate PCIe configuration data to get definitions of display connectors
SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1;
SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex;
ASSERT ((Gfx->UmaInfo.UmaAttributes & (UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1)) != 0);
if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
Channel = 0;
} else {
Channel = 1;
}
if (GfxLibGetCsrPhySrPllPdMode (Channel, GnbLibGetHeader (Gfx)) != 0) {
SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT2;
}
if (GfxLibGetDisDllShutdownSR (Channel, GnbLibGetHeader (Gfx)) == 0) {
SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT1;
}
Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
Status = GfxIntegratedEnumerateAllConnectors (
&SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sPath[0],
Pcie,
Gfx
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
SystemInfoV1Table.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V6, sExtDispConnInfo);
// Build PP table
PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoV1Table.ulPowerplayTable;
// Build PP table
Status = GfxPowerPlayBuildTable (PpTable, Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
// Build info from fuses
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
ASSERT (PpFuseArray != NULL);
if (PpFuseArray != NULL) {
// Build Display clock info
GfxIntegratedInfoInitDispclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Build Sclk info table
GfxIntegratedInfoInitSclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx);
} else {
Status = AGESA_ERROR;
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
// Fill in HTC Data
GfxFillHtcData (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Fill in NB P states VID
GfxFillNbPStateVid (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Fill in NCLK info
GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Fill in the M3 arbitration control tables
GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Fill South bridge MMIO Base address
GfxFillSbMmioBaseAddress (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Family specific data update
GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoV1Table.sIntegratedSysInfo, GnbLibGetHeader (Gfx));
//Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.)
IntegratedInfoAddress = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V1));
GfxLibCopyMemToFb ((VOID *) (&SystemInfoV1Table), IntegratedInfoAddress, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), Gfx);
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status);
return Status;
}
