static int ofw_pcib_pci_route_interrupt(device_t bridge, device_t dev, int intpin) { struct ofw_pcib_softc *sc; struct ofw_bus_iinfo *ii; struct ofw_pci_register reg; cell_t pintr, mintr; phandle_t iparent; uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; sc = device_get_softc(bridge); ii = &sc->ops_iinfo; if (ii->opi_imapsz > 0) { pintr = intpin; if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), ii, ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), &iparent, maskbuf)) { /* * If we've found a mapping, return it and don't map * it again on higher levels - that causes problems * in some cases, and never seems to be required. */ return (INTR_VEC(iparent, mintr)); } } else if (intpin >= 1 && intpin <= 4) { /* * When an interrupt map is missing, we need to do the * standard PCI swizzle and continue mapping at the parent. */ return (pcib_route_interrupt(bridge, dev, intpin)); } return (PCIB_ROUTE_INTERRUPT(device_get_parent(device_get_parent( bridge)), bridge, intpin)); }
static int grackle_route_interrupt(device_t bus, device_t dev, int pin) { struct grackle_softc *sc; struct ofw_pci_register reg; uint32_t pintr, mintr; phandle_t iparent; uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; sc = device_get_softc(bus); pintr = pin; if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), &iparent, maskbuf)) return (INTR_VEC(iparent, mintr)); /* Maybe it's a real interrupt, not an intpin */ if (pin > 4) return (pin); device_printf(bus, "could not route pin %d for device %d.%d\n", pin, pci_get_slot(dev), pci_get_function(dev)); return (PCI_INVALID_IRQ); }
#define INTR_OP 0x82 #define INTR_VEC(func) { INTR_OP, (intr_handler_t)func } @interrupt void DefaultInterrupt (void) { return; } #define INTR_DEFAULT INTR_VEC(DefaultInterrupt) extern void _stext(); /* startup routine */ extern void ppm_interrupt(void); extern void timer_interrupt(void); struct intr_vector const _vectab[] = { INTR_VEC(_stext), /* reset */ INTR_DEFAULT, /* trap */ INTR_DEFAULT, /* 0 TLI - External top level interrupt */ INTR_DEFAULT, /* 1 AWU - Auto wakeup from halt */ INTR_DEFAULT, /* 2 CLK - Clock controller */ INTR_DEFAULT, /* 3 EXTI0 - Port A external interrupts */ INTR_DEFAULT, /* 4 EXTI1 - Port B external interrupts */ INTR_DEFAULT, /* 5 EXTI2 - Port C external interrupts */ INTR_DEFAULT, /* 6 EXTI3 - Port D external interrupts */ INTR_DEFAULT, /* 7 EXTI4 - Port E external interrupts */ INTR_DEFAULT, /* 8 */ INTR_DEFAULT, /* 9 */ INTR_DEFAULT, /* 10 SPI - End of transfer */ INTR_DEFAULT, /* 11 TIM1 - update/overflow/underflow/trigger/break */ INTR_DEFAULT, /* 12 TIM1 - capture/compare */ INTR_VEC(timer_interrupt),/* 13 TIM2 - update/overflow */