* Interrupt Management Functions
*/
#define TNUM_INHNO 6
const uint_t _kernel_tnum_inhno = TNUM_INHNO;
INTHDR_ENTRY(INHNO_TIMER_PRC1, 0x10005, target_timer_handler)
INTHDR_ENTRY(INHNO_TIMER_PRC2, 0x20005, target_timer_handler)
INTHDR_ENTRY(INHNO_SIO_PRC1, 0x10002, sio_handler)
INTHDR_ENTRY(INHNO_SIO_PRC2, 0x20002, sio_handler)
INTHDR_ENTRY(INHNO_IPI_PRC1, 0x10010, _kernel_ipi_handler)
INTHDR_ENTRY(INHNO_IPI_PRC2, 0x20010, _kernel_ipi_handler)
const INHINIB _kernel_inhinib_table[TNUM_INHNO] = {
{ (INHNO_TIMER_PRC1), (TA_NULL), (FP)(INT_ENTRY(INHNO_TIMER_PRC1, target_timer_handler)), 1, (uint_t)(0x1) },
{ (INHNO_TIMER_PRC2), (TA_NULL), (FP)(INT_ENTRY(INHNO_TIMER_PRC2, target_timer_handler)), 2, (uint_t)(0x2) },
{ (INHNO_SIO_PRC1), (TA_NULL), (FP)(INT_ENTRY(INHNO_SIO_PRC1, sio_handler)), 1, (uint_t)(0x1) },
{ (INHNO_SIO_PRC2), (TA_NULL), (FP)(INT_ENTRY(INHNO_SIO_PRC2, sio_handler)), 2, (uint_t)(0x2) },
{ (INHNO_IPI_PRC1), (TA_NULL), (FP)(INT_ENTRY(INHNO_IPI_PRC1, _kernel_ipi_handler)), 1, (uint_t)(0x1) },
{ (INHNO_IPI_PRC2), (TA_NULL), (FP)(INT_ENTRY(INHNO_IPI_PRC2, _kernel_ipi_handler)), 2, (uint_t)(0x2) }
};
#define TNUM_INTNO 6
const uint_t _kernel_tnum_intno = TNUM_INTNO;
const INTINIB _kernel_intinib_table[TNUM_INTNO] = {
{ (INTNO_TIMER_PRC1), (TA_ENAINT|INTATR_TIMER_PRC1), (INTPRI_TIMER_PRC1), 1, (uint_t)(0x1)},
{ (INTNO_TIMER_PRC2), (TA_ENAINT|INTATR_TIMER_PRC2), (INTPRI_TIMER_PRC2), 2, (uint_t)(0x2)},
{ (INTNO_SIO_PRC1), (INTATR_SIO_PRC1), (INTPRI_SIO_PRC1), 1, (uint_t)(0x1)},
{ (INTNO_SIO_PRC2), (INTATR_SIO_PRC2), (INTPRI_SIO_PRC2), 2, (uint_t)(0x2)},
TOPPERS_EMPTY_LABEL(ALMCB, _kernel_almcb_table);
/*
* Interrupt Management Functions
*/
#define TNUM_INHNO 3
const uint_t _kernel_tnum_inhno = TNUM_INHNO;
INTHDR_ENTRY(INHNO_TIMER, 21, target_timer_handler)
INTHDR_ENTRY(TINHNO_S0RACK, 18, UART_receive_handler)
INTHDR_ENTRY(TINHNO_S0TNACK, 17, UART_send_handler)
const INHINIB _kernel_inhinib_table[TNUM_INHNO] = {
{ (INHNO_TIMER), (TA_NULL), (FP)(INT_ENTRY(INHNO_TIMER, target_timer_handler)) },
{ (TINHNO_S0RACK), (TA_NULL), (FP)(INT_ENTRY(TINHNO_S0RACK, UART_receive_handler)) },
{ (TINHNO_S0TNACK), (TA_NULL), (FP)(INT_ENTRY(TINHNO_S0TNACK, UART_send_handler)) }
};
#define TNUM_INTNO 3
const uint_t _kernel_tnum_intno = TNUM_INTNO;
const INTINIB _kernel_intinib_table[TNUM_INTNO] = {
{ (INTNO_TIMER), (TA_ENAINT | INTATR_TIMER), (INTPRI_TIMER) },
{ (TINTNO_S0RACK), (TA_EDGE), (INTPRI_UART_recieve) },
{ (TINTNO_S0TNACK), (TA_EDGE), (INTPRI_UART_send) }
};
/*
* CPU Exception Handler
INT_ENTRY(PREFIX "_plus_us", (VAR)->thr_plus, 0600), \
INT_ENTRY(PREFIX "_max_ms", (VAR)->thr_max, 0600), \
INT_ENTRY(PREFIX "_triggered", (VAR)->thr_triggered,0400), \
INT_ENTRY(PREFIX "_true_hit", (VAR)->thr_true_hit, 0400) \
static
struct ctl_table traffic_tuning_table[] = {
LIMITER_ENTRIES(&client_limiter, "client_role_traffic", "kb"),
LIMITER_ENTRIES(&server_limiter, "server_role_traffic", "kb"),
{}
};
static
struct ctl_table io_tuning_table[] = {
LIMITER_ENTRIES(&global_writeback.limiter, "writeback", "kb"),
INT_ENTRY("writeback_until_percent", global_writeback.until_percent, 0600),
THRESHOLD_ENTRIES(&global_io_threshold, "global_io"),
THRESHOLD_ENTRIES(&bio_submit_threshold, "bio_submit"),
THRESHOLD_ENTRIES(&bio_io_threshold[0], "bio_io_r"),
THRESHOLD_ENTRIES(&bio_io_threshold[1], "bio_io_w"),
THRESHOLD_ENTRIES(&aio_submit_threshold, "aio_submit"),
THRESHOLD_ENTRIES(&aio_io_threshold[0], "aio_io_r"),
THRESHOLD_ENTRIES(&aio_io_threshold[1], "aio_io_w"),
THRESHOLD_ENTRIES(&aio_sync_threshold, "aio_sync"),
{}
};
static
struct ctl_table tcp_tuning_table[] = {
INT_ENTRY("ip_tos", default_tcp_params.ip_tos, 0600),
INT_ENTRY("tcp_window_size", default_tcp_params.tcp_window_size, 0600),
