static void
nitrogen6_mux_config(const struct iomux_conf *conflist)
{
int i;
uint32_t reg;
for (i = 0; conflist[i].pin != IOMUX_CONF_EOT; i++) {
reg = IOMUX_PIN_TO_PAD_ADDRESS(conflist[i].pin);
if (reg != IOMUX_PAD_NONE)
IOMUX_WRITE(reg, conflist[i].pad);
reg = IOMUX_PIN_TO_MUX_ADDRESS(conflist[i].pin);
if (reg != IOMUX_MUX_NONE)
IOMUX_WRITE(reg, conflist[i].mux);
}
}
static void
iomux_set_pad_sub(struct iomux_softc *sc, uint32_t pin, uint32_t config)
{
bus_size_t pad_ctl_reg = IOMUX_PIN_TO_PAD_ADDRESS(pin);
if (pad_ctl_reg != IOMUX_PAD_NONE)
IOMUX_WRITE(sc, pad_ctl_reg, config);
}
static void
iomux_set_function_sub(struct iomux_softc *sc, uint32_t pin, uint32_t fn)
{
bus_size_t mux_ctl_reg = IOMUX_PIN_TO_MUX_ADDRESS(pin);
if (mux_ctl_reg != IOMUX_MUX_NONE)
IOMUX_WRITE(sc, mux_ctl_reg, fn);
}
void
imx_iomux_gpr_set(u_int regnum, uint32_t val)
{
KASSERT(iomuxsc != NULL, ("imx_iomux_gpr_set() called before attach"));
KASSERT(regnum >= 0 && regnum <= 13,
("imx_iomux_gpr_set bad regnum %u", regnum));
IOMUX_WRITE(iomuxsc, IOMUXC_GPR0 + regnum, val);
}
void
imx_iomux_gpr_set_masked(u_int regnum, uint32_t clrbits, uint32_t setbits)
{
uint32_t val;
KASSERT(iomuxsc != NULL,
("imx_iomux_gpr_set_masked called before attach"));
KASSERT(regnum >= 0 && regnum <= 13,
("imx_iomux_gpr_set_masked bad regnum %u", regnum));
val = IOMUX_READ(iomuxsc, IOMUXC_GPR0 + regnum);
val = (val & ~clrbits) | setbits;
IOMUX_WRITE(iomuxsc, IOMUXC_GPR0 + regnum, val);
}
