int Flash_Write(ioAddress offset, ioData data) { ioData status = 0; IO_Write(CommandRegister, ProgramCommand); IO_Write(offset, data); while ((status & ReadyBit) == 0) status = IO_Read(StatusRegister); if (status != ReadyBit) { IO_Write(CommandRegister, Reset); if (status & VppErrorBit) return FLASH_VPP_ERROR; else if (status & ProgramErrorBit) return FLASH_PROGRAM_ERROR; else if (status & BlockProtectionErrorBit) return FLASH_PROTECTED_BLOCK_ERROR; else return FLASH_UNKNOWN_PROGRAM_ERROR; } return FLASH_SUCCESS; }
int Flash_Write(ioAddress address, ioData data) { IO_Write(0, 0x40); IO_Write(address, data); IO_Read(0); IO_Read(address); return FLASH_SUCCESS; }
int Flash_Write(ioAddress address, ioData data) { IO_Write(CommandRegister, ProgramCommand); IO_Write(address, data); IO_Read(StatusRegister); IO_Read(address); return FLASH_SUCCESS; }
Bit8u VESA_SetCPUWindow(Bit8u window,Bit8u address) { if (window) return VESA_FAIL; if (((Bit32u)(address)*64*1024<vga.vmemsize)) { IO_Write(0x3d4,0x6a); IO_Write(0x3d5,(Bit8u)address); return VESA_SUCCESS; } else return VESA_FAIL; }
void RestoreVgaRegisters() { for (int i=0; i<9; i++) { IO_Write(0x3CE,i); IO_Write(0x3CF,gfxReg3CE[i]); } IO_Write(0x3C4,2); IO_Write(0x3C5,gfxReg3C5); IO_Write(0x3C4,index3C4); }
void RestoreVgaRegisters() { if (IS_VGA_ARCH) { for (Bit8u i=0; i<9; i++) { IO_Write(0x3CE,i); IO_Write(0x3CF,gfxReg3CE[i]); } IO_Write(0x3C4,2); IO_Write(0x3C5,gfxReg3C5); IO_Write(0x3C4,index3C4); } }
int Flash_Write(ioAddress address, ioData data) { ioData status = 0; IO_Write(CommandRegister, ProgramCommand); IO_Write(address, data); while ((status & ReadyBit) == 0) status = IO_Read(StatusRegister); IO_Read(address); return FLASH_SUCCESS; }
int Flash_Write(ioAddress offset, ioData data) { ioData status = 0; IO_Write(CommandRegister, ProgramCommand); IO_Write(offset, data); while ((status & ReadyBit) == 0) status = IO_Read(StatusRegister); if (status != ReadyBit) return writeError(status); if (data != IO_Read(offset)) return FLASH_READ_BACK_ERROR; return FLASH_SUCCESS; }
Bit8u VESA_SetDisplayStart(Bit16u x,Bit16u y) { // TODO wait for retrace in case bl==0x80 Bitu pixels_per_offset; Bitu panning_factor = 1; switch (CurMode->type) { case M_TEXT: case M_LIN4: pixels_per_offset = 16; break; case M_LIN8: panning_factor = 2; // the panning register ignores bit0 in this mode pixels_per_offset = 8; break; case M_LIN15: case M_LIN16: panning_factor = 2; // this may be DOSBox specific pixels_per_offset = 4; break; case M_LIN32: pixels_per_offset = 2; break; default: return VESA_MODE_UNSUPPORTED; } // We would have to divide y by the character height for text modes and // write the remainder to the CRTC preset row scan register, // but VBE2 BIOSes that actually get that far also don't. // Only a VBE3 BIOS got it right. Bitu virtual_screen_width = vga.config.scan_len * pixels_per_offset; Bitu new_start_pixel = virtual_screen_width * y + x; Bitu new_crtc_start = new_start_pixel / (pixels_per_offset/2); Bitu new_panning = new_start_pixel % (pixels_per_offset/2); new_panning *= panning_factor; vga.config.display_start = new_crtc_start; // Setting the panning register is nice as it allows for super smooth // scrolling, but if we hit the retrace pulse there may be flicker as // panning and display start are latched at different times. IO_Read(0x3da); // reset attribute flipflop IO_Write(0x3c0,0x13 | 0x20); // panning register, screen on IO_Write(0x3c0,new_panning); return VESA_SUCCESS; }
Bit8u VESA_SetPalette(PhysPt data,Bitu index,Bitu count) { //Structure is (vesa 3.0 doc): blue,green,red,alignment Bit8u r,g,b; if (index>255) return VESA_FAIL; if (index+count>256) return VESA_FAIL; IO_Write(0x3c8,(Bit8u)index); while (count) { b = mem_readb(data++); g = mem_readb(data++); r = mem_readb(data++); data++; IO_Write(0x3c9,r); IO_Write(0x3c9,g); IO_Write(0x3c9,b); count--; } return VESA_SUCCESS; }
static int writeError(int status) { IO_Write(CommandRegister, Reset); if (status & VppErrorBit) return FLASH_VPP_ERROR; else if (status & ProgramErrorBit) return FLASH_PROGRAM_ERROR; else if (status & BlockProtectionErrorBit) return FLASH_PROTECTED_BLOCK_ERROR; else return FLASH_UNKNOWN_PROGRAM_ERROR; }
static void EGA16_FillRow(Bit8u cleft,Bit8u cright,Bit8u row,PhysPt base,Bit8u attr) { /* Set Bitmask / Color / Full Set Reset */ IO_Write(0x3ce,0x8);IO_Write(0x3cf,0xff); IO_Write(0x3ce,0x0);IO_Write(0x3cf,attr); IO_Write(0x3ce,0x1);IO_Write(0x3cf,0xf); /* Enable all Write planes */ IO_Write(0x3c4,2);IO_Write(0x3c5,0xf); /* Write some bytes */ Bit8u cheight = real_readb(BIOSMEM_SEG,BIOSMEM_CHAR_HEIGHT); PhysPt dest=base+(CurMode->twidth*row)*cheight+cleft; Bitu nextline=CurMode->twidth; Bitu copy = cheight;Bitu rowsize=(Bitu)(cright-cleft); for (;copy>0;copy--) { for (Bitu x=0;x<rowsize;x++) mem_writeb(dest+x,0xff); dest+=nextline; } IO_Write(0x3cf,0); }
static Bitu INT74_Handler(void) { if (mouse.events>0) { mouse.events--; /* Check for an active Interrupt Handler that will get called */ if (mouse.sub_mask & mouse.event_queue[mouse.events].type) { /* Save lot's of registers */ Bit32u oldeax,oldebx,oldecx,oldedx,oldesi,oldedi,oldebp,oldesp; Bit16u oldds,oldes,oldss; oldeax=reg_eax;oldebx=reg_ebx;oldecx=reg_ecx;oldedx=reg_edx; oldesi=reg_esi;oldedi=reg_edi;oldebp=reg_ebp;oldesp=reg_esp; oldds=SegValue(ds); oldes=SegValue(es); oldss=SegValue(ss); // Save segments reg_ax=mouse.event_queue[mouse.events].type; reg_bx=mouse.event_queue[mouse.events].buttons; reg_cx=POS_X; reg_dx=POS_Y; reg_si=(Bit16s)(mouse.mickey_x*mouse.mickeysPerPixel_x); reg_di=(Bit16s)(mouse.mickey_y*mouse.mickeysPerPixel_y); // Hmm... this look ok, but moonbase wont work with it /*if (mouse.event_queue[mouse.events].type==MOUSE_MOVED) { mouse.mickey_x=0; mouse.mickey_y=0; }*/ CALLBACK_RunRealFar(mouse.sub_seg,mouse.sub_ofs); reg_eax=oldeax;reg_ebx=oldebx;reg_ecx=oldecx;reg_edx=oldedx; reg_esi=oldesi;reg_edi=oldedi;reg_ebp=oldebp;reg_esp=oldesp; SegSet16(ds,oldds); SegSet16(es,oldes); SegSet16(ss,oldss); // Save segments } DoPS2Callback(mouse.event_queue[mouse.events].buttons, POS_X, POS_Y); } IO_Write(0xa0,0x20); IO_Write(0x20,0x20); /* Check for more Events if so reactivate IRQ */ if (mouse.events) { PIC_ActivateIRQ(MOUSE_IRQ); } return CBRET_NONE; }
void SaveVgaRegisters() { if (IS_VGA_ARCH) { for (Bit8u i=0; i<9; i++) { IO_Write (0x3CE,i); gfxReg3CE[i] = IO_Read(0x3CF); } /* Setup some default values in GFX regs that should work */ IO_Write(0x3CE,3); IO_Write(0x3Cf,0); //disable rotate and operation IO_Write(0x3CE,5); IO_Write(0x3Cf,gfxReg3CE[5]&0xf0); //Force read/write mode 0 //Set Map to all planes. Celtic Tales index3C4 = IO_Read(0x3c4); IO_Write(0x3C4,2); gfxReg3C5 = IO_Read(0x3C5); IO_Write(0x3C5,0xF); } else if (machine==MCH_EGA) { //Set Map to all planes. IO_Write(0x3C4,2); IO_Write(0x3C5,0xF); } }
static Bitu INT70_Handler(void) { /* Acknowledge irq with cmos */ IO_Write(0x70,0xc); IO_Read(0x71); if (mem_readb(BIOS_WAIT_FLAG_ACTIVE)) { Bit32u count=mem_readd(BIOS_WAIT_FLAG_COUNT); if (count>997) { mem_writed(BIOS_WAIT_FLAG_COUNT,count-997); } else { mem_writed(BIOS_WAIT_FLAG_COUNT,0); PhysPt where=Real2Phys(mem_readd(BIOS_WAIT_FLAG_POINTER)); mem_writeb(where,mem_readb(where)|0x80); mem_writeb(BIOS_WAIT_FLAG_ACTIVE,0); mem_writed(BIOS_WAIT_FLAG_POINTER,RealMake(0,BIOS_WAIT_FLAG_TEMP)); IO_Write(0x70,0xb); IO_Write(0x71,IO_Read(0x71)&~0x40); } } /* Signal EOI to both pics */ IO_Write(0xa0,0x20); IO_Write(0x20,0x20); return 0; }
int Flash_Write(ioAddress offset, ioData data) { ioData status = 0; uint32_t timestamp = MicroTime_Get(); IO_Write(CommandRegister, ProgramCommand); IO_Write(offset, data); status = IO_Read(StatusRegister); while ((status & ReadyBit) == 0) { if (MicroTime_Get() - timestamp >= FLASH_WRITE_TIMEOUT_IN_MICROSECONDS) return FLASH_TIMEOUT_ERROR; status = IO_Read(StatusRegister); } if (status != ReadyBit) return writeError(status); if (data != IO_Read(offset)) return FLASH_READ_BACK_ERROR; return FLASH_SUCCESS; }
//TODO Maybe use fflush, but that seemed to f**k up in visual c bool localFile::Read(Bit8u * data,Bit16u * size) { if ((this->flags & 0xf) == OPEN_WRITE) { // check if file opened in write-only mode DOS_SetError(DOSERR_ACCESS_DENIED); return false; } if (last_action==WRITE) fseek(fhandle,ftell(fhandle),SEEK_SET); last_action=READ; *size=(Bit16u)fread(data,1,*size,fhandle); /* Fake harddrive motion. Inspector Gadget with soundblaster compatible */ /* Same for Igor */ /* hardrive motion => unmask irq 2. Only do it when it's masked as unmasking is realitively heavy to emulate */ Bit8u mask = IO_Read(0x21); if(mask & 0x4 ) IO_Write(0x21,mask&0xfb); return true; }
Bit8u VESA_GetPalette(PhysPt data,Bitu index,Bitu count) { Bit8u r,g,b; if (index>255) return VESA_FAIL; if (index+count>256) return VESA_FAIL; IO_Write(0x3c7,(Bit8u)index); while (count) { r = IO_Read(0x3c9); g = IO_Read(0x3c9); b = IO_Read(0x3c9); mem_writeb(data++,b); mem_writeb(data++,g); mem_writeb(data++,r); data++; count--; } return VESA_SUCCESS; }
/* check if Tandy DAC is still playing */ static bool Tandy_TransferInProgress(void) { if (real_readw(0x40,0xd0)) return true; /* not yet done */ if (real_readb(0x40,0xd4)==0xff) return false; /* still in init-state */ Bit8u tandy_dma = 1; if (tandy_sb.port) tandy_dma = tandy_sb.dma; else if (tandy_dac.port) tandy_dma = tandy_dac.dma; IO_Write(0x0c,0x00); Bit16u datalen=(Bit8u)(IO_ReadB(tandy_dma*2+1)&0xff); datalen|=(IO_ReadB(tandy_dma*2+1)<<8); if (datalen==0xffff) return false; /* no DMA transfer */ else if ((datalen<0x10) && (real_readb(0x40,0xd4)==0x0f) && (real_readw(0x40,0xd2)==0x1c)) { /* stop already requested */ return false; } return true; }
Bit8u VESA_GetDisplayStart(Bit16u & x,Bit16u & y) { Bitu pixels_per_offset; Bitu panning_factor = 1; switch (CurMode->type) { case M_TEXT: pixels_per_offset = 16; break; case M_LIN4: pixels_per_offset = 16; break; case M_LIN8: panning_factor = 2; pixels_per_offset = 8; break; case M_LIN15: case M_LIN16: panning_factor = 2; pixels_per_offset = 4; break; case M_LIN32: pixels_per_offset = 2; break; default: return VESA_MODE_UNSUPPORTED; } IO_Read(0x3da); // reset attribute flipflop IO_Write(0x3c0,0x13 | 0x20); // panning register, screen on Bit8u panning = IO_Read(0x3c1); Bitu virtual_screen_width = vga.config.scan_len * pixels_per_offset; Bitu start_pixel = vga.config.display_start * (pixels_per_offset/2) + panning / panning_factor; y = start_pixel / virtual_screen_width; x = start_pixel % virtual_screen_width; return VESA_SUCCESS; }
void SVGA_Setup_ParadisePVGA1A(void) { svga.write_p3cf = &write_p3cf_pvga1a; svga.read_p3cf = &read_p3cf_pvga1a; svga.set_video_mode = &FinishSetMode_PVGA1A; svga.determine_mode = &DetermineMode_PVGA1A; svga.set_clock = &SetClock_PVGA1A; svga.get_clock = &GetClock_PVGA1A; svga.accepts_mode = &AcceptsMode_PVGA1A; VGA_SetClock(0,CLK_25); VGA_SetClock(1,CLK_28); VGA_SetClock(2,32400); // could not find documentation VGA_SetClock(3,35900); // Adjust memory, default to 512K if (vga.vmemsize == 0) vga.vmemsize = 512*1024; if (vga.vmemsize < 512*1024) { vga.vmemsize = 256*1024; pvga1a.PR1 = 1<<6; } else if (vga.vmemsize > 512*1024) { vga.vmemsize = 1024*1024; pvga1a.PR1 = 3<<6; } else { pvga1a.PR1 = 2<<6; } // Paradise ROM signature PhysPt rom_base=PhysMake(0xc000,0); phys_writeb(rom_base+0x007d,'V'); phys_writeb(rom_base+0x007e,'G'); phys_writeb(rom_base+0x007f,'A'); phys_writeb(rom_base+0x0080,'='); IO_Write(0x3cf, 0x05); // Enable! }
static void EGA16_CopyRow(Bit8u cleft,Bit8u cright,Bit8u rold,Bit8u rnew,PhysPt base) { PhysPt src,dest;Bitu copy; Bit8u cheight = real_readb(BIOSMEM_SEG,BIOSMEM_CHAR_HEIGHT); dest=base+(CurMode->twidth*rnew)*cheight+cleft; src=base+(CurMode->twidth*rold)*cheight+cleft; Bitu nextline=(Bitu)CurMode->twidth; /* Setup registers correctly */ IO_Write(0x3ce,5);IO_Write(0x3cf,1); /* Memory transfer mode */ IO_Write(0x3c4,2);IO_Write(0x3c5,0xf); /* Enable all Write planes */ /* Do some copying */ Bitu rowsize=(Bitu)(cright-cleft); copy=cheight; for (;copy>0;copy--) { for (Bitu x=0;x<rowsize;x++) mem_writeb(dest+x,mem_readb(src+x)); dest+=nextline;src+=nextline; } /* Restore registers */ IO_Write(0x3ce,5);IO_Write(0x3cf,0); /* Normal transfer mode */ }
Bitu XMS_EnableA20(bool enable) { Bit8u val = IO_Read (0x92); if (enable) IO_Write(0x92,val | 2); else IO_Write(0x92,val & ~2); return 0; }
int CT_data( unsigned int ctn, unsigned char *dad, unsigned char *sad, unsigned int lc, const unsigned char *cmd, unsigned int *lr, unsigned char *rsp ) { int IretVal; unsigned char ack_byte; /* READER COMMAND */ if (*dad == 1) { /* This command goes to the reader */ *sad = 1; /* Data is going from reader (1) to host (2) */ *dad = 2; /*******************/ /* CT-BCS Commands */ /*******************/ /* Reset - Reset the card and return ATR */ if (cmd[0] == 0x20 && cmd[1] == 0x11) { if (IO_RF2SC_Reset () == FALSE) IretVal = ERR_TRANS; else { /* Read the ATR. */ *lr = IO_Read2 (*lr, rsp); rsp[*lr] = 0x90; rsp[*lr+1] = 0x00; *lr += 2; IretVal = OK; } } /* Request ICC - Turn on reader/card */ else if (cmd[0] == 0x20 && cmd[1] == 0x12) { /* Just turn on the clock */ IO_RF2SC_EN_CLK (TRUE); *lr = 0; IretVal = OK; } /* Eject ICC - Turn off card's clock & Reset Low */ else if (cmd[0] == 0x20 && cmd[1] == 0x15) { reset_low(); /* Reset Low smart card*/ IO_RF2SC_EN_CLK (FALSE); /* Stop clock */ *lr = 0; IretVal = OK; } /* Get Card Status, ICC status Data Object (DO) */ else if (cmd[0] == 0x20 && cmd[1] == 0x13) { if (IO_RF2SC_IsCardInserted ()) *rsp = 5; /* card is present and electrically connected */ else *rsp = 0; /* card not present */ *lr = 1; IretVal = OK; } /* Command sent directly to the card */ else { /* Don't do anything.. */ *lr = 0; IretVal = OK; } } /* CARD COMMAND */ else if (*dad == 0) { /* This command goes to the card */ BYTE sw1, sw2; BYTE get_response[5]; int i, max_len; /* printf("sending command to card... len %d\n", lc); */ *sad = 0; /* Card (0) --> Host (2) */ *dad = 2; IretVal = OK; /* Algoritmo T = 0 implementado como indica el libro Smart Card Handbook 3rd edition, * Autores Rankl & Effing. Chapter 6, Smart Card data transmission, page 403 */ /* Send the command (first five bytes) */ for (i = 0; i < 5; i++) if (!IO_Write (cmd[i])) { IretVal = ERR_TRANS; break; } max_len = *lr; /* Read the card's ACK byte */ *lr = IO_Read (1, &ack_byte); //printf("\nACK de la tarjeta: %02X\n", ack_byte); /*Si el byte ACK de la tarjeta es igual al byte INS mando el resto del comando*/ if (ack_byte == cmd[1]) { /* Send the rest of the command */ for (i = 5; i < lc; i++) { if (!IO_Write (cmd[i])) { IretVal = ERR_TRANS; break; } } IO_Read (1, &sw1); IO_Read (1, &sw2); } else { sw1 = ack_byte; IO_Read (1, &sw2); } //printf("SW1: %02X, SW2: %02X\n", sw1, sw2); switch(sw1){ case 0x90: rsp[0] = sw1; rsp[1] = sw2; *lr = 2; break; case 0x6c: memcpy(get_response, cmd, 5); get_response[4] = sw2; for (i = 0; i < 5; i++) if (!IO_Write (get_response[i])) { IretVal = ERR_TRANS; break; } /* Read the card's second response, if something was sent */ /* CHECK: can there be anything here more than two bytes if it was a long command above? */ *lr = IO_Read (1, &ack_byte); //printf("\nACK de la tarjeta: %02X\n", ack_byte); *lr = IO_Read2 (max_len, rsp); break; default: rsp[0] = sw1; rsp[1] = sw2; *lr = 2; break; } } else { /* This command goes nowhere because the dest. is invalid */ IretVal = ERR_INVALID; } if (IretVal != OK) *lr = 0; return IretVal; }
void FinishSetMode_PVGA1A(Bitu /*crtc_base*/, VGA_ModeExtraData* modeData) { pvga1a.biosMode = modeData->modeNo; // Reset to single bank and set it to 0. May need to unlock first (DPaint locks on exit) IO_Write(0x3ce, 0x0f); Bitu oldlock = IO_Read(0x3cf); IO_Write(0x3cf, 0x05); IO_Write(0x3ce, 0x09); IO_Write(0x3cf, 0x00); IO_Write(0x3ce, 0x0a); IO_Write(0x3cf, 0x00); IO_Write(0x3ce, 0x0b); Bit8u val = IO_Read(0x3cf); IO_Write(0x3cf, val & ~0x08); IO_Write(0x3ce, 0x0c); IO_Write(0x3cf, 0x00); IO_Write(0x3ce, 0x0d); IO_Write(0x3cf, 0x00); IO_Write(0x3ce, 0x0e); IO_Write(0x3cf, 0x00); IO_Write(0x3ce, 0x0f); IO_Write(0x3cf, oldlock); if (svga.determine_mode) svga.determine_mode(); if(vga.mode != M_VGA) { vga.config.compatible_chain4 = false; vga.vmemwrap = vga.vmemsize; } else { vga.config.compatible_chain4 = true; vga.vmemwrap = 256*1024; } vga.config.compatible_chain4 = false; VGA_SetupHandlers(); }
int Flash_Write(ioAddress address, ioData data) { IO_Write(0x40, 0); return -1; }
static void Tandy_SetupTransfer(PhysPt bufpt,bool isplayback) { Bitu length=real_readw(0x40,0xd0); if (length==0) return; /* nothing to do... */ if ((tandy_sb.port==0) && (tandy_dac.port==0)) return; Bit8u tandy_irq = 7; if (tandy_sb.port) tandy_irq = tandy_sb.irq; else if (tandy_dac.port) tandy_irq = tandy_dac.irq; Bit8u tandy_irq_vector = tandy_irq; if (tandy_irq_vector<8) tandy_irq_vector += 8; else tandy_irq_vector += (0x70-8); /* revector IRQ-handler if necessary */ RealPt current_irq=RealGetVec(tandy_irq_vector); if (current_irq!=tandy_DAC_callback[0]->Get_RealPointer()) { real_writed(0x40,0xd6,current_irq); RealSetVec(tandy_irq_vector,tandy_DAC_callback[0]->Get_RealPointer()); } Bit8u tandy_dma = 1; if (tandy_sb.port) tandy_dma = tandy_sb.dma; else if (tandy_dac.port) tandy_dma = tandy_dac.dma; if (tandy_sb.port) { IO_Write(tandy_sb.port+0xc,0xd0); /* stop DMA transfer */ IO_Write(0x21,IO_Read(0x21)&(~(1<<tandy_irq))); /* unmask IRQ */ IO_Write(tandy_sb.port+0xc,0xd1); /* turn speaker on */ } else { IO_Write(tandy_dac.port,IO_Read(tandy_dac.port)&0x60); /* disable DAC */ IO_Write(0x21,IO_Read(0x21)&(~(1<<tandy_irq))); /* unmask IRQ */ } IO_Write(0x0a,0x04|tandy_dma); /* mask DMA channel */ IO_Write(0x0c,0x00); /* clear DMA flipflop */ if (isplayback) IO_Write(0x0b,0x48|tandy_dma); else IO_Write(0x0b,0x44|tandy_dma); /* set physical address of buffer */ Bit8u bufpage=(Bit8u)((bufpt>>16)&0xff); IO_Write(tandy_dma*2,(Bit8u)(bufpt&0xff)); IO_Write(tandy_dma*2,(Bit8u)((bufpt>>8)&0xff)); switch (tandy_dma) { case 0: IO_Write(0x87,bufpage); break; case 1: IO_Write(0x83,bufpage); break; case 2: IO_Write(0x81,bufpage); break; case 3: IO_Write(0x82,bufpage); break; } real_writeb(0x40,0xd4,bufpage); /* calculate transfer size (respects segment boundaries) */ Bit32u tlength=length; if (tlength+(bufpt&0xffff)>0x10000) tlength=0x10000-(bufpt&0xffff); real_writew(0x40,0xd0,(Bit16u)(length-tlength)); /* remaining buffer length */ tlength--; /* set transfer size */ IO_Write(tandy_dma*2+1,(Bit8u)(tlength&0xff)); IO_Write(tandy_dma*2+1,(Bit8u)((tlength>>8)&0xff)); Bit16u delay=(Bit16u)(real_readw(0x40,0xd2)&0xfff); Bit8u amplitude=(Bit8u)((real_readw(0x40,0xd2)>>13)&0x7); if (tandy_sb.port) { IO_Write(0x0a,tandy_dma); /* enable DMA channel */ /* set frequency */ IO_Write(tandy_sb.port+0xc,0x40); IO_Write(tandy_sb.port+0xc,256-delay*100/358); /* set playback type to 8bit */ if (isplayback) IO_Write(tandy_sb.port+0xc,0x14); else IO_Write(tandy_sb.port+0xc,0x24); /* set transfer size */ IO_Write(tandy_sb.port+0xc,(Bit8u)(tlength&0xff)); IO_Write(tandy_sb.port+0xc,(Bit8u)((tlength>>8)&0xff)); } else {
Bit8u VESA_GetCPUWindow(Bit8u window,Bit16u & address) { if (window) return VESA_FAIL; IO_Write(0x3d4,0x6a); address=IO_Read(0x3d5); return VESA_SUCCESS; }
void MENU_KeyDelayRate(int delay, int rate) { IO_Write(0x60,0xf3); IO_Write(0x60,(Bit8u)(((delay-1)<<5)|(32-rate))); LOG_MSG("GUI: Keyboard rate %d, delay %d", rate, delay); }