/*
* This function disables a logical channel.
*
* @param channel Input parameter for the logical channel ID.
*
* @param wait_for_stop Flag to set whether to wait for channel end
* of frame or return immediately.
*
* @return This function returns 0 on success or negative error code on
* fail.
*/
int32_t ipu_disable_channel(ipu_channel_t channel)
{
uint32_t reg;
uint32_t in_dma;
uint32_t out_dma;
if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
debug("Channel already disabled %d\n",
IPU_CHAN_ID(channel));
return 0;
}
/* Get input and output dma channels */
out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
if ((idma_is_valid(in_dma) &&
!idma_is_set(IDMAC_CHA_EN, in_dma))
&& (idma_is_valid(out_dma) &&
!idma_is_set(IDMAC_CHA_EN, out_dma)))
return -EINVAL;
if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
(channel == MEM_DC_SYNC)) {
ipu_dp_dc_disable(channel, 0);
}
/* Disable DMA channel(s) */
if (idma_is_valid(in_dma)) {
reg = __raw_readl(IDMAC_CHA_EN(in_dma));
__raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
__raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
}
if (idma_is_valid(out_dma)) {
reg = __raw_readl(IDMAC_CHA_EN(out_dma));
__raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
__raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
}
g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
/* Set channel buffers NOT to be ready */
if (idma_is_valid(in_dma)) {
ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
}
if (idma_is_valid(out_dma)) {
ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
}
return 0;
}
/*
* This function is called to initialize a buffer for logical IPU channel.
*
* @param channel Input parameter for the logical channel ID.
*
* @param type Input parameter which buffer to initialize.
*
* @param pixel_fmt Input parameter for pixel format of buffer.
* Pixel format is a FOURCC ASCII code.
*
* @param width Input parameter for width of buffer in pixels.
*
* @param height Input parameter for height of buffer in pixels.
*
* @param stride Input parameter for stride length of buffer
* in pixels.
*
* @param phyaddr_0 Input parameter buffer 0 physical address.
*
* @param phyaddr_1 Input parameter buffer 1 physical address.
* Setting this to a value other than NULL enables
* double buffering mode.
*
* @param u private u offset for additional cropping,
* zero if not used.
*
* @param v private v offset for additional cropping,
* zero if not used.
*
* @return Returns 0 on success or negative error code on fail
*/
int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
uint32_t pixel_fmt,
uint16_t width, uint16_t height,
uint32_t stride,
dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
uint32_t u, uint32_t v)
{
uint32_t reg;
uint32_t dma_chan;
dma_chan = channel_2_dma(channel, type);
if (!idma_is_valid(dma_chan))
return -EINVAL;
if (stride < width * bytes_per_pixel(pixel_fmt))
stride = width * bytes_per_pixel(pixel_fmt);
if (stride % 4) {
printf(
"Stride not 32-bit aligned, stride = %d\n", stride);
return -EINVAL;
}
/* Build parameter memory data for DMA channel */
ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
phyaddr_0, phyaddr_1);
if (ipu_is_dmfc_chan(dma_chan)) {
ipu_dmfc_set_wait4eot(dma_chan, width);
}
if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
ipu_ch_param_set_high_priority(dma_chan);
ipu_ch_param_dump(dma_chan);
reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
if (phyaddr_1)
reg |= idma_mask(dma_chan);
else
reg &= ~idma_mask(dma_chan);
__raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
/* Reset to buffer 0 */
__raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
return 0;
}
void ipu_dump()
{
ipu_dump_registers();
printk(KERN_INFO "IPU_INT_STAT_1 = \t0x%08X\n", __raw_readl(IPU_STAT));
printk(KERN_INFO "IPU_INT_CTRL_1 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(1)));
printk(KERN_INFO "IPU_INT_CTRL_2 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(2)));
printk(KERN_INFO "IPU_INT_CTRL_3 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(3)));
printk(KERN_INFO "IPU_INT_CTRL_4 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(4)));
printk(KERN_INFO "IPU_INT_CTRL_5 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(5)));
printk(KERN_INFO "IPU_INT_CTRL_6 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(6)));
printk(KERN_INFO "IPU_INT_CTRL_7 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(7)));
printk(KERN_INFO "IPU_INT_CTRL_8 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(8)));
printk(KERN_INFO "IPU_INT_CTRL_9 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(9)));
printk(KERN_INFO "IPU_INT_CTRL_10 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(10)));
printk(KERN_INFO "IPU_INT_CTRL_11 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(11)));
printk(KERN_INFO "IPU_INT_CTRL_12 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(12)));
printk(KERN_INFO "IPU_INT_CTRL_13 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(13)));
printk(KERN_INFO "IPU_INT_CTRL_14 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(14)));
printk(KERN_INFO "IPU_INT_CTRL_15 = \t0x%08X\n", __raw_readl(IPU_INT_CTRL(15)));
printk(KERN_INFO "IPU_INT_STAT_1 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(1)));
printk(KERN_INFO "IPU_INT_STAT_2 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(2)));
printk(KERN_INFO "IPU_INT_STAT_3 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(3)));
printk(KERN_INFO "IPU_INT_STAT_4 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(4)));
printk(KERN_INFO "IPU_INT_STAT_5 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(5)));
printk(KERN_INFO "IPU_INT_STAT_6 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(6)));
printk(KERN_INFO "IPU_INT_STAT_7 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(7)));
printk(KERN_INFO "IPU_INT_STAT_8 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(8)));
printk(KERN_INFO "IPU_INT_STAT_9 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(9)));
printk(KERN_INFO "IPU_INT_STAT_10 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(10)));
printk(KERN_INFO "IPU_INT_STAT_11 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(11)));
printk(KERN_INFO "IPU_INT_STAT_12 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(12)));
printk(KERN_INFO "IPU_INT_STAT_13 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(13)));
printk(KERN_INFO "IPU_INT_STAT_14 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(14)));
printk(KERN_INFO "IPU_INT_STAT_15 = \t0x%08X\n", __raw_readl(IPU_INT_STAT(15)));
printk(KERN_INFO "IPU_CHA_BUF0_RDY(27) = \t0x%08X\n", __raw_readl(IPU_CHA_BUF0_RDY(27)));
printk(KERN_INFO "IPU_CHA_BUF0_RDY(23) = \t0x%08X\n", __raw_readl(IPU_CHA_BUF0_RDY(23)));
printk(KERN_INFO "IPU_CHA_CUR_BUF(27) = \t0x%08X\n", __raw_readl(IPU_CHA_CUR_BUF(27)));
printk(KERN_INFO "IDMAC_CH_BUSY1(27) = \t0x%08X\n", __raw_readl(IDMAC_CH_BUSY1));
ipu_ch_param_dump(23);
ipu_ch_param_dump(27);
ipu_ch_param_dump(15);
ipu_ch_param_dump(20);
ipu_ch_param_dump(0);
}
