static int spi_qmsi_init(struct device *dev)
{
struct spi_qmsi_config *spi_config = dev->config->config_info;
struct spi_qmsi_runtime *context = dev->driver_data;
dev->driver_api = &spi_qmsi_api;
switch (spi_config->spi) {
case QM_SPI_MST_0:
IRQ_CONNECT(CONFIG_SPI_QMSI_PORT_0_IRQ,
CONFIG_SPI_QMSI_PORT_0_PRI, qm_spi_master_0_isr,
0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(CONFIG_SPI_QMSI_PORT_0_IRQ);
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M0_REGISTER);
QM_SCSS_INT->int_spi_mst_0_mask &= ~BIT(0);
break;
case QM_SPI_MST_1:
IRQ_CONNECT(CONFIG_SPI_QMSI_PORT_1_IRQ,
CONFIG_SPI_QMSI_PORT_1_PRI, qm_spi_master_1_isr,
0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(CONFIG_SPI_QMSI_PORT_1_IRQ);
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M1_REGISTER);
QM_SCSS_INT->int_spi_mst_1_mask &= ~BIT(0);
break;
default:
return DEV_FAIL;
}
context->gpio_cs = gpio_cs_init(spi_config);
device_sync_call_init(&context->sync);
return DEV_OK;
}
HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, HwiP_Params *params)
{
HwiP_Handle handle = 0;
uint32_t priority = ~0;
uintptr_t arg = 0;
if (params) {
priority = params->priority;
arg = params->arg;
}
/*
* SimpleLink only uses the NWPIC, UDMA, UDMAERR and LSPI interrupts:
*/
__ASSERT(INT_NWPIC == interruptNum || INT_UDMA == interruptNum ||
INT_UDMAERR == interruptNum || INT_LSPI == interruptNum,
"Unexpected interruptNum: %d\r\n",
interruptNum);
/*
* Priority expected is either:
* INT_PRIORITY_LVL_1,
* or ~0 or 255 (meaning lowest priority)
* ~0 and 255 are meant to be the same as INT_PRIORITY_LVL_7.
* For ~0 or 255, we want 7; but Zephyr IRQ_CONNECT adds +1,
* so we pass 6 for those TI drivers passing prio = ~0.
*/
__ASSERT((INT_PRIORITY_LVL_1 == priority) ||
(0xff == (priority & 0xff)),
"Expected priority: 0x%x or 0x%x, got: 0x%x\r\n",
INT_PRIORITY_LVL_1, 0xff, priority);
switch(interruptNum) {
case INT_UDMA:
sl_UDMA_cb.cb = hwiFxn;
sl_UDMA_cb.arg = arg;
IRQ_CONNECT(EXCEPTION_UDMA, 6, sl_isr, &sl_UDMA_cb, 0);
break;
case INT_UDMAERR:
sl_UDMAERR_cb.cb = hwiFxn;
sl_UDMAERR_cb.arg = arg;
IRQ_CONNECT(EXCEPTION_UDMAERR, 6, sl_isr, &sl_UDMAERR_cb, 0);
break;
case INT_NWPIC:
sl_NWPIC_cb.cb = hwiFxn;
sl_NWPIC_cb.arg = arg;
IRQ_CONNECT(EXCEPTION_NWPIC, 1, sl_isr, &sl_NWPIC_cb, 0);
break;
case INT_LSPI:
sl_LSPI_cb.cb = hwiFxn;
sl_LSPI_cb.arg = arg;
IRQ_CONNECT(EXCEPTION_LSPI, 6, sl_isr, &sl_LSPI_cb, 0);
break;
default:
return(handle);
}
irq_enable(interruptNum - 16);
return (HwiP_Handle)interruptNum;
}
static void i2c_stm32_irq_config_func_4(struct device *dev)
{
IRQ_CONNECT(DT_I2C_4_EVENT_IRQ, DT_I2C_4_EVENT_IRQ_PRI,
stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_4), 0);
irq_enable(DT_I2C_4_EVENT_IRQ);
IRQ_CONNECT(DT_I2C_4_ERROR_IRQ, DT_I2C_4_ERROR_IRQ_PRI,
stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_4), 0);
irq_enable(DT_I2C_4_ERROR_IRQ);
}
static int i2c_qmsi_init(struct device *dev)
{
struct i2c_qmsi_driver_data *driver_data = GET_DRIVER_DATA(dev);
const struct i2c_qmsi_config_info *config = dev->config->config_info;
qm_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
u32_t bitrate_cfg;
int err;
k_sem_init(&driver_data->device_sync_sem, 0, UINT_MAX);
k_sem_init(&driver_data->sem, 1, UINT_MAX);
switch (instance) {
case QM_I2C_0:
/* Register interrupt handler, unmask IRQ and route it
* to Lakemont core.
*/
IRQ_CONNECT(CONFIG_I2C_0_IRQ,
CONFIG_I2C_0_IRQ_PRI, qm_i2c_0_irq_isr, NULL,
CONFIG_I2C_0_IRQ_FLAGS);
irq_enable(CONFIG_I2C_0_IRQ);
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->i2c_master_0_int_mask);
break;
#ifdef CONFIG_I2C_1
case QM_I2C_1:
IRQ_CONNECT(CONFIG_I2C_1_IRQ,
CONFIG_I2C_1_IRQ_PRI, qm_i2c_1_irq_isr, NULL,
CONFIG_I2C_1_IRQ_FLAGS);
irq_enable(CONFIG_I2C_1_IRQ);
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->i2c_master_1_int_mask);
break;
#endif /* CONFIG_I2C_1 */
default:
return -EIO;
}
clk_periph_enable(config->clock_gate);
bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
err = i2c_qmsi_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (err < 0) {
return err;
}
dev->driver_api = &api;
i2c_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
return 0;
}
static void dma_qmsi_config(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_0), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_0, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_0));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_0_mask);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_1), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_1, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_1));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_1_mask);
#if (CONFIG_SOC_QUARK_SE_C1000)
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_2), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_2, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_2));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_2_mask);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_3), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_3, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_3));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_3_mask);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_4), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_4, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_4));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_4_mask);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_5), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_5, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_5));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_5_mask);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_6), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_6, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_6));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_6_mask);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_7), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_7, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_7));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_7_mask);
#endif /* CONFIG_SOC_QUARK_SE_C1000 */
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_ERROR_INT),
CONFIG_DMA_0_IRQ_PRI, qm_dma_0_error_isr,
DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_ERROR_INT));
#if (QM_LAKEMONT)
QM_INTERRUPT_ROUTER->dma_0_error_int_mask &= ~QM_IR_DMA_ERROR_HOST_MASK;
#elif (QM_SENSOR)
QM_INTERRUPT_ROUTER->dma_0_error_int_mask &= ~QM_IR_DMA_ERROR_SS_MASK;
#endif
}
static void usart_gecko_config_func_3(struct device *dev)
{
IRQ_CONNECT(DT_SILABS_GECKO_USART_3_IRQ_RX,
DT_SILABS_GECKO_USART_3_IRQ_RX_PRIORITY,
uart_gecko_isr, DEVICE_GET(usart_3), 0);
IRQ_CONNECT(DT_SILABS_GECKO_USART_3_IRQ_TX,
DT_SILABS_GECKO_USART_3_IRQ_TX_PRIORITY,
uart_gecko_isr, DEVICE_GET(usart_3), 0);
irq_enable(DT_SILABS_GECKO_USART_3_IRQ_RX);
irq_enable(DT_SILABS_GECKO_USART_3_IRQ_TX);
}
static int mcux_igpio_5_init(struct device *dev)
{
IRQ_CONNECT(DT_MCUX_IGPIO_5_IRQ_0, DT_MCUX_IGPIO_5_IRQ_0_PRI,
mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_5), 0);
irq_enable(DT_MCUX_IGPIO_5_IRQ_0);
IRQ_CONNECT(DT_MCUX_IGPIO_5_IRQ_1, DT_MCUX_IGPIO_5_IRQ_1_PRI,
mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_5), 0);
irq_enable(DT_MCUX_IGPIO_5_IRQ_1);
return 0;
}
static void uart_mcux_config_func_5(struct device *dev)
{
IRQ_CONNECT(CONFIG_UART_MCUX_5_IRQ_STATUS,
CONFIG_UART_MCUX_5_IRQ_STATUS_PRI,
uart_mcux_isr, DEVICE_GET(uart_5), 0);
irq_enable(CONFIG_UART_MCUX_5_IRQ_STATUS);
IRQ_CONNECT(CONFIG_UART_MCUX_5_IRQ_ERROR,
CONFIG_UART_MCUX_5_IRQ_ERROR_PRI,
uart_mcux_isr, DEVICE_GET(uart_5), 0);
irq_enable(CONFIG_UART_MCUX_5_IRQ_ERROR);
}
static void uart_mcux_config_func_5(struct device *dev)
{
IRQ_CONNECT(IRQ_UART5_STATUS, CONFIG_UART_MCUX_5_IRQ_PRI,
uart_mcux_isr, DEVICE_GET(uart_5), 0);
irq_enable(IRQ_UART5_STATUS);
#ifdef IRQ_UART5_ERROR
IRQ_CONNECT(IRQ_UART5_ERROR, CONFIG_UART_MCUX_5_IRQ_PRI,
uart_mcux_isr, DEVICE_GET(uart_5), 0);
irq_enable(IRQ_UART5_ERROR);
#endif
}
static int mcux_igpio_4_init(struct device *dev)
{
IRQ_CONNECT(CONFIG_MCUX_IGPIO_4_IRQ_0, CONFIG_MCUX_IGPIO_4_IRQ_0_PRI,
mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_4), 0);
irq_enable(CONFIG_MCUX_IGPIO_4_IRQ_0);
IRQ_CONNECT(CONFIG_MCUX_IGPIO_4_IRQ_1, CONFIG_MCUX_IGPIO_4_IRQ_1_PRI,
mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_4), 0);
irq_enable(CONFIG_MCUX_IGPIO_4_IRQ_1);
return 0;
}
static void timer_cmsdk_apb_config_1(struct device *dev)
{
IRQ_CONNECT(CMSDK_APB_TIMER_1_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_1_IRQ_PRI,
timer_tmr_cmsdk_apb_isr,
DEVICE_GET(timer_tmr_cmsdk_apb_0), 0);
irq_enable(CMSDK_APB_TIMER_1_IRQ);
}
static void nrf5_config(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(NRF5_IRQ_RADIO_IRQn, 0, nrf5_radio_irq, NULL, 0);
irq_enable(NRF5_IRQ_RADIO_IRQn);
}
static void i2c_mcux_config_func_1(struct device *dev)
{
IRQ_CONNECT(CONFIG_I2C_MCUX_1_IRQ, CONFIG_I2C_MCUX_1_IRQ_PRI,
i2c_mcux_isr, DEVICE_GET(i2c_mcux_1), 0);
irq_enable(CONFIG_I2C_MCUX_1_IRQ);
}
static void mcux_adc16_config_func_1(struct device *dev)
{
IRQ_CONNECT(CONFIG_ADC_1_IRQ, CONFIG_ADC_1_IRQ_PRI,
mcux_adc16_isr, DEVICE_GET(mcux_adc16_1), 0);
irq_enable(CONFIG_ADC_1_IRQ);
}
int z_clock_driver_init(struct device *device)
{
extern int z_clock_hw_cycles_per_sec;
u32_t hz;
IRQ_CONNECT(CONFIG_HPET_TIMER_IRQ, CONFIG_HPET_TIMER_IRQ_PRIORITY,
hpet_isr, 0, 0);
set_timer0_irq(CONFIG_HPET_TIMER_IRQ);
irq_enable(CONFIG_HPET_TIMER_IRQ);
/* CLK_PERIOD_REG is in femtoseconds (1e-15 sec) */
hz = (u32_t)(1000000000000000ull / CLK_PERIOD_REG);
z_clock_hw_cycles_per_sec = hz;
cyc_per_tick = hz / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
/* Note: we set the legacy routing bit, because otherwise
* nothing in Zephyr disables the PIT which then fires
* interrupts into the same IRQ. But that means we're then
* forced to use IRQ2 contra the way the kconfig IRQ selection
* is supposed to work. Should fix this.
*/
GENERAL_CONF_REG |= GCONF_LR | GCONF_ENABLE;
TIMER0_CONF_REG &= ~TCONF_PERIODIC;
TIMER0_CONF_REG |= TCONF_MODE32;
max_ticks = (0x7fffffff - cyc_per_tick) / cyc_per_tick;
last_count = MAIN_COUNTER_REG;
TIMER0_CONF_REG |= TCONF_INT_ENABLE;
TIMER0_COMPARATOR_REG = MAIN_COUNTER_REG + cyc_per_tick;
return 0;
}
static void i2c_stm32_irq_config_func_2(struct device *dev)
{
#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
IRQ_CONNECT(DT_I2C_2_COMBINED_IRQ, DT_I2C_2_COMBINED_IRQ_PRI,
stm32_i2c_combined_isr, DEVICE_GET(i2c_stm32_2), 0);
irq_enable(DT_I2C_2_COMBINED_IRQ);
#else
IRQ_CONNECT(DT_I2C_2_EVENT_IRQ, DT_I2C_2_EVENT_IRQ_PRI,
stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_2), 0);
irq_enable(DT_I2C_2_EVENT_IRQ);
IRQ_CONNECT(DT_I2C_2_ERROR_IRQ, DT_I2C_2_ERROR_IRQ_PRI,
stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_2), 0);
irq_enable(DT_I2C_2_ERROR_IRQ);
#endif
}
int z_clock_driver_init(struct device *device)
{
struct device *clock;
ARG_UNUSED(device);
clock = device_get_binding(CONFIG_CLOCK_CONTROL_NRF_K32SRC_DRV_NAME);
if (!clock) {
return -1;
}
clock_control_on(clock, (void *)CLOCK_CONTROL_NRF_K32SRC);
/* TODO: replace with counter driver to access RTC */
nrf_rtc_prescaler_set(RTC, 0);
nrf_rtc_cc_set(RTC, 0, CYC_PER_TICK);
nrf_rtc_event_enable(RTC, RTC_EVTENSET_COMPARE0_Msk);
nrf_rtc_int_enable(RTC, RTC_INTENSET_COMPARE0_Msk);
/* Clear the event flag and possible pending interrupt */
nrf_rtc_event_clear(RTC, NRF_RTC_EVENT_COMPARE_0);
NVIC_ClearPendingIRQ(RTC1_IRQn);
IRQ_CONNECT(RTC1_IRQn, 1, rtc1_nrf_isr, 0, 0);
irq_enable(RTC1_IRQn);
nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);
if (!IS_ENABLED(TICKLESS_KERNEL)) {
set_comparator(counter() + CYC_PER_TICK);
}
return 0;
}
static int init_wdt(struct device *dev)
{
nrfx_err_t err_code;
/* Set default values. They will be overwritten by setup function. */
const nrfx_wdt_config_t config = {
.behaviour = NRF_WDT_BEHAVIOUR_RUN_SLEEP_HALT,
.reload_value = 2000
};
ARG_UNUSED(dev);
err_code = nrfx_wdt_init(&config, wdt_event_handler);
if (err_code != NRFX_SUCCESS) {
return -EBUSY;
}
IRQ_CONNECT(DT_NORDIC_NRF_WATCHDOG_WDT_0_IRQ,
DT_NORDIC_NRF_WATCHDOG_WDT_0_IRQ_PRIORITY,
nrfx_isr, nrfx_wdt_irq_handler, 0);
irq_enable(DT_NORDIC_NRF_WATCHDOG_WDT_0_IRQ);
return 0;
}
DEVICE_AND_API_INIT(wdt_nrf, DT_NORDIC_NRF_WATCHDOG_WDT_0_LABEL, init_wdt,
NULL, NULL, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_nrf_api);
static void uart_cmsdk_apb_irq_config_func_4(struct device *dev)
{
IRQ_CONNECT(DT_ARM_CMSDK_UART_4_IRQ_TX,
DT_ARM_CMSDK_UART_4_IRQ_TX_PRIORITY,
uart_cmsdk_apb_isr,
DEVICE_GET(uart_cmsdk_apb_4),
0);
irq_enable(DT_ARM_CMSDK_UART_4_IRQ_TX);
IRQ_CONNECT(DT_ARM_CMSDK_UART_4_IRQ_RX,
DT_ARM_CMSDK_UART_4_IRQ_RX_PRIORITY,
uart_cmsdk_apb_isr,
DEVICE_GET(uart_cmsdk_apb_4),
0);
irq_enable(DT_ARM_CMSDK_UART_4_IRQ_RX);
}
/**
*
* @brief Initialize and enable the system clock
*
* This routine is used to program the timer to deliver interrupts at the
* rate specified via the 'sys_clock_us_per_tick' global variable.
*
* @return 0
*/
int _sys_clock_driver_init(struct device *device)
{
ARG_UNUSED(device);
/* determine the timer counter value (in timer clock cycles/system tick)
*/
cycles_per_tick = sys_clock_hw_cycles_per_tick;
tickless_idle_init();
divide_configuration_register_set();
initial_count_register_set(cycles_per_tick - 1);
periodic_mode_set();
IRQ_CONNECT(CONFIG_LOAPIC_TIMER_IRQ, CONFIG_LOAPIC_TIMER_IRQ_PRIORITY,
_timer_int_handler, 0, 0);
/* Everything has been configured. It is now safe to enable the
* interrupt
*/
irq_enable(CONFIG_LOAPIC_TIMER_IRQ);
return 0;
}
static void uart_cmsdk_apb_irq_config_func_4(struct device *dev)
{
IRQ_CONNECT(CMSDK_APB_UART_4_IRQ_TX,
CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI,
uart_cmsdk_apb_isr,
DEVICE_GET(uart_cmsdk_apb_4),
0);
irq_enable(CMSDK_APB_UART_4_IRQ_TX);
IRQ_CONNECT(CMSDK_APB_UART_4_IRQ_RX,
CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI,
uart_cmsdk_apb_isr,
DEVICE_GET(uart_cmsdk_apb_4),
0);
irq_enable(CMSDK_APB_UART_4_IRQ_RX);
}
static int comp_init(struct td_device *dev)
{
int i;
struct cmp_cb *cmp_cb_tmp = (struct cmp_cb *)dev->priv;
for (i = 0; i < CMP_COUNT; i++) {
cmp_cb_tmp[i].cb = NULL;
cmp_cb_tmp[i].cb_data = NULL;
}
dev->priv = cmp_cb_tmp;
#ifdef CONFIG_QUARK
MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE,
INT_COMPARATORS_HOST_MASK) |=
INT_COMPARATORS_MASK;
#elif CONFIG_ARC
MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE, INT_COMPARATORS_SS_MASK) |=
INT_COMPARATORS_MASK;
#endif
MMIO_REG_VAL(CMP_STAT_CLR) |= INT_COMPARATORS_MASK;
MMIO_REG_VAL(CMP_EN) &= ~(INT_COMPARATORS_MASK);
MMIO_REG_VAL(CMP_PWR) &= ~(INT_COMPARATORS_MASK);
/* enable interrupt trap for comparator driver */
IRQ_CONNECT(SOC_CMP_INTERRUPT, ISR_DEFAULT_PRIO, comp_isr, NULL, 0);
irq_enable(SOC_CMP_INTERRUPT);
return 0;
}
static int entropy_nrf5_init(struct device *device)
{
/* Check if this API is called on correct driver instance. */
__ASSERT_NO_MSG(&entropy_nrf5_data == DEV_DATA(device));
/* Locking semaphore initialized to 1 (unlocked) */
k_sem_init(&entropy_nrf5_data.sem_lock, 1, 1);
/* Synching semaphore */
k_sem_init(&entropy_nrf5_data.sem_sync, 0, 1);
rng_pool_init((struct rng_pool *)(entropy_nrf5_data.thr),
CONFIG_ENTROPY_NRF5_THR_POOL_SIZE,
CONFIG_ENTROPY_NRF5_THR_THRESHOLD);
rng_pool_init((struct rng_pool *)(entropy_nrf5_data.isr),
CONFIG_ENTROPY_NRF5_ISR_POOL_SIZE,
CONFIG_ENTROPY_NRF5_ISR_THRESHOLD);
/* Enable or disable bias correction */
if (IS_ENABLED(CONFIG_ENTROPY_NRF5_BIAS_CORRECTION)) {
nrf_rng_error_correction_enable();
} else {
nrf_rng_error_correction_disable();
}
nrf_rng_event_clear(NRF_RNG_EVENT_VALRDY);
nrf_rng_int_enable(NRF_RNG_INT_VALRDY_MASK);
nrf_rng_task_trigger(NRF_RNG_TASK_START);
IRQ_CONNECT(RNG_IRQn, CONFIG_ENTROPY_NRF5_PRI, isr,
&entropy_nrf5_data, 0);
irq_enable(RNG_IRQn);
return 0;
}
static int arc_quark_se_ipm_init(void)
{
IRQ_CONNECT(QUARK_SE_IPM_INTERRUPT, QUARK_SE_IPM_INTERRUPT_PRI,
quark_se_ipm_isr, NULL, 0);
irq_enable(QUARK_SE_IPM_INTERRUPT);
return 0;
}
void main(void)
{
#ifdef CONFIG_OBJECTS_PRINTK
printk("Using printk\n");
#endif
#if CONFIG_STATIC_ISR
IRQ_CONNECT(IRQ_LINE, IRQ_PRIORITY, dummyIsr, NULL, 0);
#endif
#ifdef CONFIG_DYNAMIC_ISR
/* dynamically link in dummy ISR */
irq_connect_dynamic(IRQ_LINE, IRQ_PRIORITY, dummyIsr,
(void *) 0, 0);
#endif
#ifdef CONFIG_OBJECTS_FIBER
/* start a trivial fiber */
task_fiber_start(pStack, FIBER_STACK_SIZE, fiberEntry, (int) MESSAGE,
(int) func_array, 10, 0);
#endif
#ifdef CONFIG_OBJECTS_WHILELOOP
while (1) {
i++;
}
#endif
}
/**
*
* @brief Initialize and enable the system clock
*
* This routine is used to program the timer to deliver interrupts at the
* rate specified via the 'sys_clock_us_per_tick' global variable.
*
* @return 0
*/
int _sys_clock_driver_init(struct device *device)
{
ARG_UNUSED(device);
/* determine the timer counter value (in timer clock cycles/system tick)
*/
cycles_per_tick = sys_clock_hw_cycles_per_tick;
tickless_idle_init();
#ifndef CONFIG_MVIC
divide_configuration_register_set();
#endif
initial_count_register_set(cycles_per_tick - 1);
periodic_mode_set();
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
loapic_timer_device_power_state = DEVICE_PM_ACTIVE_STATE;
#endif
IRQ_CONNECT(TIMER_IRQ, TIMER_IRQ_PRIORITY, _timer_int_handler, 0, 0);
/* Everything has been configured. It is now safe to enable the
* interrupt
*/
irq_enable(TIMER_IRQ);
return 0;
}
static int imx_gpio_7_init(struct device *dev)
{
IRQ_CONNECT(DT_GPIO_IMX_PORT_7_IRQ_0,
DT_GPIO_IMX_PORT_7_IRQ_0_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_7), 0);
irq_enable(DT_GPIO_IMX_PORT_7_IRQ_0);
IRQ_CONNECT(DT_GPIO_IMX_PORT_7_IRQ_1,
DT_GPIO_IMX_PORT_7_IRQ_1_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_7), 0);
irq_enable(DT_GPIO_IMX_PORT_7_IRQ_1);
return 0;
}
static void mcux_wdog_config_func_0(struct device *dev)
{
IRQ_CONNECT(CONFIG_WDT_0_IRQ, CONFIG_WDT_0_IRQ_PRI,
mcux_wdog_isr, DEVICE_GET(mcux_wdog_0), 0);
irq_enable(CONFIG_WDT_0_IRQ);
}
/**
*
* @brief Initialize and enable the system clock
*
* This routine is used to program the ARCv2 timer to deliver interrupts at the
* rate specified via the 'sys_clock_us_per_tick' global variable.
*
* @return 0
*/
int _sys_clock_driver_init(struct device *device)
{
ARG_UNUSED(device);
/* ensure that the timer will not generate interrupts */
timer0_control_register_set(0);
timer0_count_register_set(0);
cycles_per_tick = sys_clock_hw_cycles_per_tick;
IRQ_CONNECT(IRQ_TIMER0, CONFIG_ARCV2_TIMER_IRQ_PRIORITY,
_timer_int_handler, NULL, 0);
/*
* Set the reload value to achieve the configured tick rate, enable the
* counter and interrupt generation.
*/
tickless_idle_init();
timer0_limit_register_set(cycles_per_tick - 1);
timer0_control_register_set(_ARC_V2_TMR_CTRL_NH | _ARC_V2_TMR_CTRL_IE);
/* everything has been configured: safe to enable the interrupt */
irq_enable(IRQ_TIMER0);
return 0;
}
static int qdec_nrfx_init(struct device *dev)
{
static const nrfx_qdec_config_t config = {
.reportper = NRF_QDEC_REPORTPER_40,
.sampleper = NRF_QDEC_SAMPLEPER_2048us,
.psela = DT_NORDIC_NRF_QDEC_QDEC_0_A_PIN,
.pselb = DT_NORDIC_NRF_QDEC_QDEC_0_B_PIN,
#if defined(DT_NORDIC_NRF_QDEC_QDEC_0_LED_PIN)
.pselled = DT_NORDIC_NRF_QDEC_QDEC_0_LED_PIN,
#else
.pselled = 0xFFFFFFFF, /* disabled */
#endif
.ledpre = DT_NORDIC_NRF_QDEC_QDEC_0_LED_PRE,
.ledpol = NRF_QDEC_LEPOL_ACTIVE_HIGH,
.interrupt_priority = NRFX_QDEC_CONFIG_IRQ_PRIORITY,
.dbfen = 0, /* disabled */
.sample_inten = 0, /* disabled */
};
nrfx_err_t nerr;
LOG_DBG("");
IRQ_CONNECT(DT_NORDIC_NRF_QDEC_QDEC_0_IRQ,
DT_NORDIC_NRF_QDEC_QDEC_0_IRQ_PRIORITY,
nrfx_isr, nrfx_qdec_irq_handler, 0);
nerr = nrfx_qdec_init(&config, qdec_nrfx_event_handler);
if (nerr == NRFX_ERROR_INVALID_STATE) {
LOG_ERR("qdec already in use");
return -EBUSY;
} else if (nerr != NRFX_SUCCESS) {
LOG_ERR("failed to initialize qdec");
return -EFAULT;
}
qdec_nrfx_gpio_ctrl(true);
nrfx_qdec_enable();
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
struct qdec_nrfx_data *data = &qdec_nrfx_data;
data->pm_state = DEVICE_PM_ACTIVE_STATE;
#endif
return 0;
}
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static int qdec_nrfx_pm_get_state(struct qdec_nrfx_data *data,
u32_t *state)
{
unsigned int key = irq_lock();
*state = data->pm_state;
irq_unlock(key);
return 0;
}
