/**
* @brief Set the software priority of the specified interrupt source.
* @param[in] IRQn: The interrupt source to access.
* @param[in] ITC_PriorityLevel : The software priority value to set.
* @retval ITC_PriorityLevel_TypeDef : The software priority of the interrupt source.
* @par Required preconditions:
* - The modification of the software priority is only possible when the interrupts are disabled.
* - The normal behavior is to disable the interrupts before calling this function, and re-enable it after.
* - The priority level 0 cannot be set (see product specification for more details).
*/
void ITC_SetSoftwarePriority(IRQn_TypeDef IRQn, ITC_PriorityLevel_TypeDef ITC_PriorityLevel)
{
uint8_t Mask;
uint8_t NewPriority;
/* Check function parameters */
assert_param(IS_ITC_IRQ((uint8_t)IRQn));
assert_param(IS_ITC_PRIORITY(ITC_PriorityLevel));
/* Check if interrupts are disabled */
assert_param(IS_ITC_INTERRUPTS_DISABLED);
/* Define the mask corresponding to the bits position in the SPR register */
/* The mask is reversed in order to clear the 2 bits after more easily */
Mask = (uint8_t)(~(uint8_t)(0x03U << (((uint8_t)IRQn % 4U) * 2U)));
/* Define the new priority to write */
NewPriority = (uint8_t)((uint8_t)(ITC_PriorityLevel) << (((uint8_t)IRQn % 4U) * 2U));
switch (IRQn)
{
case FLASH_IRQn:
ITC->ISPR1 &= Mask;
ITC->ISPR1 |= NewPriority;
break;
case AWU_IRQn:
case EXTIB_IRQn:
case EXTID_IRQn:
ITC->ISPR2 &= Mask;
ITC->ISPR2 |= NewPriority;
break;
case EXTI0_IRQn:
case EXTI1_IRQn:
case EXTI2_IRQn:
case EXTI3_IRQn:
ITC->ISPR3 &= Mask;
ITC->ISPR3 |= NewPriority;
break;
case EXTI4_IRQn:
case EXTI5_IRQn:
case EXTI6_IRQn:
case EXTI7_IRQn:
ITC->ISPR4 &= Mask;
ITC->ISPR4 |= NewPriority;
break;
case COMP_IRQn:
case TIM2_UPD_OVF_TRG_BRK_IRQn:
ITC->ISPR5 &= Mask;
ITC->ISPR5 |= NewPriority;
break;
case TIM2_CAP_IRQn:
case TIM3_UPD_OVF_TRG_BRK_IRQn:
case TIM3_CAP_IRQn:
ITC->ISPR6 &= Mask;
ITC->ISPR6 |= NewPriority;
break;
case TIM4_UPD_OVF_IRQn:
case SPI_IRQn:
case USART_TX_IRQn:
ITC->ISPR7 &= Mask;
ITC->ISPR7 |= NewPriority;
break;
case USART_RX_IRQn:
case I2C_IRQn:
ITC->ISPR8 &= Mask;
ITC->ISPR8 |= NewPriority;
break;
default:
break;
}
}
/**
* @brief Sets the software priority of the specified interrupt source.
* @note The modification of the software priority is only possible when
* the interrupts are disabled.
* @note The normal behavior is to disable the interrupt before calling
* this function, and re-enable it after.
* @note The priority level 0 cannot be set (see product specification
* for more details).
* @param IRQn : Specifies the peripheral interrupt source.
* @param ITC_PriorityLevel : Specifies the software priority value to set
* This parameter can be one of the following values:
* @arg ITC_PriorityLevel_0: Software priority level 0 (cannot be written)
* @arg ITC_PriorityLevel_1: Software priority level 1
* @arg ITC_PriorityLevel_2: Software priority level 2
* @arg ITC_PriorityLevel_3: Software priority level 3
* @retval None
*/
void ITC_SetSoftwarePriority(IRQn_TypeDef IRQn, ITC_PriorityLevel_TypeDef ITC_PriorityLevel)
{
uint8_t Mask = 0;
uint8_t NewPriority = 0;
/* Check function parameters */
assert_param(IS_ITC_IRQ(IRQn));
assert_param(IS_ITC_PRIORITY(ITC_PriorityLevel));
/* Check if interrupts are disabled */
assert_param(IS_ITC_INTERRUPTS_DISABLED);
/* Define the mask corresponding to the bits position in the SPR register */
/* The mask is reversed in order to clear the 2 bits after more easily */
Mask = (uint8_t)(~(uint8_t)(0x03U << ((IRQn % 4U) * 2U)));
/* Define the new priority to write */
NewPriority = (uint8_t)((uint8_t)(ITC_PriorityLevel) << ((IRQn % 4U) * 2U));
switch (IRQn)
{
case FLASH_IRQn:
case DMA1_CHANNEL0_1_IRQn:
case DMA1_CHANNEL2_3_IRQn:
ITC->ISPR1 &= Mask;
ITC->ISPR1 |= NewPriority;
break;
case EXTIE_F_PVD_IRQn:
#ifdef STM8L15X_MD
case RTC_IRQn:
case EXTIB_IRQn:
case EXTID_IRQn:
#elif defined (STM8L15X_LD)
case RTC_CSSLSE_IRQn:
case EXTIB_IRQn:
case EXTID_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
case RTC_CSSLSE_IRQn:
case EXTIB_G_IRQn:
case EXTID_H_IRQn:
#endif /* STM8L15X_MD */
ITC->ISPR2 &= Mask;
ITC->ISPR2 |= NewPriority;
break;
case EXTI0_IRQn:
case EXTI1_IRQn:
case EXTI2_IRQn:
case EXTI3_IRQn:
ITC->ISPR3 &= Mask;
ITC->ISPR3 |= NewPriority;
break;
case EXTI4_IRQn:
case EXTI5_IRQn:
case EXTI6_IRQn:
case EXTI7_IRQn:
ITC->ISPR4 &= Mask;
ITC->ISPR4 |= NewPriority;
break;
#ifndef STM8L15X_LD
case SWITCH_CSS_BREAK_DAC_IRQn:
#else
case SWITCH_CSS_IRQn:
#endif /* STM8L15X_LD */
case ADC1_COMP_IRQn:
#ifdef STM8L15X_MD
case LCD_IRQn:
case TIM2_UPD_OVF_TRG_BRK_IRQn:
#elif defined (STM8L15X_LD)
case TIM2_UPD_OVF_TRG_BRK_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
case LCD_AES_IRQn:
case TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn:
#endif /* STM8L15X_MD */
ITC->ISPR5 &= Mask;
ITC->ISPR5 |= NewPriority;
break;
#ifndef STM8L15X_LD
case TIM1_UPD_OVF_TRG_IRQn:
#endif /* STM8L15X_LD */
#if defined (STM8L15X_MD) || defined (STM8L15X_LD)
case TIM2_CC_IRQn:
case TIM3_UPD_OVF_TRG_BRK_IRQn :
case TIM3_CC_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
case TIM2_CC_USART2_RX_IRQn:
case TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn :
case TIM3_CC_USART3_RX_IRQn:
#endif /* STM8L15X_MD */
ITC->ISPR6 &= Mask;
ITC->ISPR6 |= NewPriority;
break;
#ifndef STM8L15X_LD
case TIM1_CC_IRQn:
#endif /* STM8L15X_LD */
case TIM4_UPD_OVF_TRG_IRQn:
case SPI1_IRQn:
#if defined (STM8L15X_MD) || defined (STM8L15X_LD)
case USART1_TX_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
case USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn:
#endif /* STM8L15X_MD */
ITC->ISPR7 &= Mask;
ITC->ISPR7 |= NewPriority;
break;
#if defined (STM8L15X_MD) || defined (STM8L15X_LD)
case USART1_RX_IRQn:
case I2C1_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP)
case USART1_RX_TIM5_CC_IRQn:
case I2C1_SPI2_IRQn:
#endif /* STM8L15X_MD */
ITC->ISPR8 &= Mask;
ITC->ISPR8 |= NewPriority;
break;
default:
break;
}
}
