VOID RT30xxHaltAction(
IN PRTMP_ADAPTER pAd)
{
UINT32 TxPinCfg = 0x00050F0F;
/* Turn off LNA_PE or TRSW_POL*/
if ((IS_RT3071(pAd) || IS_RT3572(pAd))
#ifdef RTMP_EFUSE_SUPPORT
&& (pAd->bUseEfuse)
#endif /* RTMP_EFUSE_SUPPORT */
)
{
TxPinCfg &= 0xFFFBF0F0; /* bit18 off */
}
else
{
TxPinCfg &= 0xFFFFF0F0;
}
#ifdef RT35xx
if (IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x00);
#endif /* RT35xx */
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
VOID RT30xxHaltAction(
IN PRTMP_ADAPTER pAd)
{
UINT32 TxPinCfg = 0x00050F0F;
//
// Turn off LNA_PE or TRSW_POL
//
if (IS_RT3070(pAd) || IS_RT3071(pAd) || IS_RT3572(pAd) || IS_RT5390(pAd))
{
if ((IS_RT3071(pAd) || IS_RT3572(pAd) || IS_RT5390(pAd))
#ifdef RTMP_EFUSE_SUPPORT
&& (pAd->bUseEfuse)
#endif // RTMP_EFUSE_SUPPORT //
)
{
TxPinCfg &= 0xFFFBF0F0; // bit18 off
}
else
{
TxPinCfg &= 0xFFFFF0F0;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
}
VOID RT35xxLoadRFSleepModeSetup(
IN PRTMP_ADAPTER pAd)
{
UCHAR RFValue;
#ifdef RT35xx
if(IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, 0x00);
#endif /* RT35xx */
if(!IS_RT3572(pAd))
{
/* RF_BLOCK_en. RF R1 register Bit 0 to 0*/
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue &= (~0x01);
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
/* VCO_IC, RF R7 register Bit 4 & Bit 5 to 0*/
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue &= (~0x30);
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
/* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0*/
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue &= (~0x0E);
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
/* RX_CTB_en, RF R21 register Bit 7 to 0*/
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue &= (~0x80);
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
}
VOID RT35xxLoadRFSleepModeSetup(
IN PRTMP_ADAPTER pAd)
{
UCHAR RFValue;
UINT32 MACValue;
#ifdef RT35xx
if(IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, 0x00);
#endif /* RT35xx */
if(!IS_RT3572(pAd))
{
/* RF_BLOCK_en. RF R1 register Bit 0 to 0*/
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue &= (~0x01);
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
/* VCO_IC, RF R7 register Bit 4 & Bit 5 to 0*/
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue &= (~0x30);
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
/* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0*/
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue &= (~0x0E);
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
/* RX_CTB_en, RF R21 register Bit 7 to 0*/
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue &= (~0x80);
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
/* Don't touch LDO_CFG0 for 3090F & 3593, possibly the board is single power scheme*/
if (IS_RT3090(pAd) || /*IS_RT3090 including RT309x and RT3071/72*/
IS_RT3572(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
{
if (!IS_RT3572(pAd))
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
RFValue |= 0x77;
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
}
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue |= 0x1D000000;
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
static INT rtmp_bbp_init(RTMP_ADAPTER *pAd)
{
INT Index = 0;
/* Read BBP register, make sure BBP is up and running before write new data*/
if (rtmp_bbp_is_ready(pAd)== FALSE)
return FALSE;
Index = 0;
/* Initialize BBP register to default value*/
for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++)
{
#ifdef MICROWAVE_OVEN_SUPPORT
#endif /* MICROWAVE_OVEN_SUPPORT */
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd,
BBPRegTable[Index].Register,
BBPRegTable[Index].Value);
}
/* re-config specific BBP registers for individual chip */
if (pAd->chipCap.pBBPRegTable)
{
REG_PAIR *reg_list = pAd->chipCap.pBBPRegTable;
for (Index = 0; Index < pAd->chipCap.bbpRegTbSize; Index++)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd,
reg_list[Index].Register,
reg_list[Index].Value);
DBGPRINT(RT_DEBUG_TRACE, ("BBP_R%d=0x%x\n",
reg_list[Index].Register,
reg_list[Index].Value));
}
}
if (pAd->chipOps.AsicBbpInit != NULL)
pAd->chipOps.AsicBbpInit(pAd);
/*
For rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT.
RT3090 should not program BBP R84 to 0x19, otherwise TX will block.
3070/71/72,3090,3090A( are included in RT30xx),3572,3390
*/
if (((pAd->MACVersion & 0xffff) != 0x0101) &&
!(IS_RT30xx(pAd)|| IS_RT3572(pAd) || IS_RT5390(pAd) || IS_RT5392(pAd) || IS_RT3290(pAd) || IS_MT7601(pAd) || IS_RT6352(pAd) || IS_MT76x2(pAd)))
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19);
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x12);
}
return TRUE;
}
/*
==========================================================================
Description:
Load RF sleep-mode setup
==========================================================================
*/
void RT30xxLoadRFSleepModeSetup(struct rt_rtmp_adapter *pAd)
{
u8 RFValue;
u32 MACValue;
#ifdef RTMP_MAC_USB
if (!IS_RT3572(pAd))
#endif /* RTMP_MAC_USB // */
{
/* RF_BLOCK_en. RF R1 register Bit 0 to 0 */
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue &= (~0x01);
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
/* VCO_IC, RF R7 register Bit 4 & Bit 5 to 0 */
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue &= (~0x30);
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
/* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0 */
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue &= (~0x0E);
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
/* RX_CTB_en, RF R21 register Bit 7 to 0 */
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue &= (~0x80);
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72 */
IS_RT3572(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) {
#ifdef RTMP_MAC_USB
if (!IS_RT3572(pAd))
#endif /* RTMP_MAC_USB // */
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
RFValue |= 0x77;
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
}
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue |= 0x1D000000;
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
// IRQL = PASSIVE_LEVEL
int rtmp_ee_prom_read16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
OUT USHORT *pValue)
{
UINT32 x;
USHORT data;
#ifdef RT30xx
#ifdef ANT_DIVERSITY_SUPPORT
if (pAd->NicConfig2.field.AntDiversity)
{
pAd->EepromAccess = TRUE;
}
#endif // ANT_DIVERSITY_SUPPORT //
#endif // RT30xx //
Offset /= 2;
// reset bits and set EECS
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
// patch can not access e-Fuse issue
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)))
{
// kick a pulse
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
// output the read_opcode and register number in that order
ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
// Now read the data (16 bits) in from the selected EEPROM word
data = ShiftInBits(pAd);
EEpromCleanup(pAd);
#ifdef RT30xx
#ifdef ANT_DIVERSITY_SUPPORT
// Antenna and EEPROM access are both using EESK pin,
// Therefor we should avoid accessing EESK at the same time
// Then restore antenna after EEPROM access
if ((pAd->NicConfig2.field.AntDiversity)/* || (pAd->RfIcType == RFIC_3020)*/)
{
pAd->EepromAccess = FALSE;
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
}
#endif // ANT_DIVERSITY_SUPPORT //
#endif // RT30xx //
*pValue = data;
return NDIS_STATUS_SUCCESS;
}
int rtmp_ee_prom_read16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
OUT USHORT *pValue)
{
UINT32 x;
USHORT data;
#ifdef RT30xx
#ifdef ANT_DIVERSITY_SUPPORT
if (pAd->NicConfig2.field.AntDiversity)
{
pAd->EepromAccess = TRUE;
}
#endif
#endif
Offset /= 2;
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)))
{
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
data = ShiftInBits(pAd);
EEpromCleanup(pAd);
#ifdef RT30xx
#ifdef ANT_DIVERSITY_SUPPORT
if ((pAd->NicConfig2.field.AntDiversity))
{
pAd->EepromAccess = FALSE;
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
}
#endif
#endif
*pValue = data;
return NDIS_STATUS_SUCCESS;
}
void RT30xxHaltAction(struct rt_rtmp_adapter *pAd)
{
u32 TxPinCfg = 0x00050F0F;
/* */
/* Turn off LNA_PE or TRSW_POL */
/* */
if (IS_RT3070(pAd) || IS_RT3071(pAd) || IS_RT3572(pAd)) {
if ((IS_RT3071(pAd) || IS_RT3572(pAd))
#ifdef RTMP_EFUSE_SUPPORT
&& (pAd->bUseEfuse)
#endif /* RTMP_EFUSE_SUPPORT // */
) {
TxPinCfg &= 0xFFFBF0F0; /* bit18 off */
} else {
TxPinCfg &= 0xFFFFF0F0;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
}
/*
==========================================================================
Description:
dynamic tune BBP R66 to find a balance between sensibility and
noise isolation
IRQL = DISPATCH_LEVEL
==========================================================================
*/
UCHAR RT35xx_ChipAGCAdjust(
IN RTMP_ADAPTER *pAd,
IN CHAR Rssi,
IN UCHAR OrigR66Value)
{
UCHAR R66 = OrigR66Value;
CHAR lanGain = GET_LNA_GAIN(pAd);
if (!(IS_RT3572(pAd) || IS_RT3593(pAd)))
{
DBGPRINT(RT_DEBUG_ERROR, ("RT35xx_ChipAGCAdjust - Mismatch MACVersion = 0x%x \n", pAd->MACVersion));
return R66;
}
if (pAd->LatchRfRegs.Channel <= 14)
{ /*BG band*/
R66 = 0x1C + 2 * lanGain;
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
R66 += 0x20;
}
else
{ /*A band*/
if (pAd->CommonCfg.BBPCurrentBW == BW_20)
{
R66 = 0x32 + (lanGain*5) / 3;
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
R66 += 0x10;
}
else
{
R66 = 0x3A + (lanGain*5)/3;
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
R66 += 0x10;
}
#ifdef RT3593
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) {
RT3593_R66_MID_LOW_SENS_GET(pAd, R66);
} else {
RT3593_R66_NON_MID_LOW_SEMS_GET(pAd, R66);
}
#endif /* RT3593 */
}
if (OrigR66Value != R66)
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
return R66;
}
VOID RT35xx_RxSensitivityTuning(
IN PRTMP_ADAPTER pAd)
{
UCHAR R66;
R66 = 0x26 + GET_LNA_GAIN(pAd);
#ifdef RT35xx
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
#endif /* RT35xx */
DBGPRINT(RT_DEBUG_TRACE,("turn off R17 tuning, restore to 0x%02x\n", R66));
}
int rtmp_ee_prom_write16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
IN USHORT Data)
{
UINT32 x;
#ifdef RT30xx
#endif // RT30xx //
Offset /= 2;
EWEN(pAd);
// reset bits and set EECS
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
// patch can not access e-Fuse issue
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)))
{
// kick a pulse
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
// output the read_opcode ,register number and data in that order
ShiftOutBits(pAd, EEPROM_WRITE_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
ShiftOutBits(pAd, Data, 16); // 16-bit access
// read DO status
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
EEpromCleanup(pAd);
RTMPusecDelay(10000); //delay for twp(MAX)=10ms
EWDS(pAd);
EEpromCleanup(pAd);
#ifdef RT30xx
#endif // RT30xx //
return NDIS_STATUS_SUCCESS;
}
VOID RT35xx_NICInitAsicFromEEPROM(
IN PRTMP_ADAPTER pAd)
{
UCHAR bbpreg = 0;
UCHAR RFValue = 0;
if (IS_RT3572(pAd))
{
/* enable DC filter*/
if ((pAd->MACVersion & 0xffff) >= 0x0201)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R103, 0xc0);
}
/* improve power consumption */
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R138, &bbpreg);
if (pAd->Antenna.field.TxPath == 1)
{
/* turn off tx DAC_1 */
bbpreg = (bbpreg | 0x20);
}
if (pAd->Antenna.field.RxPath == 1)
{
/* turn off tx ADC_1*/
bbpreg &= (~0x2);
}
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R138, bbpreg);
if ((pAd->MACVersion & 0xffff) >= 0x0211)
{
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R31, &bbpreg);
bbpreg &= (~0x3);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R31, bbpreg);
}
/* TX_LO1_en*/
RT30xxReadRFRegister(pAd, RF_R16, &RFValue);
/* set RF_R16_bit[2:0] equal to EEPROM setting at 0x48h and the value should start from 2.*/
/*if (pAd->TxMixerGain24G >= 2)*/
{
RFValue &= (~0x7); /* clean bit [2:0]*/
RFValue |= pAd->TxMixerGain24G;
}
RT30xxWriteRFRegister(pAd, RF_R16, RFValue);
}
}
VOID RtmpChipOpsRFHook(
IN RTMP_ADAPTER *pAd)
{
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
pChipOps->pRFRegTable = NULL;
pChipOps->pBBPRegTable = NULL;
pChipOps->bbpRegTbSize = 0;
pChipOps->AsicRfInit = NULL;
pChipOps->AsicRfTurnOn = NULL;
pChipOps->AsicRfTurnOff = NULL;
pChipOps->AsicReverseRfFromSleepMode = NULL;
pChipOps->AsicHaltAction = NULL;
/* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */
#ifdef RT30xx
#ifdef RT35xx
if (IS_RT3572(pAd))
{
pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
pChipOps->pRFRegTable = RF3572_RFRegTable;
pChipOps->AsicRfInit = NICInitRT3572RFRegisters;
pChipOps->AsicReverseRfFromSleepMode = RT3572ReverseRFSleepModeSetup;
pChipOps->AsicHaltAction = RT30xxHaltAction;
}
#endif // RT35xx //
if (IS_RT30xx(pAd))
{
/*
WARNING:
Currently following table are shared by all RT30xx based IC, change it carefully when you add a new IC here.
*/
pChipOps->pRFRegTable = RT3020_RFRegTable;
pChipOps->AsicHaltAction = RT30xxHaltAction;
pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup;
}
#endif // RT30xx //
DBGPRINT(RT_DEBUG_TRACE, ("Chip specific bbpRegTbSize=%d!\n", pChipOps->bbpRegTbSize));
}
/*
==========================================================================
Description:
Reverse RF sleep-mode setup
==========================================================================
*/
VOID RT30xxReverseRFSleepModeSetup(
IN PRTMP_ADAPTER pAd,
IN BOOLEAN FlgIsInitState)
{
UCHAR RFValue;
UINT32 MACValue;
if(!IS_RT3572(pAd))
{
/* RF_BLOCK_en, RF R1 register Bit 0 to 1*/
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue |= 0x01;
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
/* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1*/
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue |= 0x20;
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
/* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1*/
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue |= 0x0E;
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
/* RX_CTB_en, RF R21 register Bit 7 to 1*/
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72*/
IS_RT3390(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
{
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
if ((pAd->MACVersion & 0xffff) < 0x0211)
RFValue = (RFValue & (~0x77)) | 0x3;
else
RFValue = (RFValue & (~0x77));
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
}
/* RT3071 version E has fixed this issue*/
}
}
/*
==========================================================================
Description:
Load RF sleep-mode setup
==========================================================================
*/
VOID RT33xxLoadRFSleepModeSetup(
IN PRTMP_ADAPTER pAd)
{
UCHAR RFValue;
UINT32 MACValue;
{
// RF_BLOCK_en. RF R1 register Bit 0 to 0
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue &= (~0x01);
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
// VCO_IC, RF R7 register Bit 4 & Bit 5 to 0
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue &= (~0x30);
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue &= (~0x0E);
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
// RX_CTB_en, RF R21 register Bit 7 to 0
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue &= (~0x80);
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72
IS_RT3572(pAd) ||
IS_RT3390(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
{
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
RFValue |= 0x77;
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
}
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue |= 0x1D000000;
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
// IRQL = PASSIVE_LEVEL
int rtmp_ee_prom_read16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
OUT USHORT *pValue)
{
UINT32 x;
USHORT data;
#ifdef RT30xx
#endif // RT30xx //
Offset /= 2;
// reset bits and set EECS
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
// patch can not access e-Fuse issue
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)))
{
// kick a pulse
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
// output the read_opcode and register number in that order
ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
// Now read the data (16 bits) in from the selected EEPROM word
data = ShiftInBits(pAd);
EEpromCleanup(pAd);
#ifdef RT30xx
#endif // RT30xx //
*pValue = data;
return NDIS_STATUS_SUCCESS;
}
VOID RT35xx_RxSensitivityTuning(
IN PRTMP_ADAPTER pAd)
{
UCHAR R66;
R66 = 0x26 + GET_LNA_GAIN(pAd);
#ifdef RALINK_ATE
if (ATE_ON(pAd))
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x26 + GET_LNA_GAIN(pAd)));
}
else
#endif /* RALINK_ATE */
#ifdef RT35xx
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
#endif /* RT35xx */
DBGPRINT(RT_DEBUG_TRACE,("turn off R17 tuning, restore to 0x%02x\n", R66));
}
/*
========================================================================
Routine Description: 3572/3592 R66 writing must select BBP_R27
Arguments:
Return Value:
IRQL =
Note:
========================================================================
*/
NTSTATUS RT3572WriteBBPR66(
IN PRTMP_ADAPTER pAd,
IN UCHAR Value)
{
NTSTATUS NStatus = STATUS_UNSUCCESSFUL;
UCHAR bbpData = 0;
if (!IS_RT3572(pAd) && !IS_RT3593(pAd))
{
DBGPRINT(RT_DEBUG_ERROR, ("%s: Incorrect MAC version, pAd->MACVersion = 0x%X\n",
__FUNCTION__,
pAd->MACVersion));
return NStatus;
}
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R27, &bbpData);
/* R66 controls the gain of Rx0*/
bbpData &= ~(0x60); /*clear bit 5,6*/
#ifdef RTMP_MAC_USB
if (RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R27, bbpData) == STATUS_SUCCESS)
#endif /* RTMP_MAC_USB */
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, Value);
}
/* R66 controls the gain of Rx1*/
bbpData |= 0x20; /* set bit 5*/
#ifdef RTMP_MAC_USB
if (RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R27, bbpData) == STATUS_SUCCESS)
#endif /* RTMP_MAC_USB */
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, Value);
NStatus = STATUS_SUCCESS;
}
return NStatus;
}
VOID RT35xx_ChipBBPAdjust(
IN RTMP_ADAPTER *pAd)
{
UINT32 Value;
UCHAR byteValue = 0;
#ifdef DOT11_N_SUPPORT
if ((pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth == BW_40) &&
(pAd->CommonCfg.RegTransmitSetting.field.EXTCHA == EXTCHA_ABOVE))
{
pAd->CommonCfg.BBPCurrentBW = BW_40;
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel + 2;
/* TX : control channel at lower */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x1);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* RX : control channel at lower */
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &byteValue);
byteValue &= (~0x20);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, byteValue);
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue);
byteValue &= (~0x18);
byteValue |= 0x10;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue);
if (pAd->CommonCfg.Channel > 14)
{ /* request by Gary 20070208 for middle and long range A Band*/
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, 0x48);
}
else
{ /* request by Gary 20070208 for middle and long range G Band*/
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, 0x38);
}
/* */
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10);
}
DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : ExtAbove, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n",
pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth,
pAd->CommonCfg.Channel,
pAd->CommonCfg.RegTransmitSetting.field.EXTCHA,
pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset));
}
else if ((pAd->CommonCfg.Channel > 2) &&
(pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth == BW_40) &&
(pAd->CommonCfg.RegTransmitSetting.field.EXTCHA == EXTCHA_BELOW))
{
pAd->CommonCfg.BBPCurrentBW = BW_40;
if (pAd->CommonCfg.Channel == 14)
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel - 1;
else
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel - 2;
/* TX : control channel at upper */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value |= (0x1);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* RX : control channel at upper */
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &byteValue);
byteValue |= (0x20);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, byteValue);
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue);
byteValue &= (~0x18);
byteValue |= 0x10;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue);
if (pAd->CommonCfg.Channel > 14)
{ /* request by Gary 20070208 for middle and long range A Band*/
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, 0x48);
}
else
{ /* request by Gary 20070208 for middle and long range G band*/
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, 0x38);
}
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10);
}
DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : ExtBlow, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n",
pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth,
pAd->CommonCfg.Channel,
pAd->CommonCfg.RegTransmitSetting.field.EXTCHA,
pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset));
}
else
#endif /* DOT11_N_SUPPORT */
{
pAd->CommonCfg.BBPCurrentBW = BW_20;
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel;
/* TX : control channel at lower */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x1);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue);
byteValue &= (~0x18);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue);
/* 20 MHz bandwidth*/
if (pAd->CommonCfg.Channel > 14)
{ /* request by Gary 20070208*/
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, 0x40);
}
else
{ /* request by Gary 20070208*/
/*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, 0x30);*/
/* request by Brian 20070306*/
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, 0x38);
}
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x08);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x11);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0a);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10);
}
#ifdef DOT11_N_SUPPORT
DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : 20MHz, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n",
pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth,
pAd->CommonCfg.Channel,
pAd->CommonCfg.RegTransmitSetting.field.EXTCHA,
pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset));
#endif /* DOT11_N_SUPPORT */
}
if (pAd->CommonCfg.Channel > 14)
{ /* request by Gary 20070208 for middle and long range A Band*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x1D);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x1D);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x1D);
/*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x1D);*/
}
else
{ /* request by Gary 20070208 for middle and long range G band*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x2D);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x2D);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x2D);
/*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x2D);*/
}
}
/*
==========================================================================
Description:
dynamic tune BBP R66 to find a balance between sensibility and
noise isolation
IRQL = DISPATCH_LEVEL
==========================================================================
*/
UCHAR RT35xx_ChipStaBBPAdjust(
IN RTMP_ADAPTER *pAd,
IN CHAR Rssi,
IN UCHAR R66)
{
UCHAR OrigR66Value = 0;/*, R66UpperBound = 0x30, R66LowerBound = 0x30;*/
if (pAd->LatchRfRegs.Channel <= 14)
{ /*BG band*/
if (IS_RT3572(pAd)|| IS_RT3593(pAd))
{
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
{
R66 = 0x1C + 2*GET_LNA_GAIN(pAd) + 0x20;
if (OrigR66Value != R66)
{
RT3572WriteBBPR66(pAd, R66);
}
}
else
{
R66 = 0x1C + 2*GET_LNA_GAIN(pAd);
if (OrigR66Value != R66)
{
RT3572WriteBBPR66(pAd, R66);
}
}
}
else
DBGPRINT(RT_DEBUG_ERROR, ("RT35xx_ChipStaBBPAdjust - Mismatch MACVersion = 0x%x \n", pAd->MACVersion));
}
else
{ /*A band*/
if (pAd->CommonCfg.BBPCurrentBW == BW_20)
{
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
{
R66 = 0x32 + (GET_LNA_GAIN(pAd)*5)/3 + 0x10;
if (OrigR66Value != R66)
{
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, R66);
}
}
else
{
R66 = 0x32 + (GET_LNA_GAIN(pAd)*5)/3;
if (OrigR66Value != R66)
{
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, R66);
}
}
}
else
{
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
{
R66 = 0x3A + (GET_LNA_GAIN(pAd)*5)/3 + 0x10;
if (OrigR66Value != R66)
{
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, R66);
}
}
else
{
R66 = 0x3A + (GET_LNA_GAIN(pAd)*5)/3;
if (OrigR66Value != R66)
{
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, R66);
}
}
}
}
return 0;
}
VOID RT35xx_ChipSwitchChannel(
IN PRTMP_ADAPTER pAd,
IN UCHAR Channel,
IN BOOLEAN bScan)
{
CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/
UCHAR index;
UINT32 Value = 0; /*BbpReg, Value;*/
UCHAR RFValue;
UINT32 i = 0;
i = i; /* avoid compile warning */
RFValue = 0;
/* Search Tx power value*/
/*
We can't use ChannelList to search channel, since some central channl's txpowr doesn't list
in ChannelList, so use TxPower array instead.
*/
for (index = 0; index < MAX_NUM_OF_CHANNELS; index++)
{
if (Channel == pAd->TxPower[index].Channel)
{
TxPwer = pAd->TxPower[index].Power;
TxPwer2 = pAd->TxPower[index].Power2;
break;
}
}
if (index == MAX_NUM_OF_CHANNELS)
{
DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel));
}
#ifdef RT35xx
/* 3562:RFIC_3052/ 3062:RFIC_3022 */
if (IS_RT3572(pAd) /*&& (pAd->RfIcType == RFIC_3052)*/)
{
for (index = 0; index < NUM_OF_3572_CHNL; index++)
{
if (Channel == FreqItems3572[index].Channel)
{
/* for 2.4G, restore BBP25, BBP26*/
if (Channel <= 14)
{
BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, pAd->Bbp25);
BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R26, pAd->Bbp26);
}
/* hard code for 5GGhz, Gary 2008-12-10*/
else
{
/* Enable IQ Phase Correction*/
BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x09);
/* IQ Phase correction value*/
BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R26, 0xFF);
}
/* Programming channel parameters*/
RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3572[index].N);
RT30xxWriteRFRegister(pAd, RF_R03, FreqItems3572[index].K);
RT30xxReadRFRegister(pAd, RF_R06, &RFValue);
if (Channel <= 14)
RFValue = (RFValue & 0xF0) | FreqItems3572[index].R | 0x8;
else
RFValue = (RFValue & 0xF0) | FreqItems3572[index].R | 0x4;
RT30xxWriteRFRegister(pAd, RF_R06, RFValue);
/* Pll mode for 2.4G or 5G*/
RT30xxReadRFRegister(pAd, RF_R05, &RFValue);
if (Channel <= 14)
RFValue = (RFValue & 0xF3) | 0x4;
else
RFValue = (RFValue & 0xF3) | 0x8;
RT30xxWriteRFRegister(pAd, RF_R05, RFValue);
/* Set Tx0 Power*/
RT30xxReadRFRegister(pAd, RF_R12, (PUCHAR)&RFValue);
if (Channel <= 14)
RFValue = 0x60 | TxPwer;
else
RFValue = 0xE0 | (TxPwer & 0x3) | ((TxPwer & 0xC) << 1);
RT30xxWriteRFRegister(pAd, RF_R12, RFValue);
/* Set Tx1 Power*/
RT30xxReadRFRegister(pAd, RF_R13, (PUCHAR)&RFValue);
if (Channel <= 14)
RFValue = 0x60 | TxPwer2;
else
RFValue = 0xE0 | (TxPwer2 & 0x3) | ((TxPwer2 & 0xC) << 1);
RT30xxWriteRFRegister(pAd, RF_R13, RFValue);
/* Tx/Rx Stream setting*/
RT30xxReadRFRegister(pAd, RF_R01, (PUCHAR)&RFValue);
RFValue &= 0x03; /*clear bit[7~2]*/
if (pAd->Antenna.field.TxPath == 1)
RFValue |= 0xA0;
else if (pAd->Antenna.field.TxPath == 2)
RFValue |= 0x80;
if (pAd->Antenna.field.RxPath == 1)
RFValue |= 0x50;
else if (pAd->Antenna.field.RxPath == 2)
RFValue |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R01, (UCHAR)RFValue);
/* Set RF offset*/
RT30xxReadRFRegister(pAd, RF_R23, (PUCHAR)&RFValue);
RFValue = (RFValue & 0x80) | pAd->RfFreqOffset;
RT30xxWriteRFRegister(pAd, RF_R23, (UCHAR)RFValue);
/* Set BW*/
if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
{
RFValue = pAd->Mlme.CaliBW40RfR24;
/*DISABLE_11N_CHECK(pAd);*/
}
else
{
RFValue = pAd->Mlme.CaliBW20RfR24;
}
/* R24, R31, one is for tx, the other is for rx*/
RT30xxWriteRFRegister(pAd, RF_R24, (UCHAR)RFValue);
RT30xxWriteRFRegister(pAd, RF_R31, (UCHAR)RFValue);
/* Enable RF tuning*/
RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)&RFValue);
if (Channel <= 14)
/*RFValue = (RFValue & 0x37) | 0xCC;*/
RFValue = 0xd8; /*?? to check 3572?? hardcode*/
else
RFValue = (RFValue & 0x37) | 0x14;
RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue);
/* TSSI_BS*/
RT30xxReadRFRegister(pAd, RF_R09, (PUCHAR)&RFValue);
if (Channel <= 14)
RFValue = 0xC3; /*RFValue = (RFValue & 0xBF) | 0x40;*/
else
RFValue = 0xC0; /*RFValue = (RFValue & 0xBF) | 0x40;*/
RT30xxWriteRFRegister(pAd, RF_R09, (UCHAR)RFValue);
/* Loop filter 1*/
RT30xxWriteRFRegister(pAd, RF_R10, (UCHAR)0xF1);
/* Loop filter 2*/
if (Channel <= 14)
RT30xxWriteRFRegister(pAd, RF_R11, (UCHAR)0xB9);
else
RT30xxWriteRFRegister(pAd, RF_R11, (UCHAR)0x00);
/* tx_mx2_ic*/
if (Channel <= 14)
RT30xxWriteRFRegister(pAd, RF_R15, (UCHAR)0x53);
else
RT30xxWriteRFRegister(pAd, RF_R15, (UCHAR)0x43);
/* tx_mx1_ic*/
/*RT30xxReadRFRegister(pAd, RF_R16, (PUCHAR)&RFValue);*/
if (Channel <= 14)
{
RFValue = 0x4c;
RFValue &= (~0x7); /* clean bit [2:0]*/
RFValue |= pAd->TxMixerGain24G;
}
else
{
RFValue = 0x7a;
RFValue &= (~0x7); /* clean bit [2:0]*/
RFValue |= pAd->TxMixerGain5G;
}
RT30xxWriteRFRegister(pAd, RF_R16, (UCHAR)RFValue);
/* tx_lo1*/
RT30xxWriteRFRegister(pAd, RF_R17, (UCHAR)0x23);
/* tx_lo2*/
RFValue = ((Channel <= 14) ? (0x93) : ((Channel <= 64) ? (0xb7) : ((Channel <= 128) ? (0x74) : (0x72))));
RT30xxWriteRFRegister(pAd, RF_R19, (UCHAR)RFValue);
/* rx_l01*/
RFValue = ((Channel <= 14) ? (0xB3) : ((Channel <= 64) ? (0xF6) : ((Channel <= 128) ? (0xF4) : (0xF3))));
RT30xxWriteRFRegister(pAd, RF_R20, (UCHAR)RFValue);
/* pfd_delay*/
RFValue = ((Channel <= 14) ? (0x15) : ((Channel <= 64) ? (0x3d) : ((Channel <= 128) ? (0x01) : (0x01))));
RT30xxWriteRFRegister(pAd, RF_R25, (UCHAR)RFValue);
/* rx_lo2*/
if (Channel <= 14)
RT30xxWriteRFRegister(pAd, RF_R26, (UCHAR)0x85);
else
RT30xxWriteRFRegister(pAd, RF_R26, (UCHAR)0x87);
/* ldo_rf_vc*/
if (Channel <= 14)
RT30xxWriteRFRegister(pAd, RF_R27, (UCHAR)0x00);
else
RT30xxWriteRFRegister(pAd, RF_R27, (UCHAR)0x01);
/* drv_cc*/
if (Channel <= 14)
RT30xxWriteRFRegister(pAd, RF_R29, (UCHAR)0x9B);
else
RT30xxWriteRFRegister(pAd, RF_R29, (UCHAR)0x9F);
RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
if (Channel <= 14)
Value = ((Value & 0xFFFF7FFF) | 0x00000080);
else
Value = (Value & 0xFFFF7F7F);
RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
/* Enable RF tuning, this must be in the last*/
RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)&RFValue);
RFValue = RFValue | 0x1;
RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue);
RTMPusecDelay(2000);
/* latch channel for future usage.*/
pAd->LatchRfRegs.Channel = Channel;
DBGPRINT(RT_DEBUG_TRACE, ("RT35xx: SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
Channel,
pAd->RfIcType,
TxPwer,
TxPwer2,
pAd->Antenna.field.TxPath,
FreqItems3572[index].N,
FreqItems3572[index].K,
FreqItems3572[index].R));
break;
}
}
}
else
#endif /* RT35xx */
{
switch (pAd->RfIcType)
{
default:
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d : unknown RFIC=%d\n",
Channel, pAd->RfIcType));
break;
}
}
/* Change BBP setting during siwtch from a->g, g->a*/
if (Channel <= 14)
{
ULONG TxPinCfg = 0x00050F0A;/*Gary 2007/08/09 0x050A0A*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
/* Rx High power VGA offset for LNA select*/
{
if (pAd->NicConfig2.field.ExternalLNAForG)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x04);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
#ifdef RT35xx
if (IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x00);
#endif /* RT35xx */
{
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
#ifdef RT35xx
if (IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x80);
#endif /* RT35xx */
}
else
{
ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/
UINT8 bbpValue;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue. */
/* Set the BBP_R82 value here */
bbpValue = 0xF2;
#ifdef RT35xx
if (IS_RT3572(pAd))
{
/* TODO: check if the BBP_R82 value is the same in both of following cases!!!*/
/* Rx High power VGA offset for LNA select*/
bbpValue = 0x94;
}
#endif /* RT35xx */
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, bbpValue);
/* Rx High power VGA offset for LNA select*/
if (pAd->NicConfig2.field.ExternalLNAForA)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x02);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R*/
#ifdef RT35xx
if (IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x00);
#endif /* RT35xx */
{
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
#ifdef RT35xx
if (IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x80);
#endif /* RT35xx */
}
/* R66 should be set according to Channel and use 20MHz when scanning*/
/*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x2E + GET_LNA_GAIN(pAd)));*/
if (bScan)
RTMPSetAGCInitValue(pAd, BW_20);
else
RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW);
/* On 11A, We should delay and wait RF/BBP to be stable*/
/* and the appropriate time should be 1000 micro seconds */
/* 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.*/
RTMPusecDelay(1000);
}
/*
========================================================================
Routine Description:
Set LED Status
Arguments:
pAd Pointer to our adapter
Status LED Status
Return Value:
None
IRQL = PASSIVE_LEVEL
IRQL = DISPATCH_LEVEL
Note:
========================================================================
*/
VOID RTMPSetLEDStatus(RTMP_ADAPTER *pAd, UCHAR Status)
{
/*ULONG data; */
UCHAR LinkStatus = 0;
UCHAR LedMode;
UCHAR MCUCmd = 0;
BOOLEAN bIgnored = FALSE;
#ifdef MT7628
INT LED_CMD = -1;
#endif /*MT7628*/
#ifdef WSC_INCLUDED
#ifdef WSC_LED_SUPPORT
PWSC_CTRL pWscControl = NULL;
#ifdef CONFIG_AP_SUPPORT
pWscControl = &pAd->ApCfg.MBSSID[MAIN_MBSSID].WscControl;
#endif /* CONFIG_AP_SUPPORT */
#ifdef CONFIG_STA_SUPPORT
pWscControl = &pAd->StaCfg.WscControl;
#endif /* CONFIG_STA_SUPPORT */
#endif /* WSC_LED_SUPPORT */
#endif /* WSC_INCLUDED */
#ifdef CONFIG_ATE
/*
In ATE mode of RT2860 AP/STA, we have erased 8051 firmware.
So LED mode is not supported when ATE is running.
*/
if (!IS_RT3572(pAd))
{
if (ATE_ON(pAd))
return;
}
#endif /* CONFIG_ATE */
LedMode = 1;//LED_MODE(pAd);
#ifdef MT7628
if (IS_MT7603(pAd) || IS_MT7628(pAd))
{
if (LedMode < 0 || Status <0 || LedMode > 15 || Status > 11)
return;
else
LED_CMD = LED_Array[LedMode][Status];
}
#endif /*MT7628*/
switch (Status)
{
case LED_LINK_DOWN:
LinkStatus = LINK_STATUS_LINK_DOWN;
pAd->LedCntl.LedIndicatorStrength = 0;
MCUCmd = MCU_SET_LED_MODE;
break;
case LED_LINK_UP:
if (pAd->CommonCfg.Channel > 14)
LinkStatus = LINK_STATUS_ABAND_LINK_UP;
else
LinkStatus = LINK_STATUS_GBAND_LINK_UP;
MCUCmd = MCU_SET_LED_MODE;
break;
case LED_RADIO_ON:
LinkStatus = LINK_STATUS_RADIO_ON;
MCUCmd = MCU_SET_LED_MODE;
break;
case LED_HALT:
LedMode = 0; /* Driver sets MAC register and MAC controls LED */
case LED_RADIO_OFF:
LinkStatus = LINK_STATUS_RADIO_OFF;
MCUCmd = MCU_SET_LED_MODE;
break;
case LED_WPS:
LinkStatus = LINK_STATUS_WPS;
MCUCmd = MCU_SET_LED_MODE;
break;
case LED_ON_SITE_SURVEY:
LinkStatus = LINK_STATUS_ON_SITE_SURVEY;
MCUCmd = MCU_SET_LED_MODE;
break;
case LED_POWER_UP:
LinkStatus = LINK_STATUS_POWER_UP;
MCUCmd = MCU_SET_LED_MODE;
break;
#ifdef CONFIG_ATE
#endif /* CONFIG_ATE */
#ifdef WSC_INCLUDED
#ifdef WSC_LED_SUPPORT
case LED_WPS_IN_PROCESS:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_WPS_IN_PROCESS;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_IN_PROCESS;
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_TRACE, ("%s: LED_WPS_IN_PROCESS\n", __FUNCTION__));
}
else
bIgnored = TRUE;
break;
case LED_WPS_ERROR:
if (WscSupportWPSLEDMode(pAd))
{
/* In the case of LED mode 9, the error LED should be turned on only after WPS walk time expiration. */
if ((pWscControl->bWPSWalkTimeExpiration == FALSE) &&
(LED_MODE(pAd) == WPS_LED_MODE_9))
{
/* do nothing. */
}
else
{
LinkStatus = LINK_STATUS_WPS_ERROR;
MCUCmd = MCU_SET_WPS_LED_MODE;
}
pWscControl->WscLEDMode = LED_WPS_ERROR;
pWscControl->WscLastWarningLEDMode = LED_WPS_ERROR;
}
else
bIgnored = TRUE;
break;
case LED_WPS_SESSION_OVERLAP_DETECTED:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_WPS_SESSION_OVERLAP_DETECTED;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SESSION_OVERLAP_DETECTED;
pWscControl->WscLastWarningLEDMode = LED_WPS_SESSION_OVERLAP_DETECTED;
}
else
bIgnored = TRUE;
break;
case LED_WPS_SUCCESS:
if (WscSupportWPSLEDMode(pAd))
{
if ((LED_MODE(pAd) == WPS_LED_MODE_7) ||
(LED_MODE(pAd) == WPS_LED_MODE_11) ||
(LED_MODE(pAd) == WPS_LED_MODE_12)
)
{
/* In the WPS LED mode 7, 11 and 12, the blue LED would last 300 seconds regardless of the AP's security settings. */
LinkStatus = LINK_STATUS_WPS_SUCCESS_WITH_SECURITY;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
/* Turn off the WPS successful LED pattern after 300 seconds. */
RTMPSetTimer(&pWscControl->WscLEDTimer, WSC_SUCCESSFUL_LED_PATTERN_TIMEOUT);
}
else if (LED_MODE(pAd) == WPS_LED_MODE_8) /* The WPS LED mode 8 */
{
if (WscAPHasSecuritySetting(pAd, pWscControl)) /* The WPS AP has the security setting. */
{
LinkStatus = LINK_STATUS_WPS_SUCCESS_WITH_SECURITY;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
/* Turn off the WPS successful LED pattern after 300 seconds. */
RTMPSetTimer(&pWscControl->WscLEDTimer, WSC_SUCCESSFUL_LED_PATTERN_TIMEOUT);
}
else /* The WPS AP does not have the secuirty setting. */
{
LinkStatus = LINK_STATUS_WPS_SUCCESS_WITHOUT_SECURITY;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
/* Turn off the WPS successful LED pattern after 300 seconds. */
RTMPSetTimer(&pWscControl->WscLEDTimer, WSC_SUCCESSFUL_LED_PATTERN_TIMEOUT);
}
}
else if (LED_MODE(pAd) == WPS_LED_MODE_9) /* The WPS LED mode 9. */
{
/* Always turn on the WPS blue LED for 300 seconds. */
LinkStatus = LINK_STATUS_WPS_BLUE_LED;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
/* Turn off the WPS successful LED pattern after 300 seconds. */
RTMPSetTimer(&pWscControl->WscLEDTimer, WSC_SUCCESSFUL_LED_PATTERN_TIMEOUT);
}
else
{
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_TRACE, ("%s: LED_WPS_SUCCESS (Incorrect LED mode = %d)\n",
__FUNCTION__, LED_MODE(pAd)));
ASSERT(FALSE);
}
}
else
bIgnored = TRUE;
break;
case LED_WPS_TURN_LED_OFF:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_WPS_TURN_LED_OFF;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_TURN_LED_OFF;
}
else
bIgnored = TRUE;
break;
case LED_WPS_TURN_ON_BLUE_LED:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_WPS_BLUE_LED;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
}
else
bIgnored = TRUE;
break;
case LED_NORMAL_CONNECTION_WITHOUT_SECURITY:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_NORMAL_CONNECTION_WITHOUT_SECURITY;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
}
else
bIgnored = TRUE;
break;
case LED_NORMAL_CONNECTION_WITH_SECURITY:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_NORMAL_CONNECTION_WITH_SECURITY;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
}
else
bIgnored = TRUE;
break;
/*WPS LED Mode 10 */
case LED_WPS_MODE10_TURN_ON:
if(WscSupportWPSLEDMode10(pAd))
{
LinkStatus = LINK_STATUS_WPS_MODE10_TURN_ON;
MCUCmd = MCU_SET_WPS_LED_MODE;
}
else
bIgnored = TRUE;
break;
case LED_WPS_MODE10_FLASH:
if(WscSupportWPSLEDMode10(pAd))
{
LinkStatus = LINK_STATUS_WPS_MODE10_FLASH;
MCUCmd = MCU_SET_WPS_LED_MODE;
}
else
bIgnored = TRUE;
break;
case LED_WPS_MODE10_TURN_OFF:
if(WscSupportWPSLEDMode10(pAd))
{
LinkStatus = LINK_STATUS_WPS_MODE10_TURN_OFF;
MCUCmd = MCU_SET_WPS_LED_MODE;;
}
else
bIgnored = TRUE;
break;
#endif /* WSC_LED_SUPPORT */
#endif /* WSC_INCLUDED */
default:
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_WARN, ("RTMPSetLED::Unknown Status 0x%x\n", Status));
break;
}
#ifdef MT7628
if (IS_MT7628(pAd))
{
AndesLedEnhanceOP(pAd, 0, 0, 0, LED_CMD);
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_TRACE, ("%s: LED_CMD:0x%x, LED Mode:0x%x, LinkStatus:0x%x\n", __FUNCTION__, LED_CMD, LedMode, LinkStatus));
} else
#endif /*MT7628*/
if (MCUCmd)
{
AsicSendCommandToMcu(pAd, MCUCmd, 0xff, LedMode, LinkStatus, FALSE);
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_TRACE, ("%s: MCUCmd:0x%x, LED Mode:0x%x, LinkStatus:0x%x\n", __FUNCTION__, MCUCmd, LedMode, LinkStatus));
}
/*
Keep LED status for LED SiteSurvey mode.
After SiteSurvey, we will set the LED mode to previous status.
*/
if ((Status != LED_ON_SITE_SURVEY) && (Status != LED_POWER_UP) && (bIgnored == FALSE))
pAd->LedCntl.LedStatus = Status;
}
VOID RTMPInitPCIeLinkCtrlValue(
IN PRTMP_ADAPTER pAd)
{
INT pos;
USHORT reg16, data2, PCIePowerSaveLevel, Configuration;
UINT32 MacValue;
BOOLEAN bFindIntel = FALSE;
POS_COOKIE pObj;
pObj = (POS_COOKIE) pAd->OS_Cookie;
if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE))
{
DBGPRINT(RT_DEBUG_TRACE, ("Not PCIe device.\n"));
return;
}
DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __FUNCTION__));
// Init EEPROM, and save settings
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)))
{
RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
pAd->PCIePowerSaveLevel = PCIePowerSaveLevel & 0xff;
pAd->LnkCtrlBitMask = 0;
if ((PCIePowerSaveLevel&0xff) == 0xff)
{
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE);
DBGPRINT(RT_DEBUG_TRACE, ("====> PCIePowerSaveLevel = 0x%x.\n", PCIePowerSaveLevel));
return;
}
else
{
PCIePowerSaveLevel &= 0x3;
RT28xx_EEPROM_READ16(pAd, 0x24, data2);
if( !(((data2&0xff00) == 0x9200) && ((data2&0x80) !=0)) )
{
if (PCIePowerSaveLevel > 1 )
PCIePowerSaveLevel = 1;
}
DBGPRINT(RT_DEBUG_TRACE, ("====> Write 0x83 = 0x%x.\n", PCIePowerSaveLevel));
AsicSendCommandToMcu(pAd, TRUE, 0x83, 0xff, (UCHAR)PCIePowerSaveLevel, 0x00);
RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
PCIePowerSaveLevel &= 0xff;
PCIePowerSaveLevel = PCIePowerSaveLevel >> 6;
switch(PCIePowerSaveLevel)
{
case 0: // Only support L0
pAd->LnkCtrlBitMask = 0;
break;
case 1: // Only enable L0s
pAd->LnkCtrlBitMask = 1;
break;
case 2: // enable L1, L0s
pAd->LnkCtrlBitMask = 3;
break;
case 3: // sync with host clk and enable L1, L0s
pAd->LnkCtrlBitMask = 0x103;
break;
}
RT28xx_EEPROM_READ16(pAd, 0x24, data2);
if ((PCIePowerSaveLevel&0xff) != 0xff)
{
PCIePowerSaveLevel &= 0x3;
if( !(((data2&0xff00) == 0x9200) && ((data2&0x80) !=0)) )
{
if (PCIePowerSaveLevel > 1 )
PCIePowerSaveLevel = 1;
}
DBGPRINT(RT_DEBUG_TRACE, ("====> rt28xx Write 0x83 Command = 0x%x.\n", PCIePowerSaveLevel));
printk("\n\n\n%s:%d\n",__FUNCTION__,__LINE__);
AsicSendCommandToMcu(pAd, TRUE, 0x83, 0xff, (UCHAR)PCIePowerSaveLevel, 0x00);
}
DBGPRINT(RT_DEBUG_TRACE, ("====> LnkCtrlBitMask = 0x%x.\n", pAd->LnkCtrlBitMask));
}
}
/*
========================================================================
Routine Description:
Set LED Status
Arguments:
pAd Pointer to our adapter
Status LED Status
Return Value:
None
IRQL = PASSIVE_LEVEL
IRQL = DISPATCH_LEVEL
Note:
========================================================================
*/
VOID RTMPSetLEDStatus(
IN PRTMP_ADAPTER pAd,
IN UCHAR Status)
{
/*ULONG data; */
UCHAR LinkStatus = 0;
UCHAR LedMode;
UCHAR MCUCmd = 0;
BOOLEAN bIgnored = FALSE;
#ifdef WSC_INCLUDED
#ifdef WSC_LED_SUPPORT
PWSC_CTRL pWscControl = NULL;
#ifdef CONFIG_AP_SUPPORT
pWscControl = &pAd->ApCfg.MBSSID[MAIN_MBSSID].WscControl;
#endif /* CONFIG_AP_SUPPORT */
#ifdef CONFIG_STA_SUPPORT
pWscControl = &pAd->StaCfg.WscControl;
#endif /* CONFIG_STA_SUPPORT */
#endif /* WSC_LED_SUPPORT */
#endif /* WSC_INCLUDED */
#ifdef RALINK_ATE
/*
In ATE mode of RT2860 AP/STA, we have erased 8051 firmware.
So LED mode is not supported when ATE is running.
*/
if (!IS_RT3572(pAd))
{
if (ATE_ON(pAd))
return;
}
#endif /* RALINK_ATE */
LedMode = LED_MODE(pAd);
switch (Status)
{
case LED_LINK_DOWN:
LinkStatus = LINK_STATUS_LINK_DOWN;
pAd->LedCntl.LedIndicatorStrength = 0;
MCUCmd = MCU_SET_LED_MODE;
break;
case LED_LINK_UP:
if (pAd->CommonCfg.Channel > 14)
LinkStatus = LINK_STATUS_ABAND_LINK_UP;
else
LinkStatus = LINK_STATUS_GBAND_LINK_UP;
MCUCmd = MCU_SET_LED_MODE;
break;
case LED_RADIO_ON:
LinkStatus = LINK_STATUS_RADIO_ON;
MCUCmd = MCU_SET_LED_MODE;
break;
case LED_HALT:
LedMode = 0; /* Driver sets MAC register and MAC controls LED */
case LED_RADIO_OFF:
LinkStatus = LINK_STATUS_RADIO_OFF;
MCUCmd = MCU_SET_LED_MODE;
break;
case LED_WPS:
LinkStatus = LINK_STATUS_WPS;
MCUCmd = MCU_SET_LED_MODE;
break;
case LED_ON_SITE_SURVEY:
LinkStatus = LINK_STATUS_ON_SITE_SURVEY;
MCUCmd = MCU_SET_LED_MODE;
break;
case LED_POWER_UP:
LinkStatus = LINK_STATUS_POWER_UP;
MCUCmd = MCU_SET_LED_MODE;
break;
#ifdef RALINK_ATE
#endif /* RALINK_ATE */
#ifdef WSC_INCLUDED
#ifdef WSC_LED_SUPPORT
#ifdef CONFIG_WIFI_LED_SHARE
case LED_WPS_PRE_STAGE:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_WPS_PRE_STAGE;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_PRE_STAGE;
}
else
bIgnored = TRUE;
break;
case LED_WPS_POST_STAGE:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_WPS_PRE_STAGE;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_POST_STAGE;
}
else
bIgnored = TRUE;
break;
#endif /* CONFIG_WIFI_LED_SHARE */
case LED_WPS_IN_PROCESS:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_WPS_IN_PROCESS;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_IN_PROCESS;
DBGPRINT(RT_DEBUG_TRACE, ("%s: LED_WPS_IN_PROCESS\n", __FUNCTION__));
}
else
bIgnored = TRUE;
break;
case LED_WPS_ERROR:
if (WscSupportWPSLEDMode(pAd))
{
/* In the case of LED mode 9, the error LED should be turned on only after WPS walk time expiration. */
if ((pWscControl->bWPSWalkTimeExpiration == FALSE) &&
(LED_MODE(pAd) == WPS_LED_MODE_9))
{
/* do nothing. */
}
else
{
LinkStatus = LINK_STATUS_WPS_ERROR;
MCUCmd = MCU_SET_WPS_LED_MODE;
}
pWscControl->WscLEDMode = LED_WPS_ERROR;
pWscControl->WscLastWarningLEDMode = LED_WPS_ERROR;
}
else
bIgnored = TRUE;
break;
case LED_WPS_SESSION_OVERLAP_DETECTED:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_WPS_SESSION_OVERLAP_DETECTED;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SESSION_OVERLAP_DETECTED;
pWscControl->WscLastWarningLEDMode = LED_WPS_SESSION_OVERLAP_DETECTED;
}
else
bIgnored = TRUE;
break;
case LED_WPS_SUCCESS:
if (WscSupportWPSLEDMode(pAd))
{
if ((LED_MODE(pAd) == WPS_LED_MODE_7) ||
(LED_MODE(pAd) == WPS_LED_MODE_11) ||
(LED_MODE(pAd) == WPS_LED_MODE_12)
#ifdef CONFIG_WIFI_LED_SHARE
||(LED_MODE(pAd) == WPS_LED_MODE_SHARE)
#endif /* CONFIG_WIFI_LED_SHARE */
)
{
/* In the WPS LED mode 7, 11 and 12, the blue LED would last 300 seconds regardless of the AP's security settings. */
LinkStatus = LINK_STATUS_WPS_SUCCESS_WITH_SECURITY;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
/* Turn off the WPS successful LED pattern after 300 seconds. */
RTMPSetTimer(&pWscControl->WscLEDTimer, WSC_SUCCESSFUL_LED_PATTERN_TIMEOUT);
}
else if (LED_MODE(pAd) == WPS_LED_MODE_8) /* The WPS LED mode 8 */
{
if (WscAPHasSecuritySetting(pAd, pWscControl)) /* The WPS AP has the security setting. */
{
LinkStatus = LINK_STATUS_WPS_SUCCESS_WITH_SECURITY;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
/* Turn off the WPS successful LED pattern after 300 seconds. */
RTMPSetTimer(&pWscControl->WscLEDTimer, WSC_SUCCESSFUL_LED_PATTERN_TIMEOUT);
}
else /* The WPS AP does not have the secuirty setting. */
{
LinkStatus = LINK_STATUS_WPS_SUCCESS_WITHOUT_SECURITY;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
/* Turn off the WPS successful LED pattern after 300 seconds. */
RTMPSetTimer(&pWscControl->WscLEDTimer, WSC_SUCCESSFUL_LED_PATTERN_TIMEOUT);
}
}
else if (LED_MODE(pAd) == WPS_LED_MODE_9) /* The WPS LED mode 9. */
{
/* Always turn on the WPS blue LED for 300 seconds. */
LinkStatus = LINK_STATUS_WPS_BLUE_LED;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
/* Turn off the WPS successful LED pattern after 300 seconds. */
RTMPSetTimer(&pWscControl->WscLEDTimer, WSC_SUCCESSFUL_LED_PATTERN_TIMEOUT);
}
else
{
DBGPRINT(RT_DEBUG_TRACE, ("%s: LED_WPS_SUCCESS (Incorrect LED mode = %d)\n",
__FUNCTION__, LED_MODE(pAd)));
ASSERT(FALSE);
}
}
else
bIgnored = TRUE;
break;
case LED_WPS_TURN_LED_OFF:
if (WscSupportWPSLEDMode(pAd))
{
#ifdef CONFIG_WIFI_LED_SHARE
USHORT value;
RT28xx_EEPROM_READ16(pAd, EEPROM_FREQ_OFFSET, value);
pAd->LedCntl.MCULedCntl.word = (value >> 8);
#endif /* CONFIG_WIFI_LED_SHARE */
LinkStatus = LINK_STATUS_WPS_TURN_LED_OFF;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_TURN_LED_OFF;
}
else
bIgnored = TRUE;
break;
case LED_WPS_TURN_ON_BLUE_LED:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_WPS_BLUE_LED;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
}
else
bIgnored = TRUE;
break;
case LED_NORMAL_CONNECTION_WITHOUT_SECURITY:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_NORMAL_CONNECTION_WITHOUT_SECURITY;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
}
else
bIgnored = TRUE;
break;
case LED_NORMAL_CONNECTION_WITH_SECURITY:
if (WscSupportWPSLEDMode(pAd))
{
LinkStatus = LINK_STATUS_NORMAL_CONNECTION_WITH_SECURITY;
MCUCmd = MCU_SET_WPS_LED_MODE;
pWscControl->WscLEDMode = LED_WPS_SUCCESS;
}
else
bIgnored = TRUE;
break;
/*WPS LED Mode 10 */
case LED_WPS_MODE10_TURN_ON:
if(WscSupportWPSLEDMode10(pAd))
{
LinkStatus = LINK_STATUS_WPS_MODE10_TURN_ON;
MCUCmd = MCU_SET_WPS_LED_MODE;
}
else
bIgnored = TRUE;
break;
case LED_WPS_MODE10_FLASH:
if(WscSupportWPSLEDMode10(pAd))
{
LinkStatus = LINK_STATUS_WPS_MODE10_FLASH;
MCUCmd = MCU_SET_WPS_LED_MODE;
}
else
bIgnored = TRUE;
break;
case LED_WPS_MODE10_TURN_OFF:
if(WscSupportWPSLEDMode10(pAd))
{
LinkStatus = LINK_STATUS_WPS_MODE10_TURN_OFF;
MCUCmd = MCU_SET_WPS_LED_MODE;;
}
else
bIgnored = TRUE;
break;
#endif /* WSC_LED_SUPPORT */
#endif /* WSC_INCLUDED */
default:
DBGPRINT(RT_DEBUG_WARN, ("RTMPSetLED::Unknown Status 0x%x\n", Status));
break;
}
VOID RT35xx_ChipBBPAdjust(
IN RTMP_ADAPTER *pAd)
{
UINT32 Value;
UCHAR byteValue = 0;
#ifdef RT3593
/* 3x3 device will not run AsicEvaluateRxAnt*/
if (IS_RT3593(pAd))
{
UCHAR BBPValue = 0;
/* Receiver Antenna Selection*/
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPValue);
if(pAd->Antenna.field.RxPath == 3)
{
BBPValue |= (0x10);
}
else if(pAd->Antenna.field.RxPath == 2)
{
BBPValue |= (0x8);
}
else if(pAd->Antenna.field.RxPath == 1)
{
BBPValue |= (0x0);
}
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPValue);
/*Number of transmitter chains*/
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BBPValue);
BBPValue &= (~0x18);
if (pAd->Antenna.field.TxPath == 3)
BBPValue |= 0x10;
else if (pAd->Antenna.field.TxPath == 2)
BBPValue |= 0x08;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BBPValue);
}
#endif /* RT3593 */
#ifdef DOT11_N_SUPPORT
if ((pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth == BW_40) &&
(pAd->CommonCfg.RegTransmitSetting.field.EXTCHA == EXTCHA_ABOVE))
{
pAd->CommonCfg.BBPCurrentBW = BW_40;
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel + 2;
/* TX : control channel at lower */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x1);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* RX : control channel at lower */
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &byteValue);
byteValue &= (~0x20);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, byteValue);
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue);
byteValue &= (~0x18);
byteValue |= 0x10;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue);
if (pAd->CommonCfg.Channel > 14)
{ /* request by Gary 20070208 for middle and long range A Band*/
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x48, RX_CHAIN_ALL);
}
else
{ /* request by Gary 20070208 for middle and long range G Band*/
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x38, RX_CHAIN_ALL);
}
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10);
}
DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : ExtAbove, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n",
pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth,
pAd->CommonCfg.Channel,
pAd->CommonCfg.RegTransmitSetting.field.EXTCHA,
pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset));
}
else if ((pAd->CommonCfg.Channel > 2) &&
(pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth == BW_40) &&
(pAd->CommonCfg.RegTransmitSetting.field.EXTCHA == EXTCHA_BELOW))
{
pAd->CommonCfg.BBPCurrentBW = BW_40;
if (pAd->CommonCfg.Channel == 14)
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel - 1;
else
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel - 2;
/* TX : control channel at upper */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value |= (0x1);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* RX : control channel at upper */
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &byteValue);
byteValue |= (0x20);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, byteValue);
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue);
byteValue &= (~0x18);
byteValue |= 0x10;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue);
if (pAd->CommonCfg.Channel > 14)
{ /* request by Gary 20070208 for middle and long range A Band*/
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x48, RX_CHAIN_ALL);
}
else
{ /* request by Gary 20070208 for middle and long range G band*/
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x38, RX_CHAIN_ALL);
}
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10);
}
DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : ExtBlow, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n",
pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth,
pAd->CommonCfg.Channel,
pAd->CommonCfg.RegTransmitSetting.field.EXTCHA,
pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset));
}
else
#endif /* DOT11_N_SUPPORT */
{
pAd->CommonCfg.BBPCurrentBW = BW_20;
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel;
/* TX : control channel at lower */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x1);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue);
byteValue &= (~0x18);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue);
/* 20 MHz bandwidth*/
if (pAd->CommonCfg.Channel > 14)
{ /* request by Gary 20070208*/
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x40, RX_CHAIN_ALL);
}
else
{ /* request by Gary 20070208*/
/*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, 0x30);*/
/* request by Brian 20070306*/
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x38, RX_CHAIN_ALL);
}
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x08);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x11);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0a);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10);
}
#ifdef DOT11_N_SUPPORT
DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : 20MHz, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n",
pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth,
pAd->CommonCfg.Channel,
pAd->CommonCfg.RegTransmitSetting.field.EXTCHA,
pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset));
#endif /* DOT11_N_SUPPORT */
}
if (pAd->CommonCfg.Channel > 14)
{ /* request by Gary 20070208 for middle and long range A Band*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x1D);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x1D);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x1D);
/*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x1D);*/
}
else
{ /* request by Gary 20070208 for middle and long range G band*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x2D);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x2D);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x2D);
/*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x2D);*/
}
}
/*
==========================================================================
Description:
Reverse RF sleep-mode setup
==========================================================================
*/
VOID RT30xxReverseRFSleepModeSetup(
IN PRTMP_ADAPTER pAd)
{
UCHAR RFValue;
UINT32 MACValue;
if(!IS_RT3572(pAd))
{
#ifdef RT53xx
if (IS_RT5390(pAd))
{
UCHAR rfreg;
RT30xxReadRFRegister(pAd, RF_R01, &rfreg);
if (IS_RT5392(pAd))
{
rfreg = ((rfreg & ~0x3F) | 0x3F);
}
else
{
rfreg = ((rfreg & ~0x0F) | 0x0F); // Enable rf_block_en, pll_en, rx0_en and tx0_en
}
RT30xxWriteRFRegister(pAd, RF_R01, rfreg);
RT30xxReadRFRegister(pAd, RF_R06, &rfreg);
if (IS_RT5390F(pAd) || IS_RT5392C(pAd))
{
rfreg = ((rfreg & ~0xC0) | 0xC0); // vco_ic (VCO bias current control, 11: high)
}
else
{
rfreg = ((rfreg & ~0xC0) | 0x80); // vco_ic (VCO bias current control, 10: mid.)
}
RT30xxWriteRFRegister(pAd, RF_R06, rfreg);
if (!IS_RT5392(pAd))
{
RT30xxReadRFRegister(pAd, RF_R02, &rfreg);
rfreg = ((rfreg & ~0x80) | 0x80); // rescal_en (initiate calibration)
RT30xxWriteRFRegister(pAd, RF_R02, rfreg);
}
RT30xxReadRFRegister(pAd, RF_R22, &rfreg);
rfreg = ((rfreg & ~0xE0) | 0x20); // cp_ic (reference current control, 001: 0.33 mA)
RT30xxWriteRFRegister(pAd, RF_R22, rfreg);
RT30xxReadRFRegister(pAd, RF_R42, &rfreg);
rfreg = ((rfreg & ~0x40) | 0x40); // rx_ctb_en
RT30xxWriteRFRegister(pAd, RF_R42, rfreg);
RT30xxReadRFRegister(pAd, RF_R20, &rfreg);
rfreg = ((rfreg & ~0x77) | 0x00); // ldo_rf_vc and ldo_pll_vc ( 111: +0.15)
RT30xxWriteRFRegister(pAd, RF_R20, rfreg);
RT30xxReadRFRegister(pAd, RF_R03, &rfreg);
rfreg = ((rfreg & ~0x80) | 0x80); // vcocal_en (initiate VCO calibration (reset after completion))
RT30xxWriteRFRegister(pAd, RF_R03, rfreg);
}
else
#endif // RT53xx //
{
// RF_BLOCK_en, RF R1 register Bit 0 to 1
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue |= 0x01;
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
// VCO_IC, RF R7 register Bit 5 to 1 (VCO bias current control, 11: high)
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue |= 0x30;
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue |= 0x0E;
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
// RX_CTB_en, RF R21 register Bit 7 to 1
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
}
if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72
IS_RT3572(pAd) ||
IS_RT3390(pAd) ||
IS_RT3593(pAd) ||
IS_RT5390(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
{
if ((!IS_RT3572(pAd)) && (!IS_RT3593(pAd)) && (!IS_RT5390(pAd)) && (!IS_RT3390(pAd)) && (!IS_RT3090(pAd)))
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
if ((pAd->MACVersion & 0xffff) < 0x0211)
RFValue = (RFValue & (~0x77)) | 0x3;
else
RFValue = (RFValue & (~0x77));
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
}
// RT3071 version E has fixed this issue
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
// patch tx EVM issue temporarily
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
// else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd)) || (pAd->CommonCfg.PatchHWControl.field.LDOCfg == 1))
else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd) && !IS_RT5390(pAd)))
{
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
if(IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, 0x80);
}
/*
==========================================================================
Description:
Load RF sleep-mode setup
==========================================================================
*/
VOID RT30xxLoadRFSleepModeSetup(
IN PRTMP_ADAPTER pAd)
{
UCHAR RFValue;
UINT32 MACValue;
if(!IS_RT3572(pAd))
{
#ifdef RT53xx
if (IS_RT5390(pAd))
{
UCHAR rfreg;
RT30xxReadRFRegister(pAd, RF_R01, &rfreg);
rfreg = ((rfreg & ~0x01) | 0x00); // vco_en
RT30xxWriteRFRegister(pAd, RF_R01, rfreg);
RT30xxReadRFRegister(pAd, RF_R06, &rfreg);
rfreg = ((rfreg & ~0xC0) | 0x00); // vco_ic (VCO bias current control, 00: off)
RT30xxWriteRFRegister(pAd, RF_R06, rfreg);
RT30xxReadRFRegister(pAd, RF_R22, &rfreg);
rfreg = ((rfreg & ~0xE0) | 0x00); // cp_ic (reference current control, 000: 0.25 mA)
RT30xxWriteRFRegister(pAd, RF_R22, rfreg);
RT30xxReadRFRegister(pAd, RF_R42, &rfreg);
rfreg = ((rfreg & ~0x40) | 0x00); // rx_ctb_en
RT30xxWriteRFRegister(pAd, RF_R42, rfreg);
/*
RT30xxReadRFRegister(pAd, RF_R20, &rfreg);
rfreg = ((rfreg & ~0x77) | 0x77); // ldo_pll_vc and ldo_rf_vc (111: -0.15)
RT30xxWriteRFRegister(pAd, RF_R20, rfreg);
*/
}
else
#endif // RT53xx //
{
// RF_BLOCK_en. RF R1 register Bit 0 to 0
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue &= (~0x01);
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
// VCO_IC, RF R7 register Bit 4 & Bit 5 to 0
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue &= (~0x30);
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue &= (~0x0E);
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
// RX_CTB_en, RF R21 register Bit 7 to 0
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue &= (~0x80);
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
}
// Don't touch LDO_CFG0 for 3090F & 3593, possibly the board is single power scheme
if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72
IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT5390(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
{
if (!IS_RT3572(pAd) && !IS_RT3390(pAd) && !IS_RT5390(pAd) && !IS_RT3090(pAd))
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
RFValue |= 0x77;
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue |= 0x1D000000;
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
}
/*
========================================================================
Routine Description:
For RF filter calibration purpose
Arguments:
pAd Pointer to our adapter
Return Value:
None
IRQL = PASSIVE_LEVEL
========================================================================
*/
VOID RTMPFilterCalibration(
IN PRTMP_ADAPTER pAd)
{
UCHAR R55x = 0, value, FilterTarget = 0x1E, BBPValue=0;
UINT loop = 0, count = 0, loopcnt = 0, ReTry = 0;
UCHAR RF_R24_Value = 0;
// Give bbp filter initial value
pAd->Mlme.CaliBW20RfR24 = 0x1F;
pAd->Mlme.CaliBW40RfR24 = 0x2F; //Bit[5] must be 1 for BW 40
do
{
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
return;
if (loop == 1) //BandWidth = 40 MHz
{
// Write 0x27 to RF_R24 to program filter
RT30xxReadRFRegister(pAd, RF_R24, (PUCHAR)(&RF_R24_Value));
RF_R24_Value = (RF_R24_Value & 0xC0) | 0x27; // <bit 5>:tx_h20M<bit 5> and <bit 4:0>:tx_agc_fc<bit 4:0>
RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
if (IS_RT3071(pAd) || IS_RT3572(pAd))
FilterTarget = 0x15;
else
FilterTarget = 0x19;
// when calibrate BW40, BBP mask must set to BW40.
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
BBPValue&= (~0x18);
BBPValue|= (0x10);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
// set to BW40
RT30xxReadRFRegister(pAd, RF_R31, &value);
value |= 0x20;
RT30xxWriteRFRegister(pAd, RF_R31, value);
}
else //BandWidth = 20 MHz
{
// Write 0x07 to RF_R24 to program filter
RT30xxReadRFRegister(pAd, RF_R24, (PUCHAR)(&RF_R24_Value));
RF_R24_Value = (RF_R24_Value & 0xC0) | 0x07; // <bit 5>:tx_h20M<bit 5> and <bit 4:0>:tx_agc_fc<bit 4:0>
RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
if (IS_RT3071(pAd) || IS_RT3572(pAd))
FilterTarget = 0x13;
else
FilterTarget = 0x16;
// set to BW20
RT30xxReadRFRegister(pAd, RF_R31, &value);
value &= (~0x20);
RT30xxWriteRFRegister(pAd, RF_R31, value);
}
// Write 0x01 to RF_R22 to enable baseband loopback mode
RT30xxReadRFRegister(pAd, RF_R22, &value);
value |= 0x01;
RT30xxWriteRFRegister(pAd, RF_R22, value);
// Write 0x00 to BBP_R24 to set power & frequency of passband test tone
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);
do
{
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
return;
// Write 0x90 to BBP_R25 to transmit test tone
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);
RTMPusecDelay(1000);
// Read BBP_R55[6:0] for received power, set R55x = BBP_R55[6:0]
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
R55x = value & 0xFF;
} while ((ReTry++ < 100) && (R55x == 0));
// Write 0x06 to BBP_R24 to set power & frequency of stopband test tone
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0x06);
while(TRUE)
{
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
return;
// Write 0x90 to BBP_R25 to transmit test tone
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);
//We need to wait for calibration
RTMPusecDelay(1000);
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
value &= 0xFF;
if ((R55x - value) < FilterTarget)
{
RF_R24_Value ++;
}
else if ((R55x - value) == FilterTarget)
{
RF_R24_Value ++;
count ++;
}
else
{
break;
}
// prevent infinite loop cause driver hang.
if (loopcnt++ > 100)
{
DBGPRINT(RT_DEBUG_ERROR, ("RTMPFilterCalibration - can't find a valid value, loopcnt=%d stop calibrating", loopcnt));
break;
}
// Write RF_R24 to program filter
RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
}
if (count > 0)
{
RF_R24_Value = RF_R24_Value - ((count) ? (1) : (0));
}
// Store for future usage
if (loopcnt < 100)
{
if (loop++ == 0)
{
//BandWidth = 20 MHz
pAd->Mlme.CaliBW20RfR24 = (UCHAR)RF_R24_Value;
}
else
{
//BandWidth = 40 MHz
pAd->Mlme.CaliBW40RfR24 = (UCHAR)RF_R24_Value;
break;
}
}
else
break;
RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
// reset count
count = 0;
} while(TRUE);
//
// Set back to initial state
//
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);
RT30xxReadRFRegister(pAd, RF_R22, &value);
value &= ~(0x01);
RT30xxWriteRFRegister(pAd, RF_R22, value);
//
// Check BBP R25 RF Calibration at bit 4. Patch from windows driver
//
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R25, &BBPValue);
if (BBPValue & 0x10)
{
//
// Clear RF calibration
//
BBPValue &= (~0x10);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, BBPValue);
DBGPRINT(RT_DEBUG_WARN, ("RTMPFilterCalibration, RF calibration should be done\n"));
}
// set BBP back to BW20
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
BBPValue&= (~0x18);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
DBGPRINT(RT_DEBUG_TRACE, ("RTMPFilterCalibration - CaliBW20RfR24=0x%x, CaliBW40RfR24=0x%x\n", pAd->Mlme.CaliBW20RfR24, pAd->Mlme.CaliBW40RfR24));
}
VOID NICInitRT3370RFRegisters(IN PRTMP_ADAPTER pAd)
{
INT i;
// Driver must read EEPROM to get RfIcType before initial RF registers
// Initialize RF register to default value
if (IS_RT3090(pAd)||IS_RT3390(pAd)||IS_RT3572(pAd))
{
// Init RF calibration
// Driver should toggle RF R30 bit7 before init RF registers
UINT32 RfReg = 0, data;
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
// init R24, R31
RT30xxWriteRFRegister(pAd, RF_R24, 0x0F);
RT30xxWriteRFRegister(pAd, RF_R31, 0x0F);
if (IS_RT3390(pAd))
{
// patch LNA_PE_G1 failed issue
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
// RF registers initialization
for (i = 0; i < NUM_RF_REG_PARMS_OVER_RT3390; i++)
{
RT30xxWriteRFRegister(pAd, RFRegTableOverRT3390[i].Register, RFRegTableOverRT3390[i].Value);
}
}
// patch LNA_PE_G1 failed issue
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
// Initialize RF register to default value
for (i = 0; i < NUM_RF_REG_PARMS_OVER_RT3390; i++)
{
RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value);
}
// Driver should set RF R6 bit6 on before calibration
RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
//For RF filter Calibration
RTMPFilterCalibration(pAd);
// Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration()
if ((pAd->MACVersion & 0xffff) < 0x0211)
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
// set led open drain enable
RTMP_IO_READ32(pAd, OPT_14, &data);
data |= 0x01;
RTMP_IO_WRITE32(pAd, OPT_14, data);
// set default antenna as main
if (pAd->RfIcType == RFIC_3020)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
// add by johnli, RF power sequence setup, load RF normal operation-mode setup
RT30xxLoadRFNormalModeSetup(pAd);
}
}