/* * Description: * Calls fetch and dispatches an instruction at the same cycle (if possible) * Inputs: * trace: instruction trace with all the instructions executed * current_cycle: the cycle we are at * Returns: * None */ void fetch_To_dispatch(instruction_trace_t* trace, int current_cycle) { /* ECE552: YOUR CODE GOES HERE */ /* ECE552 Assignment 3 - BEGIN CODE */ if(instr_queue_size < INSTR_QUEUE_SIZE && fetch_index <= sim_num_insn){ instruction_t *currInstr = get_instr(trace, fetch_index); while(currInstr && (IS_TRAP(currInstr->op))){ fetch_index++; currInstr = get_instr(trace, fetch_index); } if(currInstr){ currInstr->tom_dispatch_cycle = current_cycle; fetch(trace); } } //Resolve target and source operand dependence //Set map table of r_out to tag which reservation //station will produce the result if(instr_front() && USES_FP_FU(instr_front()->op)){ int i; for(i = 0; i < RESERV_FP_SIZE; i++){ if(!reservFP[i]){ reservFP[i] = instr_front(); //Make sure we mark the existing raw dependences //BEFORE updating the map table with my target regs markRAWDependence(reservFP[i]); updateMapTable(reservFP[i]); instr_pop(); break; } } } else if(instr_front() && (USES_INT_FU(instr_front()->op) || instr_front()->op == 0)){ int i; for(i = 0; i < RESERV_INT_SIZE; i++){ if(!reservINT[i]){ reservINT[i] = instr_front(); markRAWDependence(reservINT[i]); updateMapTable(reservINT[i]); instr_pop(); break; } } } else if(instr_front() && (IS_COND_CTRL(instr_front()->op) || IS_UNCOND_CTRL(instr_front()->op))) { instr_pop(); } return; /* ECE552 Assignment 3 - END CODE */ }
/* * The function looks through the trace and finds the next non trap instruction. */ instruction_t* get_next_non_trap_instr (instruction_trace_t* trace) { instruction_t* ret = NULL; while (fetch_index <= 1000000 && IS_TRAP(get_instr(trace, fetch_index)->op)) { fetch_index++; } if (fetch_index <= 1000000) { ret = get_instr(trace, fetch_index); } return ret; }
/* * Description: * Grabs an instruction from the instruction trace (if possible) * Inputs: * trace: instruction trace with all the instructions executed * Returns: * None */ void fetch(instruction_trace_t* trace, int current_cycle) { /* ECE552 Assignment 4 - BEGIN CODE */ fetch_index++; while(IS_TRAP(trace->table[fetch_index].op)) { fetch_index++; } instr_queue[instr_queue_size] = &trace->table[fetch_index]; instr_queue[instr_queue_size]->tom_dispatch_cycle = current_cycle; instr_queue_size++; /* ECE552 Assignment 4 - END CODE */ }
static int first_nibble_is_c(RAnal* anal, RAnalOp* op, ut16 code){ if (IS_TRAP(code)){ op->type = R_ANAL_OP_TYPE_SWI; op->val = (ut8)(code&0xFF); } else if (IS_MOVA_PCREL_R0(code)){ op->type = R_ANAL_OP_TYPE_MOV; op->src[0] = anal_pcrel_disp_mov(anal,op,code&0xFF); op->dst = anal_fill_ai_rg(anal,0); //Always R0 } else if (IS_AND_IMM_R0(code)){ op->type = R_ANAL_OP_TYPE_AND; op->src[0] = anal_fill_im(anal,code&0xFF); op->dst = anal_fill_ai_rg(anal,0); //Always R0 } else if (IS_OR_IMM_R0(code)){ op->type = R_ANAL_OP_TYPE_OR; op->src[0] = anal_fill_im(anal,code&0xFF); op->dst = anal_fill_ai_rg(anal,0); //Always R0 } else if (IS_XOR_IMM_R0(code)){ op->type = R_ANAL_OP_TYPE_XOR; op->src[0] = anal_fill_im(anal,code&0xFF); op->dst = anal_fill_ai_rg(anal,0); //Always R0 } //TODO Logic insns referencing GBR return op->size; }
static int first_nibble_is_c(RAnal* anal, RAnalOp* op, ut16 code){ if (IS_TRAP(code)) { op->type = R_ANAL_OP_TYPE_SWI; op->val = (ut8)(code&0xFF); } else if (IS_MOVA_PCREL_R0(code)) { // 11000111i8p4.... mova @(<disp>,PC),R0 op->type = R_ANAL_OP_TYPE_LEA; op->src[0] = anal_pcrel_disp_mov (anal, op, code&0xFF, LONG_SIZE); //this is wrong ! op->dst = anal_fill_ai_rg (anal, 0); //Always R0 } else if (IS_BINLOGIC_IMM_R0(code)) { // 110010__i8 (binop) #imm, R0 op->src[0] = anal_fill_im (anal, code&0xFF); op->src[1] = anal_fill_ai_rg (anal, 0); //Always R0 op->dst = anal_fill_ai_rg (anal, 0); //Always R0 except tst #imm, R0 switch (code & 0xFF00) { case 0xC800: //tst //TODO : get correct op->dst ! (T flag) op->type = R_ANAL_OP_TYPE_ACMP; break; case 0xC900: //and op->type = R_ANAL_OP_TYPE_AND; break; case 0xCA00: //xor op->type = R_ANAL_OP_TYPE_XOR; break; case 0xCB00: //or op->type = R_ANAL_OP_TYPE_OR; break; } } else if (IS_BINLOGIC_IMM_GBR(code)) { //110011__i8 (binop).b #imm, @(R0,GBR) op->src[0] = anal_fill_im (anal, code&0xFF); switch (code & 0xFF00) { case 0xCC00: //tst //TODO : get correct op->dst ! (T flag) op->type = R_ANAL_OP_TYPE_ACMP; break; case 0xCD00: //and op->type = R_ANAL_OP_TYPE_AND; break; case 0xCE00: //xor op->type = R_ANAL_OP_TYPE_XOR; break; case 0xCF00: //or op->type = R_ANAL_OP_TYPE_OR; break; } //TODO : implement @(R0,GBR) dest and src[1] } else if (IS_MOVB_R0_GBRREF(code)) { //11000000i8*1.... mov.b R0,@(<disp>,GBR) op->type = R_ANAL_OP_TYPE_STORE; op->src[0] = anal_fill_ai_rg (anal, 0); //todo: implement @(disp,GBR) dest } else if (IS_MOVW_R0_GBRREF(code)) { //11000001i8*2.... mov.w R0,@(<disp>,GBR) op->type = R_ANAL_OP_TYPE_STORE; op->src[0] = anal_fill_ai_rg (anal, 0); //todo: implement @(disp,GBR) dest } else if (IS_MOVL_R0_GBRREF(code)) { //11000010i8*4.... mov.l R0,@(<disp>,GBR) op->type = R_ANAL_OP_TYPE_STORE; op->src[0] = anal_fill_ai_rg (anal, 0); //todo: implement @(disp,GBR) dest } else if (IS_MOVB_GBRREF_R0(code)) { //11000100i8*1.... mov.b @(<disp>,GBR),R0 op->type = R_ANAL_OP_TYPE_LOAD; op->dst = anal_fill_ai_rg (anal, 0); //todo: implement @(disp,GBR) src } else if (IS_MOVW_GBRREF_R0(code)) { //11000101i8*2.... mov.w @(<disp>,GBR),R0 op->type = R_ANAL_OP_TYPE_LOAD; op->dst = anal_fill_ai_rg (anal, 0); //todo: implement @(disp,GBR) src } else if (IS_MOVL_GBRREF_R0(code)) { //11000110i8*4.... mov.l @(<disp>,GBR),R0 op->type = R_ANAL_OP_TYPE_LOAD; op->dst = anal_fill_ai_rg (anal, 0); //todo: implement @(disp,GBR) src } return op->size; }