/*
** For each end of frame interrupt base and ceiling is reconfigured
*/
static void LCDIsr(void)
{
unsigned int status;
IntSystemStatusClear(SYS_INT_LCDINT);
status = RasterIntStatus(SOC_LCDC_0_REGS,RASTER_END_OF_FRAME0_INT_STAT |
RASTER_END_OF_FRAME1_INT_STAT );
status = RasterClearGetIntStatus(SOC_LCDC_0_REGS, status);
if (status & RASTER_END_OF_FRAME0_INT_STAT)
{
/* configuring the base ceiling */
RasterDMAFBConfig(SOC_LCDC_0_REGS,
(unsigned int)(g_pucBuffer+4),
(unsigned int)(g_pucBuffer+4) + sizeof(g_pucBuffer) - 2 - 4,
0);
}
if(status & RASTER_END_OF_FRAME1_INT_STAT)
{
RasterDMAFBConfig(SOC_LCDC_0_REGS,
(unsigned int)(g_pucBuffer+4),
(unsigned int)(g_pucBuffer+4) + sizeof(g_pucBuffer) - 2 - 4,
1);
}
}
/*
** For each end of frame interrupt base and ceiling is reconfigured
*/
static void LCDIsr(void)
{
unsigned int status;
#ifdef _TMS320C6X
IntEventClear(SYS_INT_LCDC_INT);
#else
IntSystemStatusClear(SYS_INT_LCDINT);
#endif
status = RasterIntStatus(SOC_LCDC_0_REGS,RASTER_END_OF_FRAME0_INT_STAT |
RASTER_END_OF_FRAME1_INT_STAT );
status = RasterClearGetIntStatus(SOC_LCDC_0_REGS, status);
/* Read the timer counter, to see how much time has elapsed */
/*if(trIndex < TIME_ELAPSED_INST)
frameTransferRate[trIndex++] = TimerCounterGet(SOC_TMR_2_REGS, TMR_TIMER12);*/
if (status & RASTER_END_OF_FRAME0_INT_STAT)
{
flagA = 1;
}
if(status & RASTER_END_OF_FRAME1_INT_STAT)
{
flagB = 1;
}
/* since the frame buffers are constant no need to re-configure again.*/
}
/*
** VPIF Interrupt service routine.
*/
static void VPIFIsr(void)
{
#ifdef _TMS320C6X
IntEventClear(SYS_INT_VPIF_INT);
#else
IntSystemStatusClear(SYS_INT_VPIF);
#endif
/* If previously captured frame not processed, clear this interrupt and return */
if (!processed)
{
VPIFInterruptStatusClear(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0);
return;
}
/* buffcount represents buffer to be given to capture driver and
* buffcount2 represents the newly captured buffer to be processed */
processed = 0;
captured = 0;
buffcount++;
buffcount2 = buffcount - 1;
/* Currently only two buffers are being used for capture */
if (buffcount == 2)
buffcount = 0;
/* Invalidate the buffers before giving to capture driver*/
#ifdef _TMS320C6X
CacheInv((unsigned int) buff_luma[buffcount],
CAPTURE_IMAGE_WIDTH * CAPTURE_IMAGE_HEIGHT * 2);
CacheInv((unsigned int) buff_chroma[buffcount],
CAPTURE_IMAGE_WIDTH * CAPTURE_IMAGE_HEIGHT * 2);
#else
CP15ICacheFlushBuff((unsigned int) buff_luma[buffcount],
CAPTURE_IMAGE_WIDTH * CAPTURE_IMAGE_HEIGHT * 2);
CP15ICacheFlushBuff((unsigned int) buff_chroma[buffcount],
CAPTURE_IMAGE_WIDTH * CAPTURE_IMAGE_HEIGHT * 2);
#endif
/* Initialize buffer addresses for a new frame*/
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD,
VPIF_LUMA, (unsigned int) buff_luma[buffcount], CAPTURE_IMAGE_WIDTH*2);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD,
VPIF_CHROMA, (unsigned int) buff_chroma[buffcount], CAPTURE_IMAGE_WIDTH*2);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_BOTTOM_FIELD,
VPIF_LUMA, (unsigned int) (buff_luma[buffcount] + CAPTURE_IMAGE_WIDTH), CAPTURE_IMAGE_WIDTH*2);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_BOTTOM_FIELD,
VPIF_CHROMA, (unsigned int) (buff_chroma[buffcount] + CAPTURE_IMAGE_WIDTH), CAPTURE_IMAGE_WIDTH*2);
/* Initialize buffer addresses with the captured frame ready to be processed */
videoTopC = buff_chroma[buffcount2];
videoTopY = buff_luma[buffcount2];
captured = 1;
/* clear interrupt */
VPIFInterruptStatusClear(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0);
}
static void PWMTZIsr(void)
{
#ifdef _TMS320C6X
IntEventClear(SYS_INT_EHRPWM1TZ);
#else
IntSystemStatusClear(SYS_INT_EHRPWM1TZ);
#endif
EHRPWMTZFlagClear(SOC_EHRPWM_1_REGS, EHRPWM_TZ_CYCLEBYCYCLE_CLEAR);
}
/*
** Error ISR for McASP
*/
static void McASPErrorIsr(void)
{
#ifdef _TMS320C6X
IntEventClear(SYS_INT_MCASP0_INT);
#else
IntSystemStatusClear(SYS_INT_MCASPINT);
#endif
; /* Perform any error handling here.*/
}
/*
** ISR to handler i2c interrupts
*/
void I2CCodecIsr(void)
{
unsigned int intCode = 0;
unsigned int sysIntNum = 0;
/* Get interrupt vector code */
intCode = I2CInterruptVectorGet(savedBase);
if(SOC_I2C_0_REGS == savedBase)
{
#ifdef _TMS320C6X
sysIntNum = SYS_INT_I2C0_INT;
#else
sysIntNum = SYS_INT_I2CINT0;
#endif
}
else
{
intCode = 0;
}
while(intCode!=0)
{
/* Clear status of interrupt */
#ifdef _TMS320C6X
IntEventClear(sysIntNum);
#else
IntSystemStatusClear(sysIntNum);
#endif
if (intCode == I2C_INTCODE_TX_READY)
{
I2CMasterDataPut(savedBase, slaveData[dataIdx]);
dataIdx++;
}
if(intCode == I2C_INTCODE_RX_READY)
{
slaveData[dataIdx] = I2CMasterDataGet(savedBase);
dataIdx++;
}
if (intCode == I2C_INTCODE_STOP)
{
/* Disable transmit data ready and receive data read interupt */
I2CMasterIntDisableEx(savedBase, I2C_INT_TRANSMIT_READY
| I2C_INT_DATA_READY);
txCompFlag = 0;
}
intCode = I2CInterruptVectorGet(savedBase);
}
}
/*
** For each end of frame interrupt base and ceiling is reconfigured
*/
static void LCDIsr(void)
{
unsigned int status;
IntSystemStatusClear(SYS_INT_LCDINT);
status = RasterIntStatus(SOC_LCDC_0_REGS,RASTER_END_OF_FRAME0_INT_STAT |
RASTER_END_OF_FRAME1_INT_STAT );
status = RasterClearGetIntStatus(SOC_LCDC_0_REGS, status);
}
/*
** For each end of frame interrupt base and ceiling is reconfigured
*/
static void LCDIsr(void)
{
unsigned int status;
#ifdef _TMS320C6X
IntEventClear(SYS_INT_LCDC_INT);
#else
IntSystemStatusClear(SYS_INT_LCDINT);
#endif
/* Find which interrupt occurred and clear it */
status = RasterIntStatus(SOC_LCDC_0_REGS,
RASTER_END_OF_FRAME0_INT_STAT | RASTER_END_OF_FRAME1_INT_STAT);
status = RasterClearGetIntStatus(SOC_LCDC_0_REGS, status);
/* Display the appropriate output buffer on the appropriate raster buffer
* and if a new processed buffer is available, let the DSP know that
* it has configured the raster buffer to point to the new output buffer
* by updating the 'updated' flag */
if (display_buff_1)
{
if (status & RASTER_END_OF_FRAME0_INT_STAT)
{
RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer1,
(unsigned int) (Rgb_buffer1 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 0);
if (changed)
updated = updated | 0x1;
}
if (status & RASTER_END_OF_FRAME1_INT_STAT)
{
RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer1,
(unsigned int) (Rgb_buffer1 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 1);
if (changed)
updated = updated | 0x2;
}
}
else
{
if (status & RASTER_END_OF_FRAME0_INT_STAT)
{
RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer2,
(unsigned int) (Rgb_buffer2 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 0);
if (changed)
updated = updated | 0x1;
}
if (status & RASTER_END_OF_FRAME1_INT_STAT)
{
RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer2,
(unsigned int) (Rgb_buffer2 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 1);
if (changed)
updated = updated | 0x2;
}
}
}
/*
** This function will read/write data from/to PMIC through I2C bus.
*/
void I2CPMICInteract(void)
{
volatile unsigned int intCode = 0;
/* Get interrupt vector code */
intCode = I2CInterruptVectorGet(SOC_I2C_0_REGS);
while(intCode!=0)
{
/* Clear status of interrupt */
IntSystemStatusClear(SYS_INT_I2CINT0);
if (intCode == I2C_INTCODE_TX_READY)
{
/* Put data to data transmit register of i2c */
I2CMasterDataPut(SOC_I2C_0_REGS, dataToPmic[count++]);
}
if(intCode == I2C_INTCODE_RX_READY)
{
/* Receive data from data receive register */
dataFromSlave[rCount] = I2CMasterDataGet(SOC_I2C_0_REGS);
}
if (intCode == I2C_INTCODE_STOP)
{
/* Disable transmit data ready and receive data read interupt */
I2CMasterIntDisableEx(SOC_I2C_0_REGS,I2C_INT_TRANSMIT_READY|
I2C_INT_DATA_READY);
flag = 0;
}
if (intCode == I2C_INTCODE_NACK)
{
I2CMasterIntDisableEx(SOC_I2C_0_REGS, I2C_INT_TRANSMIT_READY |
I2C_INT_DATA_READY |
I2C_INT_NO_ACK |
I2C_INT_STOP_CONDITION);
/* Generate a STOP */
I2CMasterStop(SOC_I2C_0_REGS);
I2CStatusClear(SOC_I2C_0_REGS, I2C_CLEAR_STOP_CONDITION);
/* Clear interrupt at AINTC, if we missed any, in case of error */
flag = 0;
}
intCode = I2CInterruptVectorGet(SOC_I2C_0_REGS);
}
}
/**
* \brief The systick interrupt service routine (ISR) which will be called every millisecond
*
* This ISR will increase the systick_ms variable and reset the interrupt flags.
*
* \return none
**/
void systick_isr_C(void) {
/* Disable the timer interrupt */
TimerIntDisable(SOC_TMR_0_REGS, TMR_INT_TMR34_NON_CAPT_MODE);
/* Clear the interrupt status in AINTC and in timer */
IntSystemStatusClear(SYS_INT_TINT34_0);
TimerIntStatusClear(SOC_TMR_0_REGS, TMR_INT_TMR34_NON_CAPT_MODE);
++systick_ms;
/* Enable the timer interrupt */
TimerIntEnable(SOC_TMR_0_REGS, TMR_INT_TMR34_NON_CAPT_MODE);
}
static void PWMEventIsr(void)
{
#ifdef _TMS320C6X
IntEventClear(SYS_INT_EHRPWM1);
#else
IntSystemStatusClear(SYS_INT_EHRPWM1);
#endif
EHRPWMETIntClear(SOC_EHRPWM_1_REGS);
#ifdef SYNC_EN
EHRPWMTriggerSWSync(SOC_EHRPWM_1_REGS);
#endif
}
/*
** For each end of frame interrupt base and ceiling is reconfigured
*/
static void LCDIsr(void)
{
unsigned int status;
#ifdef _TMS320C6X
IntEventClear(SYS_INT_LCDC_INT);
#else
IntSystemStatusClear(SYS_INT_LCDINT);
#endif
status = RasterIntStatus(SOC_LCDC_0_REGS,RASTER_END_OF_FRAME0_INT_STAT |
RASTER_END_OF_FRAME1_INT_STAT );
status = RasterClearGetIntStatus(SOC_LCDC_0_REGS, status);
}
/*
** configures arm interrupt controller to generate PWM interrupts
*/
static void SetupIntc(void)
{
#ifdef _TMS320C6X
// Initialize the DSP interrupt controller
IntDSPINTCInit();
// Register the ISRs to the vector table
IntRegister(C674X_MASK_INT4, PWMEventIsr);
IntRegister(C674X_MASK_INT5, PWMTZIsr);
// Map system events to the DSP maskable interrupts
IntEventMap(C674X_MASK_INT4, SYS_INT_EHRPWM1);
IntEventMap(C674X_MASK_INT5, SYS_INT_EHRPWM1TZ);
// Enable the DSP maskable interrupts
IntEnable(C674X_MASK_INT4);
IntEnable(C674X_MASK_INT5);
// Enable DSP interrupts globally
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
IntSystemStatusClear(SYS_INT_EHRPWM1);
EHRPWMETIntClear(SOC_EHRPWM_1_REGS);
/************************PWM1****************************************/
IntRegister(SYS_INT_EHRPWM1, PWMEventIsr);
IntChannelSet(SYS_INT_EHRPWM1, 2);
IntSystemEnable(SYS_INT_EHRPWM1);
/********************************************************************/
IntRegister(SYS_INT_EHRPWM1TZ, PWMTZIsr);
IntChannelSet(SYS_INT_EHRPWM1TZ, 2);
IntSystemEnable(SYS_INT_EHRPWM1TZ);
/********************************************************************/
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}
/*
** Timer Interrupt Service Routine
*/
static void TimerIsr(void)
{
/* Disable the timer interrupt */
TimerIntDisable(SOC_TMR_2_REGS, TMR_INT_TMR12_NON_CAPT_MODE);
#ifdef _TMS320C6X
/* Clear interrupt status in DSPINTC */
IntEventClear(SYS_INT_T64P2_TINTALL);
#else
/* Clear the interrupt status in AINTC */
IntSystemStatusClear(SYS_INT_TIMR2_ALL);
#endif
TimerIntStatusClear(SOC_TMR_2_REGS, TMR_INT_TMR12_NON_CAPT_MODE);
/* Signal application to print a new character */
flagIsrCnt = 1;
/* Enable the timer interrupt */
TimerIntEnable(SOC_TMR_2_REGS, TMR_INT_TMR12_NON_CAPT_MODE);
}
static void Edma3ComplHandlerIsr(void)
{
volatile unsigned int pendingIrqs;
volatile unsigned int isIPR = 0;
volatile unsigned int indexl;
volatile unsigned int Cnt = 0;
indexl = 1;
IntSystemStatusClear(SYS_INT_CCINT0);
isIPR = EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS);
if(isIPR)
{
while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT)&& (indexl != 0))
{
indexl = 0;
pendingIrqs = EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS);
while (pendingIrqs)
{
if((pendingIrqs & 1) == TRUE)
{
/**
* If the user has not given any callback function
* while requesting the TCC, its TCC specific bit
* in the IPR register will NOT be cleared.
*/
/* Here write to ICR to clear the corresponding IPR bits. */
EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, indexl);
(*cb_Fxn[indexl])(indexl, EDMA3_XFER_COMPLETE);
}
++indexl;
pendingIrqs >>= 1;
}
Cnt++;
}
}
}
/*
** EDMA transfer completion ISR
*/
static void EDMA3CCComplIsr(void)
{
#ifdef _TMS320C6X
IntEventClear(SYS_INT_EDMA3_0_CC0_INT1);
#else
IntSystemStatusClear(SYS_INT_CCINT0);
#endif
/* Check if receive DMA completed */
if(EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS) & (1 << EDMA3_CHA_MCASP0_RX))
{
/* Clear the interrupt status for the 0th channel */
EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX);
McASPRxDMAComplHandler();
}
/* Check if transmit DMA completed */
if(EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS) & (1 << EDMA3_CHA_MCASP0_TX))
{
/* Clear the interrupt status for the first channel */
EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX);
McASPTxDMAComplHandler();
}
}
static void Edma3CCErrHandlerIsr(void)
{
volatile unsigned int pendingIrqs = 0;
unsigned int Cnt = 0;
unsigned int index = 1;
unsigned int regionNum = 0;
unsigned int evtqueNum = 0;
IntSystemStatusClear(SYS_INT_CCERRINT);
if((HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_EMR) != 0 )
|| (HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_QEMR) != 0)
|| (HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_CCERR) != 0))
{
/* Loop for EDMA3CC_ERR_HANDLER_RETRY_COUNT number of time, breaks
when no pending interrupt is found. */
while ((Cnt < EDMA3CC_ERR_HANDLER_RETRY_COUNT) && (index != 0))
{
index = 0;
pendingIrqs = HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_EMR);
while (pendingIrqs)
{
/*Process all the pending interrupts.*/
if((pendingIrqs & 1)==TRUE)
{
/* Write to EMCR to clear the corresponding EMR bits.*/
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_EMCR) = (1<<index);
/*Clear any SER*/
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_S_SECR(regionNum)) = (1<<index);
}
++index;
pendingIrqs >>= 1;
}
index = 0;
pendingIrqs = HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_QEMR);
while (pendingIrqs)
{
/*Process all the pending interrupts.*/
if((pendingIrqs & 1)==TRUE)
{
/* Here write to QEMCR to clear the corresponding QEMR bits.*/
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_QEMCR) = (1<<index);
/*Clear any QSER*/
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_S_QSECR(0)) = (1<<index);
}
++index;
pendingIrqs >>= 1;
}
index = 0;
pendingIrqs = HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_CCERR);
if(pendingIrqs != 0)
{
/* Process all the pending CC error interrupts. */
/* Queue threshold error for different event queues.*/
for (evtqueNum = 0; evtqueNum < EDMA3_0_NUM_EVTQUE; evtqueNum++)
{
if((pendingIrqs & (1 << evtqueNum)) != 0)
{
/* Clear the error interrupt. */
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_CCERRCLR) = (1 << evtqueNum);
}
}
/* Transfer completion code error. */
if ((pendingIrqs & (1 << EDMA3CC_CCERR_TCCERR_SHIFT)) != 0)
{
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_CCERRCLR) = \
(0x01 << EDMA3CC_CCERR_TCCERR_SHIFT);
}
++index;
}
Cnt++;
}
}
}
//*****************************************************************************
//
//! The USB device interrupt handler.
//!
//! This the main USB interrupt handler entry point for use in USB device
//! applications. This top-level handler will branch the interrupt off to the
//! appropriate application or stack handlers depending on the current status
//! of the USB controller.
//!
//! Applications which operate purely as USB devices (rather than dual mode
//! applications which can operate in either device or host mode at different
//! times) must ensure that a pointer to this function is installed in the
//! interrupt vector table entry for the USB0 interrupt. For dual mode
//! operation, the vector should be set to point to \e USB0DualModeIntHandler()
//! instead.
//!
//! \return None.
//
//*****************************************************************************
void
USB0DeviceIntHandler(void)
{
unsigned int ulStatus = 0;
#if defined(am335x) || defined (am335x_15x15) || defined(c6a811x) || defined(am386x) || \
defined(c6741x)
unsigned int epStatus = 0;
//
// Get the controller interrupt status.
//
ulStatus = HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_IRQ_STATUS_1);
//
// Get the EP interrupt status.
//
epStatus = HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_IRQ_STATUS_0);
//
// Clear the controller interrupt status.
//
HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_IRQ_STATUS_1) = ulStatus;
//
// Clear the EP interrupt status.
//
HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_IRQ_STATUS_0) = epStatus;
#ifdef DMA_MODE
HWREG(USBSS_BASE + USBSS_IRQ_STATUS) =
HWREG(USBSS_BASE + USBSS_IRQ_STATUS);
#endif
//
//Call the Interrupt Handler.
//
USBDeviceIntHandlerInternal(0, ulStatus, &epStatus);
//
//End of Interrupts.
//
HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_IRQ_EOI) = 0;
#ifdef DMA_MODE
HWREG(USBSS_BASE + USBSS_IRQ_EOI) = 0;
#endif
#else
//
// Get the controller interrupt status.
//
ulStatus = HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_INTR_SRC);
// Clear the Interrupts
HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_INTR_SRC_CLEAR) = ulStatus;
#ifdef _TMS320C6X
IntEventClear(g_USBInstance[0].uiInterruptNum);
#else
IntSystemStatusClear(g_USBInstance[0].uiInterruptNum);
#endif
//
// Call the internal handler.
//
USBDeviceIntHandlerInternal(0, ulStatus, NULL);
// End of Interrupts
HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_END_OF_INTR) = 0;
#endif
}
/*
** ISR to handler i2c interrupts
*/
static void I2C0Isr(void)
{
volatile unsigned int intCode = 0;
/* Get interrupt vector code */
intCode = I2CInterruptVectorGet(SOC_I2C_0_REGS);
while(intCode!=0)
{
/* Clear status of interrupt */
#ifdef _TMS320C6X
IntEventClear(SYS_INT_I2C0_INT);
#else
IntSystemStatusClear(15);
#endif
if (intCode == I2C_INTCODE_TX_READY)
{
I2CMasterDataPut(SOC_I2C_0_REGS, slaveData[dataIdx]);
dataIdx++;
}
if(intCode == I2C_INTCODE_RX_READY)
{
slaveData[dataIdx] = I2CMasterDataGet(SOC_I2C_0_REGS);
dataIdx++;
}
if (intCode == I2C_INTCODE_STOP)
{
I2CMasterIntDisableEx(SOC_I2C_0_REGS, I2C_INT_TRANSMIT_READY |
I2C_INT_DATA_READY |
I2C_INT_NO_ACK |
I2C_INT_STOP_CONDITION);
txCompFlag = 0;
}
if (intCode == I2C_INTCODE_NACK)
{
I2CMasterIntDisableEx(SOC_I2C_0_REGS, I2C_INT_TRANSMIT_READY |
I2C_INT_DATA_READY |
I2C_INT_NO_ACK |
I2C_INT_STOP_CONDITION);
/* Generate a STOP */
I2CMasterStop(SOC_I2C_0_REGS);
I2CStatusClear(SOC_I2C_0_REGS, I2C_CLEAR_STOP_CONDITION);
/* Clear interrupt at AINTC, if we missed any, in case of error */
#ifdef _TMS320C6X
IntEventClear(SYS_INT_I2C0_INT);
#else
IntSystemStatusClear(15);
#endif
txCompFlag = 0;
}
if (I2CMasterIntStatus(SOC_I2C_0_REGS) & I2C_ICSTR_NACKSNT)
{
I2CMasterIntDisableEx(SOC_I2C_0_REGS, I2C_INT_TRANSMIT_READY |
I2C_INT_DATA_READY |
I2C_INT_NO_ACK |
I2C_INT_STOP_CONDITION);
/* Generate a STOP */
I2CMasterStop(SOC_I2C_0_REGS);
I2CStatusClear(SOC_I2C_0_REGS, (I2C_CLEAR_NO_ACK_SENT |
I2C_CLEAR_STOP_CONDITION));
/* Clear interrupt at AINTC, if we missed any, in case of error */
#ifdef _TMS320C6X
IntEventClear(SYS_INT_I2C0_INT);
#else
IntSystemStatusClear(15);
#endif
txCompFlag = 0;
}
intCode = I2CInterruptVectorGet(SOC_I2C_0_REGS);
}
}
void UARTIsr()
{
//static unsigned int length = sizeof(txArray);
//static unsigned int count = 0;
char rxData = 0;
unsigned int int_id = 0;
static char *inBufferPtr = inBuffer;
static char traceBuf[2] = {'\0', '\0'};
do {
/* This determines the cause of UART2 interrupt.*/
int_id = UARTIntStatus(SOC_UART_2_REGS);
#ifdef _TMS320C6X
// Clear UART2 system interrupt in DSPINTC
IntEventClear(SYS_INT_UART2_INT);
#else
/* Clears the system interupt status of UART2 in AINTC. */
IntSystemStatusClear(SYS_INT_UARTINT2);
#endif
#if 0
/* Checked if the cause is transmitter empty condition.*/
if(UART_INTID_TX_EMPTY == int_id)
{
if(0 < length)
{
/* Write a byte into the THR if THR is free. */
UARTCharPutNonBlocking(SOC_UART_2_REGS, txArray[count]);
length--;
count++;
}
if(0 == length)
{
/* Disable the Transmitter interrupt in UART.*/
UARTIntDisable(SOC_UART_2_REGS, UART_INT_TX_EMPTY);
}
}
#endif
/* Check if the cause is receiver data condition.*/
if(UART_INTID_RX_DATA == int_id)
{
rxData = UARTCharGetNonBlocking(SOC_UART_2_REGS);
if (uartNewString == 0) {
if (rxData == '\r') {
*inBufferPtr = '\0';
uartNewString = 1;
inBufferPtr = inBuffer;
/* Disable the Receiver interrupt in UART.*/
//UARTIntDisable(SOC_UART_2_REGS, UART_INT_RXDATA_CTI);
} else {
*inBufferPtr = rxData;
inBufferPtr++;
if (inBufferPtr >= (inBuffer + inBufferSize))
inBufferPtr--;
else {
*traceBuf = rxData;
trace(traceBuf);
}
}
}
//UARTCharPutNonBlocking(SOC_UART_2_REGS, rxData);
}
/* Check if the cause is receiver line error condition.*/
if(UART_INTID_RX_LINE_STAT == int_id)
{
while(UARTRxErrorGet(SOC_UART_2_REGS))
{
/* Read a byte from the RBR if RBR has data.*/
UARTCharGetNonBlocking(SOC_UART_2_REGS);
}
}
} while (int_id);
return;
}
